Arquitetura de Processadores-Implementacao MIPS e Conceitos Basicos

Capítulo 4 O Processador Introdução Fatores de desempenho de uma CPU Número de Instruções Determinada pelo ISA e pelo compilador CPI e Ciclo Determinada pelo hardware CPU Vamos examinar três implementações MIPS Uma versão simplificada Uma versão mais realista Uma versão mais realista com pipeline Subconjunto simples mas suficiente para o estudo Referencia à memoria lw sw Aritméticalogica add sub and or slt Transferência de controle beq j Ricardo Pannain 2023 2 Execução de uma Instrução PC memória de instrução fetch da instrução Números de Registradores banco de registradores leitura de registradores Dependência da classe de instrução Usa a ULA para calcular Resultado aritmético Endereço de memória para loadstore Endereço alvo de branch Acesso á memória de dados para loadstore PC endereço alvo ou PC 4 Ricardo Pannain 2023 3 Conceitos Básicos de Projeto Lógico Informação codificada em binário Low voltage 0 High voltage 1 Um fio por bit Dados multibit codificados em barramentos multi wire Elemento combinacional Opera sobre o dado A saída é função das entradas Elementos de estado sequenciais Armazena informação Ricardo Pannain 2023 4 Elementos Combinacionais AND Y A B Ricardo Pannain 2023 A B Y I0 I1 Y M u x S Multiplexador Y S I1 I0 A B Y A B Y ALU F Adder Y A B ArithmeticLogic Unit Y FA B 5 Elementos Sequenciais Registrador armazena dados em um circuito Usa um sinal de clock para determinar quando o valor armazenado será atualizado Edgetriggered atualiza quando Clk muda de 0 para 1 Ricardo Pannain 2023 D Clk Q Clk D Q 6 Elementos Sequenciais Registrador controle de escrita Somente atualiza na subida do clock quando o controle de escrita é 1 Usado quando o valor a ser armazenado é necessário em um determinado tempo Ricardo Pannain 2023 D Clk Q Write Write D Q Clk 7 Metodologia que Utiliza o Clock Lógica combinacional que transforma dados durante o ciclo de clock Entre duas subidas do clock Entrada do elemento de estado saída para o elemento de estado Atrasos longos determinam o período do clock Ricardo Pannain 2023 8 Construindo um Datapath Datapath Elementos que processam dados e endereços na CPU Registradores ALUs muxs memorias Iremos construir um datapath MIPS de maneira incremental Refinando o projeto Ricardo Pannain 2023 9 Fetch da Instrução Ricardo Pannain 2023 Registrador de 32 bits Soma 4 para a próxima instrução 10 Instruções Formato R Lê dois operandos registradores Faz operações aritméticaslogicas Escreve o resultado em um registrador Ricardo Pannain 2023 11 Instruções LoadStore Lê operandos registradores Calcula o endereço usando offset de 16 bits Usa ALU com offset signextend Load Lê da memoria e atualiza o registrador Store Escreve o valor do registrador na memória Ricardo Pannain 2023 12 Instruções de Desvio Lê dois operandos registradores Compara operandos Usa ALU subtrai e verifica a saída Zero Calcula o endereço alvo Deslocamento signextend Shift left 2 posições aponta para o primeiro byte da palavra Soma com PC 4 Já calculado no fetch da instrução Ricardo Pannain 2023 13 Instruções de Desvio Ricardo Pannain 2023 Replicação do bit de sinal 14 Compondo os Elementos Primeiramente um datapath que executa uma instrução em um ciclo de clock Cada elemento pode executar somente uma função por vez Entretanto precisamos separar as memórias de instruções e dados Usar multiplexadores onde fontes de dados alternados são usados para diferentes instruções Ricardo Pannain 2023 15 Datapath Tipo RLoadStore Ricardo Pannain 2023 16 Datapath Completo Ricardo Pannain 2023 17 Controle da ALU ALU usada para LoadStore F add Branch F subtract Rtype F depende do campo funct Ricardo Pannain 2023 ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 setonlessthan 1100 NOR 18 Controle da ALU Assumir ALUOp com 2 bits derivados do opcode Controle da ALU Lógica combinacional Ricardo Pannain 2023 opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 Rtype 10 add 100000 add 0010 subtract 100010 subtract 0110 AND 100100 AND 0000 OR 100101 OR 0001 setonlessthan 101010 setonlessthan 0111 19 Unidade de Controle Principal Sinais de controle são derivados das instruções Ricardo Pannain 2023 0 rs rt rd shamt funct 3126 50 2521 2016 1511 106 35 or 43 rs rt address 3126 2521 2016 150 4 rs rt address 3126 2521 2016 150 Rtype Load Store Branch opcode Sempre leitura leitura exceto para load Escrita para Tipo R e load signextend e soma 20 Datapath com Controle Ricardo Pannain 2023 21 Instrução Tipo R Ricardo Pannain 2023 22 Instrução Load Ricardo Pannain 2023 23 Instrução BranchonEqual Ricardo Pannain 2023 24 Implementando Jumps Jump usa palavra de word Atualiza PC com a concatenação dos 4 bits mais significativos do PC 26 bits do endereço do jump campo address 00 Necessita de um sinal extra de controle decodificado do opcode Ricardo Pannain 2023 2 address 3126 250 Jump 25 Datapath com Jumps Ricardo Pannain 2023 26 Exercícios monociclo Ricardo Pannain 2023 27 tipo R sw lw beq j MemRead 0 0 1 0 0 MemWrite 0 1 0 0 0 MemToReg 0 X 1 X X ALUop 10 00 00 01 XX ALUSrc 0 1 1 0 X RegWrite 1 0 1 0 0 RegDst 1 X 0 X X Jump 0 0 0 0 1 Branch 0 0 0 1 0 Gerar os sinais de controle para as instruções Tipo R sw lw beq j OBS Sinais gerados em um período de clock Datapath Multiciclo Ricardo Pannain 2023 28 Shift left 2 PC Memory MemData Write data M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 M u x 0 1 M u x 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register 1 M u x 0 3 2 M u x ALU result ALU Zero Memory data register Instruction 1511 A B ALUOut 0 1 Address Datapath Multiciclo Sinais de Controle Shift left 2 MemtoReg IorD MemRead MemWrite PC Memory MemData Write data M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 M u x 0 1 M u x 0 1 4 ALUOp ALUSrcB RegDst RegWrite Instruction 150 Instruction 5 0 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register 1 M u x 0 3 2 ALU control M u x 0 1 ALU result ALU ALUSrcA Zero A B ALUOut IRWrite Address Memory data register Ricardo Pannain 2023 29 Datapath multiciclo com sinais de controle completo incluindo atualização do PC Shift left 2 PC M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 M u x 0 1 M u x 0 1 4 Instruction 15 0 Sign extend 32 16 Instruction 25 21 Instruction 20 16 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 M u x 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 M u x 0 3 2 M u x 0 1 ALUOut Memory MemData Write data Address Ricardo Pannain 2023 30 31 Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 Mux 0 1 Mux 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address Ricardo Pannain 2023 1 Escrever os sinais de controle para as instruções Tipo R sw lw beq e j 32 Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 Mux 0 1 Mux 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address tipo R 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo 5o Ciclo PCWriteCond 0 0 0 0 PCWrite 1 0 0 0 IorD 0 X X X MemRead 1 0 0 0 MemWrite 0 0 0 0 MemToReg X X X 0 IRWrite 1 0 0 0 PCSource 0 X X X ALUop 00 00 10 XX ALUSrcA 0 0 1 X ALUSrcB 01 11 00 XX RegWrite 0 0 0 1 RegDst X X X 1 Ricardo Pannain 2023 33 Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 Mux 0 1 Mux 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address SW 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo 5o Ciclo PCWriteCond 0 0 0 0 PCWrite 1 0 0 0 IorD 0 X X 1 MemRead 1 0 0 0 MemWrite 0 0 0 1 MemToReg X X X X IRWrite 1 0 0 0 PCSource 0 X X X ALUop 00 00 00 XX ALUSrcA 0 0 1 X ALUSrcB 01 11 10 X RegWrite 0 0 0 0 RegDst X X X X Ricardo Pannain 2023 34 Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 Mux 0 1 Mux 0 1 4 Instruction 15 0 Sign extend 32 16 Instruction 25 21 Instruction 20 16 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address LW 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo 5o Ciclo PCWriteCond 0 0 0 0 0 PCWrite 1 0 0 0 0 IorD 0 X X 1 X MemRead 1 0 0 1 0 MemWrite 0 0 0 0 0 MemToReg X X X X 1 IRWrite 1 0 0 0 0 PCSource 0 X X X X ALUop 00 00 00 XX XX ALUSrcA 0 0 1 X X ALUSrcB 01 11 10 XX XX RegWrite 0 0 0 0 1 RegDst X X X X 0 Ricardo Pannain 2023 35 Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 Mux 0 1 Mux 0 1 4 Instruction 15 0 Sign extend 32 16 Instruction 25 21 Instruction 20 16 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address BEQ 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo 5o Ciclo PCWriteCond 0 0 1 PCWrite 1 0 0 IorD 0 X X MemRead 1 0 0 MemWrite 0 0 0 MemToReg X X X IRWrite 1 0 0 PCSource 0 X 1 ALUop 00 00 01 ALUSrcA 0 0 1 ALUSrcB 01 11 00 RegWrite 0 0 0 RegDst X X X Ricardo Pannain 2023 36 Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 Mux 0 1 Mux 0 1 4 Instruction 15 0 Sign extend 32 16 Instruction 25 21 Instruction 20 16 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address J 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo 5o Ciclo PCWriteCond 0 0 0 PCWrite 1 0 1 IorD 0 X 0 MemRead 1 0 0 MemWrite 0 0 0 MemToReg X X 0 IRWrite 1 0 0 PCSource 0 X 10 ALUop 00 00 XX ALUSrcA 0 0 X ALUSrcB 01 11 XX RegWrite 0 0 0 RegDst X X X Ricardo Pannain 2023 37 Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 15 11 Mux 0 1 Mux 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 5 0 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address Ricardo Pannain 2023 2 Executar o jr reg 38 jr reg PC reg Instrução tipo R reg é o rs Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 1511 Mux 0 1 Mux 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 50 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address 3 JR sem alteração datapath 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo 5o Ciclo PCWriteCond 0 0 0 PCWrite 1 0 1 IorD 0 X X MemRead 1 0 0 MemWrite 0 0 0 MemToReg X X X IRWrite 1 0 0 PCSource 0 X 0 ALUop 00 00 00 ALUSrcA 0 0 1 ALUSrcB 01 11 00 RegWrite 0 0 0 RegDst X X X Ricardo Pannain 2023 39 JR com alteração datapath 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo 5o Ciclo PCWriteCond 0 0 0 PCWrite 1 0 1 IorD 0 X X MemRead 1 0 0 MemWrite 0 0 0 MemToReg X X X IRWrite 1 0 0 PCSource 00 XX 11 ALUop 00 00 XX ALUSrcA 0 0 X ALUSrcB 01 11 XX RegWrite 0 0 0 RegDst X X X jr reg PC reg Instrução tipo R reg é o rs Shift left 2 PC Mux 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction 1511 Mux 0 1 Mux 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 5 0 Instruction 3126 Instruction 50 Mux 0 2 Jump address 310 Instruction 250 26 28 Shift left 2 PC 3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address 3 Ricardo Pannain 2023 XCHG 40 XCHG datapath 1o Ciclo 2o Ciclo 3o Ciclo 4o Ciclo PCWriteCond 0 0 0 0 PCWrite 1 0 0 0 IorD 0 X X X MemRead 1 0 0 0 MemWrite 0 0 0 0 MemToReg XX XX 00 10 IRWrite 1 0 0 0 PCSource 0 X 0 0 ALUop 00 00 XX XX ALUSrcA 0 0 X X ALUSrcB 01 11 XX XX RegWrite 0 0 0 0 RegDst XX XX 10 11 Shift left2 PC Mux 0 1 Registers Write register Write data Read data1 Read data2 Read register1 Read register2 Instruction 1511 Mux 0 1 Mux 0 1 4 Instruction 150 Sign extend 32 16 Instruction 2521 Instruction 2016 Instruction 150 Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op 50 Instruction 3126 Instruction50 Mux 0 2 Jump address310 Instruction250 26 Shift 28 left2 PC3128 1 1 Mux 0 3 2 Mux 0 1 ALUOut Memory MemData Write data Address Ricardo Pannain 2023 Tabela com Sinais de Controle Ricardo Pannain 2023 41 Tabela com Sinais de Controle Ricardo Pannain 2023 42 Datapath Multiciclo Ciclos e Execução da Instrução Ricardo Pannain 2023 43