Datasheet for STM32F103x8 and STM32F103xB 32-bit Microcontroller

This is information on a product in full production August 2015 DocID13587 Rev 17 1117 STM32F103x8 STM32F103xB Mediumdensity performance line ARMbased 32bit MCU with 64 or 128 KB Flash USB CAN 7 timers 2 ADCs 9 com interfaces Datasheet production data Features ARM 32bit CortexM3 CPU Core 72 MHz maximum frequency 125 DMIPSMHz Dhrystone 21 performance at 0 wait state memory access Singlecycle multiplication and hardware division Memories 64 or 128 Kbytes of Flash memory 20 Kbytes of SRAM Clock reset and supply management 20 to 36 V application supply and IOs POR PDR and programmable voltage detector PVD 4to16 MHz crystal oscillator Internal 8 MHz factorytrimmed RC Internal 40 kHz RC PLL for CPU clock 32 kHz oscillator for RTC with calibration Lowpower Sleep Stop and Standby modes VBAT supply for RTC and backup registers 2 x 12bit 1 µs AD converters up to 16 channels Conversion range 0 to 36 V Dualsample and hold capability Temperature sensor DMA 7channel DMA controller Peripherals supported timers ADC SPIs I2Cs and USARTs Up to 80 fast IO ports 26375180 IOs all mappable on 16 external interrupt vectors and almost all 5 Vtolerant Debug mode Serial wire debug SWD JTAG interfaces 7 timers Three 16bit timers each with up to 4 ICOCPWM or pulse counter and quadrature incremental encoder input 16bit motor control PWM timer with dead time generation and emergency stop 2 watchdog timers Independent and Window SysTick timer 24bit downcounter Up to 9 communication interfaces Up to 2 x I2C interfaces SMBusPMBus Up to 3 USARTs ISO 7816 interface LIN IrDA capability modem control Up to 2 SPIs 18 Mbits CAN interface 20B Active USB 20 fullspeed interface CRC calculation unit 96bit unique ID Packages are ECOPACK Table 1 Device summary Reference Part number STM32F103x8 STM32F103C8 STM32F103R8 STM32F103V8 STM32F103T8 STM32F103xB STM32F103RB STM32F103VB STM32F103CB STM32F103TB BGA100 10 10 mm UFBGA100 7 x 7 mm BGA64 5 5 mm VFQFPN36 6 6 mm LQFP100 14 14 mm LQFP64 10 10 mm LQFP48 7 7 mm UFQFPN48 7 7 mm wwwstcom Contents STM32F103x8 STM32F103xB 2117 DocID13587 Rev 17 Contents 1 Introduction 9 2 Description 9 21 Device overview 10 22 Full compatibility throughout the family 13 23 Overview 14 231 ARM CortexM3 core with embedded Flash and SRAM 14 232 Embedded Flash memory 14 233 CRC cyclic redundancy check calculation unit 14 234 Embedded SRAM 14 235 Nested vectored interrupt controller NVIC 14 236 External interruptevent controller EXTI 15 237 Clocks and startup 15 238 Boot modes 15 239 Power supply schemes 15 2310 Power supply supervisor 15 2311 Voltage regulator 16 2312 Lowpower modes 16 2313 DMA 17 2314 RTC realtime clock and backup registers 17 2315 Timers and watchdogs 17 2316 I²C bus 19 2317 Universal synchronousasynchronous receiver transmitter USART 19 2318 Serial peripheral interface SPI 19 2319 Controller area network CAN 19 2320 Universal serial bus USB 19 2321 GPIOs generalpurpose inputsoutputs 20 2322 ADC analogtodigital converter 20 2323 Temperature sensor 20 2324 Serial wire JTAG debug port SWJDP 20 3 Pinouts and pin description 21 4 Memory mapping 34 DocID13587 Rev 17 3117 STM32F103x8 STM32F103xB Contents 4 5 Electrical characteristics 35 51 Parameter conditions 35 511 Minimum and maximum values 35 512 Typical values 35 513 Typical curves 35 514 Loading capacitor 35 515 Pin input voltage 35 516 Power supply scheme 36 517 Current consumption measurement 36 52 Absolute maximum ratings 37 53 Operating conditions 38 531 General operating conditions 38 532 Operating conditions at powerup powerdown 39 533 Embedded reset and power control block characteristics 40 534 Embedded reference voltage 41 535 Supply current characteristics 41 536 External clock source characteristics 51 537 Internal clock source characteristics 55 538 PLL characteristics 57 539 Memory characteristics 57 5310 EMC characteristics 58 5311 Absolute maximum ratings electrical sensitivity 60 5312 IO current injection characteristics 61 5313 IO port characteristics 62 5314 NRST pin characteristics 67 5315 TIM timer characteristics 68 5316 Communications interfaces 69 5317 CAN controller area network interface 74 5318 12bit ADC characteristics 75 5319 Temperature sensor characteristics 79 6 Package information 80 61 VFQFPN36 6 x 6 mm 05 mm pitch package information 80 62 UFQFPN48 7 x 7 mm 05 mm pitch package information 84 63 LFBGA100 10 x 10 mm lowprofile fine pitch ball grid array package information 87 Contents STM32F103x8 STM32F103xB 4117 DocID13587 Rev 17 64 LQFP100 14 x 14 mm 100pin lowprofile quad flat package information 90 65 UFBGA100 7x 7 mm ultra fine pitch ball grid array package information 93 66 LQFP64 10 x 10 mm 64pin lowprofile quad flat package information 96 67 TFBGA64 5 x 5 mm thin profile fine pitch package information 99 68 LQFP48 7 x 7 mm 48pin lowprofile quad flat package information 102 69 Thermal characteristics 105 691 Reference document 105 692 Selecting the product temperature range 106 7 Ordering information scheme 108 8 Revision history 109 DocID13587 Rev 17 5117 STM32F103x8 STM32F103xB List of tables 6 List of tables Table 1 Device summary 1 Table 2 STM32F103xx mediumdensity device features and peripheral counts 10 Table 3 STM32F103xx family 13 Table 4 Timer feature comparison 17 Table 5 Mediumdensity STM32F103xx pin definitions 28 Table 6 Voltage characteristics 37 Table 7 Current characteristics 37 Table 8 Thermal characteristics 38 Table 9 General operating conditions 38 Table 10 Operating conditions at powerup powerdown 39 Table 11 Embedded reset and power control block characteristics 40 Table 12 Embedded internal reference voltage 41 Table 13 Maximum current consumption in Run mode code with data processing running from Flash 42 Table 14 Maximum current consumption in Run mode code with data processing running from RAM 42 Table 15 Maximum current consumption in Sleep mode code running from Flash or RAM 44 Table 16 Typical and maximum current consumptions in Stop and Standby modes 45 Table 17 Typical current consumption in Run mode code with data processing running from Flash 48 Table 18 Typical current consumption in Sleep mode code running from Flash or RAM 49 Table 19 Peripheral current consumption 50 Table 20 Highspeed external user clock characteristics 51 Table 21 Lowspeed external user clock characteristics 52 Table 22 HSE 416 MHz oscillator characteristics 53 Table 23 LSE oscillator characteristics fLSE 32768 kHz 54 Table 24 HSI oscillator characteristics 56 Table 25 LSI oscillator characteristics 56 Table 26 Lowpower mode wakeup timings 57 Table 27 PLL characteristics 57 Table 28 Flash memory characteristics 57 Table 29 Flash memory endurance and data retention 58 Table 30 EMS characteristics 59 Table 31 EMI characteristics 59 Table 32 ESD absolute maximum ratings 60 Table 33 Electrical sensitivities 60 Table 34 IO current injection susceptibility 61 Table 35 IO static characteristics 62 Table 36 Output voltage characteristics 65 Table 37 IO AC characteristics 66 Table 38 NRST pin characteristics 67 Table 39 TIMx characteristics 68 Table 40 I2C characteristics 69 Table 41 SCL frequency fPCLK1 36 MHzVDDI2C 33 V 70 Table 42 SPI characteristics 71 Table 43 USB startup time 73 Table 44 USB DC electrical characteristics 74 List of tables STM32F103x8 STM32F103xB 6117 DocID13587 Rev 17 Table 45 USB Fullspeed electrical characteristics 74 Table 46 ADC characteristics 75 Table 47 RAIN max for fADC 14 MHz 76 Table 48 ADC accuracy limited test conditions 76 Table 49 ADC accuracy 77 Table 50 TS characteristics 79 Table 51 VFQFPN36 36pin 6x6 mm 05 mm pitch very thin profile fine pitch quad flat package mechanical data 81 Table 52 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package mechanical data 84 Table 53 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x 10 mm 08 mm pitch package mechanical data 87 Table 54 LFBGA100 recommended PCB design rules 08 mm pitch BGA 88 Table 55 LQPF100 14 x 14 mm 100pin lowprofile quad flat package mechanical data 90 Table 56 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package mechanical data 93 Table 57 UFBGA100 recommended PCB design rules 05 mm pitch BGA 94 Table 58 LQFP64 64pin 10 x 10 mm lowprofile quad flat package mechanical data 96 Table 59 TFBGA64 64ball 5 x 5 mm 05 mm pitch thin profile fine pitch ball grid array package mechanical data 99 Table 60 TFBGA64 recommended PCB design rules 05 mm pitch BGA 100 Table 61 LQFP48 48pin 7 x 7 mm lowprofile quad flat package mechanical data 102 Table 62 Package thermal characteristics 105 Table 63 Ordering information scheme 108 Table 64 Document revision history 109 DocID13587 Rev 17 7117 STM32F103x8 STM32F103xB List of figures 8 List of figures Figure 1 STM32F103xx performance line block diagram 11 Figure 2 Clock tree 12 Figure 3 STM32F103xx performance line LFBGA100 ballout 21 Figure 4 STM32F103xx performance line LQFP100 pinout 22 Figure 5 STM32F103xx performance line UFBGA100 pinout 23 Figure 6 STM32F103xx performance line LQFP64 pinout 24 Figure 7 STM32F103xx performance line TFBGA64 ballout 25 Figure 8 STM32F103xx performance line LQFP48 pinout 26 Figure 9 STM32F103xx performance line UFQFPN48 pinout 26 Figure 10 STM32F103xx performance line VFQFPN36 pinout 27 Figure 11 Memory map 34 Figure 12 Pin loading conditions 35 Figure 13 Pin input voltage 35 Figure 14 Power supply scheme 36 Figure 15 Current consumption measurement scheme 36 Figure 16 Typical current consumption in Run mode versus frequency at 36 V code with data processing running from RAM peripherals enabled 43 Figure 17 Typical current consumption in Run mode versus frequency at 36 V code with data processing running from RAM peripherals disabled 43 Figure 18 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values 45 Figure 19 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD 33 V and 36 V 46 Figure 20 Typical current consumption in Stop mode with regulator in Lowpower mode versus temperature at VDD 33 V and 36 V 46 Figure 21 Typical current consumption in Standby mode versus temperature at VDD 33 V and 36 V 47 Figure 22 Highspeed external clock source AC timing diagram 52 Figure 23 Lowspeed external clock source AC timing diagram 53 Figure 24 Typical application with an 8 MHz crystal 54 Figure 25 Typical application with a 32768 kHz crystal 55 Figure 26 Standard IO input characteristics CMOS port 63 Figure 27 Standard IO input characteristics TTL port 63 Figure 28 5 V tolerant IO input characteristics CMOS port 64 Figure 29 5 V tolerant IO input characteristics TTL port 64 Figure 30 IO AC characteristics definition 67 Figure 31 Recommended NRST pin protection 68 Figure 32 I2C bus AC waveforms and measurement circuit 70 Figure 33 SPI timing diagram slave mode and CPHA 0 72 Figure 34 SPI timing diagram slave mode and CPHA 11 72 Figure 35 SPI timing diagram master mode1 73 Figure 36 USB timings definition of data signal rise and fall time 74 Figure 37 ADC accuracy characteristics 77 Figure 38 Typical connection diagram using the ADC 78 Figure 39 Power supply and reference decoupling VREF not connected to VDDA 78 Figure 40 Power supply and reference decoupling VREF connected to VDDA 79 Figure 41 VFQFPN36 36pin 6x6 mm 05 mm pitch very thin profile fine pitch quad flat package outline 80 List of figures STM32F103x8 STM32F103xB 8117 DocID13587 Rev 17 Figure 42 VFQFPN36 36pin 6x6 mm 05 mm pitch very thin profile fine pitch quad flat package recommended footprint 82 Figure 43 VFPFPN36 package top view example 83 Figure 44 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package outline 84 Figure 45 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package recommended footprint 85 Figure 46 UFQFPN48 7 x 7 mm 05 mm pitch package top view example 86 Figure 47 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x10 mm 08 mm pitch package outline 87 Figure 48 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x 10 mm 08 mm pitch package recommended footprint 88 Figure 49 LFBGA100 package top view example 89 Figure 50 LQFP100 14 x 14 mm 100pin lowprofile quad flat package outline 90 Figure 51 LQFP100 100pin 14 x 14 mm lowprofile quad flat package recommended footprint 91 Figure 52 LQFP100 package top view example 92 Figure 53 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package outline 93 Figure 54 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package recommended footprint 94 Figure 55 UFBGA100 package top view example 95 Figure 56 LQFP64 64pin 10 x 10 mm lowprofile quad flat package outline 96 Figure 57 LQFP64 64pin 10 x 10 mm lowprofile quad flat package recommended footprint 97 Figure 58 LQFP64 package top view example 98 Figure 59 TFBGA64 64ball 5 x 5 mm 05 mm pitch thin profile fine pitch ball grid array package outline 99 Figure 60 TFBGA64 64ball 5 x 5 mm 05 mm pitch thin profile fine pitch ball grid array package recommended footprint 100 Figure 61 TFBGA64 package top view example 101 Figure 62 LQFP48 48pin 7 x 7 mm lowprofile quad flat package outline 102 Figure 63 LQFP48 48pin 7 x 7 mm lowprofile quad flat package recommended footprint 103 Figure 64 LQFP48 package top view example 104 Figure 65 LQFP100 PD max vs TA 107 DocID13587 Rev 17 9117 STM32F103x8 STM32F103xB Introduction 116 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB mediumdensity performance line microcontrollers For more details on the whole STMicroelectronics STM32F103xx family please refer to Section 22 Full compatibility throughout the family The mediumdensity STM32F103xx datasheet should be read in conjunction with the low medium and highdensity STM32F10xxx reference manual The reference and Flash programming manuals are both available from the STMicroelectronics website wwwstcom For information on the CortexM3 core please refer to the CortexM3 Technical Reference Manual available from the wwwarmcom website 2 Description The STM32F103xx mediumdensity performance line family incorporates the high performance ARM CortexM3 32bit RISC core operating at a 72 MHz frequency high speed embedded memories Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes and an extensive range of enhanced IOs and peripherals connected to two APB buses All devices offer two 12bit ADCs three general purpose 16bit timers plus one PWM timer as well as standard and advanced communication interfaces up to two I2Cs and SPIs three USARTs an USB and a CAN The devices operate from a 20 to 36 V power supply They are available in both the 40 to 85 C temperature range and the 40 to 105 C extended temperature range A comprehensive set of powersaving mode allows the design of lowpower applications The STM32F103xx mediumdensity performance line family includes devices in six different package types from 36 pins to 100 pins Depending on the device chosen different sets of peripherals are included the description below gives an overview of the complete range of peripherals proposed in this family These features make the STM32F103xx mediumdensity performance line microcontroller family suitable for a wide range of applications such as motor drives application control medical and handheld equipment PC and gaming peripherals GPS platforms industrial applications PLCs inverters printers scanners alarm systems video intercoms and HVACs Description STM32F103x8 STM32F103xB 10117 DocID13587 Rev 17 21 Device overview Table 2 STM32F103xx mediumdensity device features and peripheral counts Peripheral STM32F103Tx STM32F103Cx STM32F103Rx STM32F103Vx Flash Kbytes 64 128 64 128 64 128 64 128 SRAM Kbytes 20 20 20 20 Timers Generalpurpose 3 3 3 3 Advancedcontrol 1 1 1 1 Communication SPI 1 2 2 2 I2C 1 2 2 2 USART 2 3 3 3 USB 1 1 1 1 CAN 1 1 1 1 GPIOs 26 37 51 80 12bit synchronized ADC Number of channels 2 10 channels 2 10 channels 2 16 channels1 1 On the TFBGA64 package only 15 channels are available one analog input pin has been replaced by Vref 2 16 channels CPU frequency 72 MHz Operating voltage 20 to 36 V Operating temperatures Ambient temperatures 40 to 85 C 40 to 105 C see Table 9 Junction temperature 40 to 125 C see Table 9 Packages VFQFPN36 LQFP48 UFQFPN48 LQFP64 TFBGA64 LQFP100 LFBGA100 UFBGA100 STM32F103x8 STM32F103xB Description Figure 1 STM32F103xx performance line block diagram TRACECLK TRACED03 o Trace as AS Tracetrig s POWER NuTRST VOLT REG Vop 2 to 36V JTDI ie Vv JTCKSWCLK CortexM3 CPU bs 3 g Flash 128 KB 33V TO 18V ss JTMSSWDIO JTDO gs 64 bit VvDD as AE Fax 72MHz K bas cH 2s SRAM NVIC KS 20KB evop PCLK1 9868 PLL XTAL OSC OSCOUT GP OMA ly Puke Glock Je reine PLoS 7 channels z FCLK MANAGT LRC 8 MHz 8 IWDG VDDA il RC 40 kHz vpDA Standby SUPPLY us 1 interface Bar NRST SUPERVISION eS VBAT x VDDA POR PDR Rst OSC32IN VSSA XTAL 32 kHz O8C32 OUT PVD Int AHB2 AHB2 APB2 APB1 RTC Backup AWwU seg TAMPERRTC seule K WAKEUP od by cS Backup interface PA 150 GPIOA ALS 4 channels PB150 PC150 GPIOC PD150 150 GPIOD RXTX CTS RTS N 1 susant2 Kea cs SmartCardas AF PE150t GPIOE ls x UA Usanta KD RXTX CTS RTS s q CK SmartCardas AF Ww T we IL 4 Channels 4 b S see P MOSIMISO SCKNSS 3 compl Channels ct tm ETR and BKIN mM cS Q K 121 K SCLSDASMBA MOSIMISO f as AF as AF RXTX CTS RTS gmartCard as AF eq USARTA bxcan USBDPCANTX VDDA KY USBDMCANRX USB 20 FS 16AF tabit ADC1 IF VREF OD Ss SRAM 512B Vper tabit ADC2 IF wwoa fino ai14390d 1 Ty 40 C to 105 C junction temperature up to 125 C 2 AF alternate function on IO port pin ky DoclD13587 Rev 17 11117 Description STM32F103x8 STM32F103xB Figure 2 Clock tree FLITFCLK to Flash programming interface HSI RC HSI USB 48 MHz USBCLK Prescaler to USB interface 115 HCLK 72 MHz max to AHB bus core Clock D memory and DMA sw Enable 3 bits to Cortex System timer FCLK Cortex AHB APB1 free running clock wy X16 SYSCLK x2 x3 x4 72 MHP Prescaler Prescaler 36 MHz max a PLL max 1 2512 1 2 4 8 16 peripherals Peripheral Clock Enable 13 bits TIMZ3 4 to TIM2 3 If APB1 prescaler 1 x1 riMCLR css else X2 Peripheral Clock Enable 3 bits APB2 72 MHz max PCLK2 oscout Prescaler D 10 APB 1 2 4 8 16 i 416 MHz Peripherdl Clock peripherals HSE OSC Enable 11 bits oscIn TIM1 timer to TIM1 If APB2 prescaler 1 x1 TIM1CLK else x2 Peripheral Clock 1128 ADC Enable 1 bit OSC32IN to ADC IN LE se osc LSE tone Prescaler ADGCLK 32768 kHz RTCCLK 12 4 68 OSC32OUT RTCSEL10 LSIRG LsI to Independent Watchdog IWDG 40 kHz IWDGCLK Legend HSE highspeed external clock signal HSI highspeed internal clock signal Main PLLCLK LSI lowspeed internal clock signal Clock Output LSE lowspeed external clock signal McO q HSI HSE SYSCLK MCO ai14903 1 When the HSI is used as a PLL clock input the maximum system clock frequency that can be achieved is 64 MHz 2 For the USB function to be available both HSE and PLL must be enabled with USBCLK running at 48 MHz 3 To have an ADC conversion time of 1 us APB2 must be at 14 MHz 28 MHz or 56 MHz 12117 DoclD13587 Rev 17 ky DocID13587 Rev 17 13117 STM32F103x8 STM32F103xB Description 116 22 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pintopin software and feature compatible In the reference manual the STM32F103x4 and STM32F103x6 are identified as lowdensity devices the STM32F103x8 and STM32F103xB are referred to as mediumdensity devices and the STM32F103xC STM32F103xD and STM32F103xE are referred to as highdensity devices Low and highdensity devices are an extension of the STM32F103x8B devices they are specified in the STM32F103x46 and STM32F103xCDE datasheets respectively Low density devices feature lower Flash memory and RAM capacities less timers and peripherals Highdensity devices have higher Flash memory and RAM capacities and additional peripherals like SDIO FSMC I2S and DAC while remaining fully compatible with the other members of the STM32F103xx family The STM32F103x4 STM32F103x6 STM32F103xC STM32F103xD and STM32F103xE are a dropin replacement for STM32F103x8B mediumdensity devices allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle Moreover the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices Table 3 STM32F103xx family Pinout Lowdensity devices Mediumdensity devices Highdensity devices 16 KB Flash 32 KB Flash 64 KB Flash 128 KB Flash 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 5 USARTs 4 16bit timers 2 basic timers 3 SPIs 2 I2Ss 2 I2Cs USB CAN 2 PWM timers 3 ADCs 2 DACs 1 SDIO FSMC 100 and 144 pins 100 3 USARTs 3 16bit timers 2 SPIs 2 I2Cs USB CAN 1 PWM timer 2 ADCs 64 2 USARTs 2 16bit timers 1 SPI 1 I2C USB CAN 1 PWM timer 2 ADCs 48 36 Description STM32F103x8 STM32F103xB 14117 DocID13587 Rev 17 23 Overview 231 ARM CortexM3 core with embedded Flash and SRAM The ARM CortexM3 processor is the latest generation of ARM processors for embedded systems It has been developed to provide a lowcost platform that meets the needs of MCU implementation with a reduced pin count and lowpower consumption while delivering outstanding computational performance and an advanced system response to interrupts The ARM CortexM3 32bit RISC processor features exceptional codeefficiency delivering the highperformance expected from an ARM core in the memory size usually associated with 8 and 16bit devices The STM32F103xx performance line family having an embedded ARM core is therefore compatible with all ARM tools and software Figure 1 shows the general block diagram of the device family 232 Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data 233 CRC cyclic redundancy check calculation unit The CRC cyclic redundancy check calculation unit is used to get a CRC code from a 32bit data word and a fixed generator polynomial Among other applications CRCbased techniques are used to verify data transmission or storage integrity In the scope of the ENIEC 603351 standard they offer a means of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of the software during runtime to be compared with a reference signature generated at link time and stored at a given memory location 234 Embedded SRAM Twenty Kbytes of embedded SRAM accessed readwrite at CPU clock speed with 0 wait states 235 Nested vectored interrupt controller NVIC The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels not including the 16 interrupt lines of Cortex M3 and 16 priority levels Closely coupled NVIC gives lowlatency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tailchaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead DocID13587 Rev 17 15117 STM32F103x8 STM32F103xB Description 116 This hardware block provides flexible interrupt management features with minimal interrupt latency 236 External interruptevent controller EXTI The external interruptevent controller consists of 19 edge detector lines used to generate interruptevent requests Each line can be independently configured to select the trigger event rising edge falling edge both and can be masked independently A pending register maintains the status of the interrupt requests The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period Up to 80 GPIOs can be connected to the 16 external interrupt lines 237 Clocks and startup System clock selection is performed on startup however the internal RC 8 MHz oscillator is selected as default CPU clock on reset An external 416 MHz clock can be selected in which case it is monitored for failure If failure is detected the system automatically switches back to the internal RC oscillator A software interrupt is generated if enabled Similarly full interrupt management of the PLL clock entry is available when necessary for example on failure of an indirectly used external crystal resonator or oscillator Several prescalers allow the configuration of the AHB frequency the highspeed APB APB2 and the lowspeed APB APB1 domains The maximum frequency of the AHB and the highspeed APB domains is 72 MHz The maximum allowed frequency of the lowspeed APB domain is 36 MHz See Figure 2 for details on the clock tree 238 Boot modes At startup boot pins are used to select one of three boot options Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory It is used to reprogram the Flash memory by using USART1 For further details please refer to AN2606 239 Power supply schemes VDD 20 to 36 V external power supply for IOs and the internal regulator Provided externally through VDD pins VSSA VDDA 20 to 36 V external analog power supplies for ADC reset blocks RCs and PLL minimum voltage to be applied to VDDA is 24 V when the ADC is used VDDA and VSSA must be connected to VDD and VSS respectively VBAT 18 to 36 V power supply for RTC external clock 32 kHz oscillator and backup registers through power switch when VDD is not present For more details on how to connect power pins refer to Figure 14 Power supply scheme 2310 Power supply supervisor The device has an integrated poweron reset PORpowerdown reset PDR circuitry It is always active and ensures proper operation starting fromdown to 2 V The device remains Description STM32F103x8 STM32F103xB 16117 DocID13587 Rev 17 in reset mode when VDD is below a specified threshold VPORPDR without the need for an external reset circuit The device features an embedded programmable voltage detector PVD that monitors the VDDVDDA power supply and compares it to the VPVD threshold An interrupt can be generated when VDDVDDA drops below the VPVD threshold andor when VDDVDDA is higher than the VPVD threshold The interrupt service routine can then generate a warning message andor put the MCU into a safe state The PVD is enabled by software Refer to Table 11 Embedded reset and power control block characteristics for the values of VPORPDR and VPVD 2311 Voltage regulator The regulator has three operation modes main MR lowpower LPR and power down MR is used in the nominal regulation mode Run LPR is used in the Stop mode Power down is used in Standby mode the regulator output is in high impedance the kernel circuitry is powered down inducing zero consumption but the contents of the registers and SRAM are lost This regulator is always enabled after reset It is disabled in Standby mode providing high impedance output 2312 Lowpower modes The STM32F103xx performance line supports three lowpower modes to achieve the best compromise between lowpower consumption short startup time and available wakeup sources Sleep mode In Sleep mode only the CPU is stopped All peripherals continue to operate and can wake up the CPU when an interruptevent occurs Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers All clocks in the 18 V domain are stopped the PLL the HSI RC and the HSE crystal oscillators are disabled The voltage regulator can also be put either in normal or in lowpower mode The device can be woken up from Stop mode by any of the EXTI line The EXTI line source can be one of the 16 external lines the PVD output the RTC alarm or the USB wakeup Standby mode The Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire 18 V domain is powered off The PLL the HSI RC and the HSE crystal oscillators are also switched off After entering Standby mode SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry The device exits Standby mode when an external reset NRST pin an IWDG reset a rising edge on the WKUP pin or an RTC alarm occurs Note The RTC the IWDG and the corresponding clock sources are not stopped by entering Stop or Standby mode DocID13587 Rev 17 17117 STM32F103x8 STM32F103xB Description 116 2313 DMA The flexible 7channel generalpurpose DMA is able to manage memorytomemory peripheraltomemory and memorytoperipheral transfers The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer Each channel is connected to dedicated hardware DMA requests with support for software trigger on each channel Configuration is made by software and transfer sizes between source and destination are independent The DMA can be used with the main peripherals SPI I2C USART generalpurpose and advancedcontrol timers TIMx and ADC 2314 RTC realtime clock and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin The backup registers are ten 16bit registers used to store 20 bytes of user application data when VDD power is not present The realtime clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function and provides an alarm interrupt and a periodic interrupt It is clocked by a 32768 kHz external crystal resonator or oscillator the internal lowpower RC oscillator or the highspeed external clock divided by 128 The internal lowpower RC has a typical frequency of 40 kHz The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation The RTC features a 32bit programmable counter for longterm measurement using the Compare register to generate an alarm A 20bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32768 kHz 2315 Timers and watchdogs The mediumdensity STM32F103xx performance line devices include an advancedcontrol timer three generalpurpose timers two watchdog timers and a SysTick timer Table 4 compares the features of the advancedcontrol and generalpurpose timers Table 4 Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request generation Capturecompare channels Complementary outputs TIM1 16bit Up down updown Any integer between 1 and 65536 Yes 4 Yes TIM2 TIM3 TIM4 16bit Up down updown Any integer between 1 and 65536 Yes 4 No Description STM32F103x8 STM32F103xB 18117 DocID13587 Rev 17 Advancedcontrol timer TIM1 The advancedcontrol timer TIM1 can be seen as a threephase PWM multiplexed on 6 channels It has complementary PWM outputs with programmable inserted deadtimes It can also be seen as a complete generalpurpose timer The 4 independent channels can be used for Input capture Output compare PWM generation edge or centeraligned modes Onepulse mode output If configured as a generalpurpose 16bit timer it has the same features as the TIMx timer If configured as the 16bit PWM generator it has full modulation capability 0100 In debug mode the advancedcontrol timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs Many features are shared with those of the generalpurpose TIM timers which have the same architecture The advancedcontrol timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining Generalpurpose timers TIMx There are up to three synchronizable generalpurpose timers embedded in the STM32F103xx performance line devices These timers are based on a 16bit autoreload updown counter a 16bit prescaler and feature 4 independent channels each for input captureoutput compare PWM or onepulse mode output This gives up to 12 input capturesoutput comparesPWMs on the largest packages The generalpurpose timers can work together with the advancedcontrol timer via the Timer Link feature for synchronization or event chaining Their counter can be frozen in debug mode Any of the generalpurpose timers can be used to generate PWM outputs They all have independent DMA request generation These timers are capable of handling quadrature incremental encoder signals and the digital outputs from 1 to 3 halleffect sensors Independent watchdog The independent watchdog is based on a 12bit downcounter and 8bit prescaler It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock it can operate in Stop and Standby modes It can be used either as a watchdog to reset the device when a problem occurs or as a freerunning timer for application timeout management It is hardware or softwareconfigurable through the option bytes The counter can be frozen in debug mode Window watchdog The window watchdog is based on a 7bit downcounter that can be set as freerunning It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode DocID13587 Rev 17 19117 STM32F103x8 STM32F103xB Description 116 SysTick timer This timer is dedicated for OS but could also be used as a standard downcounter It features A 24bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source 2316 I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes They can support standard and fast modes They support dual slave addressing 7bit only and both 710bit addressing in master mode A hardware CRC generationverification is embedded They can be served by DMA and they support SM Bus 20PM Bus 2317 Universal synchronousasynchronous receiver transmitter USART One of the USART interfaces is able to communicate at speeds of up to 45 Mbits The other available interfaces communicate at up to 225 Mbits They provide hardware management of the CTS and RTS signals IrDA SIR ENDEC support are ISO 7816 compliant and have LIN MasterSlave capability All USART interfaces can be served by the DMA controller 2318 Serial peripheral interface SPI Up to two SPIs are able to communicate up to 18 Mbitss in slave and master modes in full duplex and simplex communication modes The 3bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits The hardware CRC generationverification supports basic SD CardMMC modes Both SPIs can be served by the DMA controller 2319 Controller area network CAN The CAN is compliant with specifications 20A and B active with a bit rate up to 1 Mbits It can receive and transmit standard frames with 11bit identifiers as well as extended frames with 29bit identifiers It has three transmit mailboxes two receive FIFOs with 3 stages and 14 scalable filter banks 2320 Universal serial bus USB The STM32F103xx performance line embeds a USB device peripheral compatible with the USB fullspeed 12 Mbs The USB interface implements a fullspeed 12 Mbits function interface It has softwareconfigurable endpoint setting and suspendresume support The dedicated 48 MHz clock is generated from the internal main PLL the clock source must use a HSE crystal oscillator Description STM32F103x8 STM32F103xB 20117 DocID13587 Rev 17 2321 GPIOs generalpurpose inputsoutputs Each of the GPIO pins can be configured by software as output pushpull or opendrain as input with or without pullup or pulldown or as peripheral alternate function Most of the GPIO pins are shared with digital or analog alternate functions All GPIOs are high current capable The IOs alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the IOs registers IOs on APB2 with up to 18 MHz toggling speed 2322 ADC analogtodigital converter Two 12bit analogtodigital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels performing conversions in single shot or scan modes In scan mode automatic conversion is performed on a selected group of analog inputs Additional logic functions embedded in the ADC interface allow Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all selected channels An interrupt is generated when the converted voltage is outside the programmed thresholds The events generated by the generalpurpose timers TIMx and the advancedcontrol timer TIM1 can be internally connected to the ADC start trigger injection trigger and DMA trigger respectively to allow the application to synchronize AD conversion and timers 2323 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature The conversion range is between 2 V VDDA 36 V The temperature sensor is internally connected to the ADC12IN16 input channel which is used to convert the sensor output voltage into a digital value 2324 Serial wire JTAG debug port SWJDP The ARM SWJDP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target The JTAG TMS and TCK pins are shared with SWDIO and SWCLK respectively and a specific sequence on the TMS pin is used to switch between JTAGDP and SWDP STM32F103x8 STM32F103xB Pinouts and pin description 3 Pi t d pin description 1 2 3 4 5 6 7 8 9 10 oof aan ors oy sy sy ae ae ary ae s 1 PCi4 4 4 PC13 4 1 1 1 A 4OSC32IN TAMPER Pe2 PBg PB7 ot Pea PBs Pais PAF PAIS s RTC sane see sane sane sane sane sane saue sane sane S s aa s 7 s o aa a aa o PC15 4 vi 1 1 1 1 1 1 1 B scszou BAT 1 PES 1 PBS 1 PB6 4 PDS PD2 PC11 PC10 PA12 sll sll Sle Sle Sle Sle sane sane sue sane s o 7s a on o s o s o aa o o 1 1 1 A 1 1 1 1 A 1 1 ry 1 in 1 1 1 1 1 1 1 Cc y OSCIN 1 SS5 PES PE PBS PD6 y PD3 y PC12 1 PAQ 1 y PA11 Le Le Le SLL SL Le Le Le Le Le o Ss o s o s o ws o Ss o s o o aan o aan o aan 1 1 1 1 1 1 1 A 1 1 1 1 1 1 1 1 1 D sOSCOUT ops PES PEO BOOTO POT PDA PDO PAB PAIO Le SLL Se Se Le SLL SLL oe Le Le ors ors ors ors ors ors ors ors rts ports 1 1 1 1 1 1 1 1 E NRST pc2 PES 1 sg 4 ss 3 1 ss2 1 Yss4 1 POLY y Poo s Por Le Le Se oe Le Le ee SLL Le sale os os ors oes os o aan o o aan o aan o aan 1 t t 1 t t t t F PCO Y vs PCT PCS Yop4 Yop 3 y Ypp2 Yoo NC PCB PCE Le SLL Se Se SLL SLL Se Se Soe SLL e arn os os arn oes o a o on aa on aa on aa 1 1 1 1 1 1 a 1 t 1 1 t 1 G ssa PAOWKUP PAL 1 PCA PBZ PE10 PEW 4 PBIS POI PDIS elle Sle se Sle lle elle Sle Sle Sle lle s on a on aa s s a aa o 1 1 1 1 1 1 t 1 1 t t H VRer PAL PAS PCS 1 PET PEW 4 PEIS PBs PDIO PD14 sll elle elle Sle Sle Sle se Sle Sle elle os os oes os an os wos os os os 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 J Vrer PAZ PAG P80 1 PES PEW2 PBIO PBI3 PDo PDI3 SLL Le ee Se SLL Se Se oe ee Le os os ory os os o an o aan o an o an o an 1 1 1 1 1 1 1 1 1 1 1 1 1 1 K VpDA i 1 PA PAT PBI i PEO i y PE13 1 PB11 y PB12 PD8 4 PD12 Slee lle Sle Sle Sle sll Sle Sle Sle Sle Al14601c ky DoclD13587 Rev 17 21117 Pinouts and pin description STM32F103x8 STM32F103xB Figure 4 STM32F103xx performance line LQFP100 pinout 09 e nN oO ANomMQOROHYHMKROHWYMALTOFE ELT QNwWWOMNMOMMMNMNMADHAAGDAAAOAOCVCOCgE aoancnaamandnananaanananaananaananaanaaaana Pi fi fifififififi titi fifi titi titi titi ti ti ti ti ti ti SMDRONDYHNALFORHDRONWYHNATODORO HKHADADAAMDAADAAAWDADADAADAAORKRKRE PE2 cq 1 7510 VDD2 PE3 C 2 740 VSS 2 PE4c 3 73 NC PE5 C4 720 PA13 PE6C 5 710 PA12 VBAT C6 70 PA11 PC13TAMPERRTC CJ 7 69 PA10 PC14OSC32IN C8 680 PAQ PC15OSC32OUT 4 9 670 PAB VSS50 10 66 O PC9 VDD50 11 65 1 PC8 OSCIN q 12 641 PC7 OSCOUT 13 LQFP100 63 PC6 NRST Cc 14 62 PD15 PCO 15 610 PD14 PC1 1c 16 60 PD13 PC2 1d 17 59 PD12 PC3 0 18 58 PD11 VSSA Cg 19 57 PD10 VREF C20 56 PD9 VREF 1 21 55 PD8 VDDA 4 22 54 PB15 PAOWKUP 23 53 PB14 PA1 C24 521 PB13 PA2 25 51 PB12 AAGAKCHHOHOOOOOOTETESTE SE ESSSB DJUUUOUUOUOUUODUUUOUU UU UO UU OUD oU oo ooo 2M F2eES Saran Rgenseswern TGR Te Faaaaaaad ooo S S ai14391 22117 DoclD13587 Rev 17 ky a r CMC MOROMCRCHICRCROBO RCM Bu Cr 3 9 Ce F ey 1 S or Co oz 0 1 K 2 886 6 6 M Pinouts and pin description STM32F103x8 STM32F103xB Figure 6 STM32F103xx performance line LQFP64 pinout oO 1 on na ondy ayrMronvntnn dn aada AAnmanmMOMNNMMNMMAVLLOYD SSaacmaoacoooacaaaks Pitititiftiftififititiftititi titi CI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT C1 ag VbD2 PC13TAMPERRTC C2 47 Vs 2 PC 14OSC 32IN 3 46 O PA 13 PC 15OSC 32OUT 4 4s 1 PA12 PDOOSCIN Os 44 PAIL PD1OS COUT 6 43 1 PA 10 NRST 7 42 1 PAS PCO Os 41 0 PAB8 PCl Co LOQFP64 4o 1 PC9 PC2 C110 39 1 PC8 PC3 11 38 LJ PC7 VssA 1 12 37 0 PC6 VDDA 13 36 H PB 15 PAOWKUP 114 35 O PB 14 PA1 Olas 34 0 PB 13 PA2 C16 33 O PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 WOU UOUOODUODODOUDU OU OU OUD oo oo mm t TNO s un On NO ad Kgdk KE ELLRLR EE ge s aaxss ai14392 24117 DoclD13587 Rev 17 1ST STM32F103x8 STM32F103xB Pinouts and pin description Figure 7 STM32F103xx performance line TFBGA64 ballout 1 2 3 4 5 6 7 8 e ee pCa A Osc32IN TAMpERarc PB9 PBA PBS F LPAIS LPAI PALS iV Loot B 08c32ouT BAT PBS BOOTO PD2 PCIL PC1O 1 PAI2 c FOSCIN i Vss qi pB7 PBS pCi2 PAIO PAS i pALl D QSCOUF Vpp4 ppe Vss3 Vss2 ssi i pas pco E inRST i pct i pco Soo3 Nop2 oni pcr pce F Vesa PC2 PA2 PAS PBO pce pBis ppd G VRer PAOWKUP PAS PAG PBL PB2 PB10 PBIB H iVppa PAL 2 PAA 2S PAZ 2 PCA of PCS tO PBI i PBI2 Al15494 ky DocID13587 Rev 17 25117 Pinouts and pin description STM32F103x8 STM32F103xB Figure 8 STM32F103xx performance line LQFP48 pinout 0909 e ANneaxOncndvH eT QAngOMOnMMHMMAHMsEs oaadnmanaaaaa Ti Citi Ci fi fi ti fi titi tity 48 47 46 45 44 43 42 41 40 39 38 37 VBAT Che 360 VDD2 PC13TAMPERRT C C2 350 VSS2 PC14OSC32IN 3 3400 PA13 PC15OSC32OUT 04 3310 PA12 PDOOSCIN 05 3210 PA11 PD1OSCOUT 6 LQFP48 310 PA10 NRST 7 300 PAY VSSA 8 291 PA8 VDDA C9 280 PB15 PAOWKUP 10 27 PB14 PA1 111 260 PB13 PA2 cyl2 2501 PB12 13 14 15 16 17 18 19 20 21 22 23 24 WTUUOUOUDUUODOUOOOUo QYrwerergorns Steere haonwa aang ai14393b Figure 9 STM32F103xx performance line UFQFPN48 pinout 7 09 e ANmnanOnonya YD QAnmnMnOMMMaAHMEE raamananaaa VBAT 47 46 45 44 43 42 41 40 39 38 34 VDD2 PC13TAMPERRTC 35CVSS2 PC14OSC32IN 5s 34C PA13 PC15OSC32OUT 33CPA12 PDOOSCIN 7 32PA11 PD1OSCOUT 31CPA10 NRST QFPN48 30C PA VSSA 29 PA8 VDDA 28CJPB15 PAOWkKuP 27PB14 PA1 fo 26CPB13 2 PA2 5 14 15 16 17 18 19 20 21 22 23 ba PB12 orNOOROTNOTTST Skee EPP aowa aawnga MS31472V1 26117 DoclD13587 Rev 17 kyy STM32F103x8 STM32F103xB Pinouts and pin description Figure 10 STM32F103xx performance line VFQFPN36 pinout oO on Qnr t mo 2 F o O nm MO Oo Oo OO ce a ao ao ao a a a a 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 I 1 1 I I 1 I I 1 I I 1 1 it I I 1 I 1 MK Wd LD ND 3 35 84 CBs HC HDs 8 BB Vop3 21 27 1 Vpp2 OSCINPDO 2 26 1 Vss2 OSCOUTPD1 7743 25 C77 PAI3 NRST 24 240 pai2 Vega 25 QFNS6 2377 pai Vppa 26 22 PAO PAOWKUP 7 21 PAg PA1 18 20177 PA8 PA2 9 19 Vpp1 10 11 12 13 14 15 16 17 18 C7 OTN OT OT OT OOTY OT OT OOTY 1 1 I I 1 1 I 1 1 I I 1 1 1 1 1 1 1 1 1 I 1 1 1 1 1 I I 1 I 1 1 1 1 2e22k8 8 a YF a a a a a a ao oa H ai14654 ky DoclD13587 Rev 17 27117 Pinouts and pin description STM32F103x8 STM32F103xB 28117 DocID13587 Rev 17 Table 5 Mediumdensity STM32F103xx pin definitions Pins Pin name Type1 I O Level2 Main function3 after reset Alternate functions4 LFBGA100 UFBG100 LQFP48UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Default Remap A3 B2 1 PE2 IO FT PE2 TRACECK B3 A1 2 PE3 IO FT PE3 TRACED0 C3 B1 3 PE4 IO FT PE4 TRACED1 D3 C2 4 PE5 IO FT PE5 TRACED2 E3 D2 5 PE6 IO FT PE6 TRACED3 B2 E2 1 B2 1 6 VBAT S VBAT A2 C1 2 A2 2 7 PC13TAMPER RTC5 IO PC136 TAMPERRTC A1 D1 3 A1 3 8 PC14OSC32IN5 IO PC146 OSC32IN B1 E1 4 B1 4 9 PC15 OSC32OUT5 IO PC156 OSC32OUT C2 F2 10 VSS5 S VSS5 D2 G2 11 VDD5 S VDD5 C1 F1 5 C1 5 12 2 OSCIN I OSCIN PD07 D1 G1 6 D1 6 13 3 OSCOUT O OSCOUT PD17 E1 H2 7 E1 7 14 4 NRST IO NRST F1 H1 E3 8 15 PC0 IO PC0 ADC12IN10 F2 J2 E2 9 16 PC1 IO PC1 ADC12IN11 E2 J3 F2 10 17 PC2 IO PC2 ADC12IN12 F3 K2 8 11 18 PC3 IO PC3 ADC12IN13 G1 J1 8 F1 12 19 5 VSSA S VSSA H1 K1 20 VREF S VREF J1 L1 G18 21 VREF S VREF K1 M1 9 H1 13 22 6 VDDA S VDDA DocID13587 Rev 17 29117 STM32F103x8 STM32F103xB Pinouts and pin description 116 G2 L2 10 G2 14 23 7 PA0WKUP IO PA0 WKUP USART2CTS9 ADC12IN0 TIM2CH1 ETR9 H2 M2 11 H2 15 24 8 PA1 IO PA1 USART2RTS9 ADC12IN1 TIM2CH29 J2 K3 12 F3 16 25 9 PA2 IO PA2 USART2TX9 ADC12IN2 TIM2CH39 K2 L3 13 G3 17 26 10 PA3 IO PA3 USART2RX9 ADC12IN3 TIM2CH49 E4 E3 C2 18 27 VSS4 S VSS4 F4 H3 D2 19 28 VDD4 S VDD4 G3 M3 14 H3 20 29 11 PA4 IO PA4 SPI1NSS9 USART2CK9 ADC12IN4 H3 K4 15 F4 21 30 12 PA5 IO PA5 SPI1SCK9 ADC12IN5 J3 L4 16 G4 22 31 13 PA6 IO PA6 SPI1MISO9 ADC12IN6 TIM3CH19 TIM1BKIN K3 M4 17 H4 23 32 14 PA7 IO PA7 SPI1MOSI9 ADC12IN7 TIM3CH29 TIM1CH1N G4 K5 H5 24 33 PC4 IO PC4 ADC12IN14 H4 L5 H6 25 34 PC5 IO PC5 ADC12IN15 J4 M5 18 F5 26 35 15 PB0 IO PB0 ADC12IN8 TIM3CH39 TIM1CH2N K4 M6 19 G5 27 36 16 PB1 IO PB1 ADC12IN9 TIM3CH49 TIM1CH3N Table 5 Mediumdensity STM32F103xx pin definitions continued Pins Pin name Type1 I O Level2 Main function3 after reset Alternate functions4 LFBGA100 UFBG100 LQFP48UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Default Remap Pinouts and pin description STM32F103x8 STM32F103xB 30117 DocID13587 Rev 17 G5 L6 20 G6 28 37 17 PB2 IO FT PB2BOOT1 H5 M7 38 PE7 IO FT PE7 TIM1ETR J5 L7 39 PE8 IO FT PE8 TIM1CH1N K5 M8 40 PE9 IO FT PE9 TIM1CH1 G6 L8 41 PE10 IO FT PE10 TIM1CH2N H6 M9 42 PE11 IO FT PE11 TIM1CH2 J6 L9 43 PE12 IO FT PE12 TIM1CH3N K6 M10 44 PE13 IO FT PE13 TIM1CH3 G7 M11 45 PE14 IO FT PE14 TIM1CH4 H7 M12 46 PE15 IO FT PE15 TIM1BKIN J7 L10 21 G7 29 47 PB10 IO FT PB10 I2C2SCL USART3TX9 TIM2CH3 K7 L11 22 H7 30 48 PB11 IO FT PB11 I2C2SDA USART3RX9 TIM2CH4 E7 F12 23 D6 31 49 18 VSS1 S VSS1 F7 G12 24 E6 32 50 19 VDD1 S VDD1 K8 L12 25 H8 33 51 PB12 IO FT PB12 SPI2NSS I2C2SMBAl USART3CK9 TIM1BKIN9 J8 K12 26 G8 34 52 PB13 IO FT PB13 SPI2SCK USART3CTS9 TIM1CH1N 9 H8 K11 27 F8 35 53 PB14 IO FT PB14 SPI2MISO USART3RTS9 TIM1CH2N 9 G8 K10 28 F7 36 54 PB15 IO FT PB15 SPI2MOSI TIM1CH3N9 K9 K9 55 PD8 IO FT PD8 USART3TX J9 K8 56 PD9 IO FT PD9 USART3RX Table 5 Mediumdensity STM32F103xx pin definitions continued Pins Pin name Type1 I O Level2 Main function3 after reset Alternate functions4 LFBGA100 UFBG100 LQFP48UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Default Remap DocID13587 Rev 17 31117 STM32F103x8 STM32F103xB Pinouts and pin description 116 H9 J12 57 PD10 IO FT PD10 USART3CK G9 J11 58 PD11 IO FT PD11 USART3CTS K10 J10 59 PD12 IO FT PD12 TIM4CH1 USART3RTS J10 H12 60 PD13 IO FT PD13 TIM4CH2 H10 H11 61 PD14 IO FT PD14 TIM4CH3 G10 H10 62 PD15 IO FT PD15 TIM4CH4 F10 E12 F6 37 63 PC6 IO FT PC6 TIM3CH1 E10 E11 E7 38 64 PC7 IO FT PC7 TIM3CH2 F9 E10 E8 39 65 PC8 IO FT PC8 TIM3CH3 E9 D12 D8 40 66 PC9 IO FT PC9 TIM3CH4 D9 D11 29 D7 41 67 20 PA8 IO FT PA8 USART1CK TIM1CH19 MCO C9 D10 30 C7 42 68 21 PA9 IO FT PA9 USART1TX9 TIM1CH29 D10 C12 31 C6 43 69 22 PA10 IO FT PA10 USART1RX9 TIM1CH39 C10 B12 32 C8 44 70 23 PA11 IO FT PA11 USART1CTS CANRX9 USBDM TIM1CH49 B10 A12 33 B8 45 71 24 PA12 IO FT PA12 USART1RTS CANTX9 USBDP TIM1ETR9 A10 A11 34 A8 46 72 25 PA13 IO FT JTMSSWDIO PA13 F8 C11 73 Not connected E6 F11 35 D5 47 74 26 VSS2 S VSS2 F6 G11 36 E5 48 75 27 VDD2 S VDD2 Table 5 Mediumdensity STM32F103xx pin definitions continued Pins Pin name Type1 I O Level2 Main function3 after reset Alternate functions4 LFBGA100 UFBG100 LQFP48UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Default Remap Pinouts and pin description STM32F103x8 STM32F103xB 32117 DocID13587 Rev 17 A9 A10 37 A7 49 76 28 PA14 IO FT JTCKSWCLK PA14 A8 A9 38 A6 50 77 29 PA15 IO FT JTDI TIM2CH1 ETR PA15 SPI1NSS B9 B11 B7 51 78 PC10 IO FT PC10 USART3TX B8 C10 B6 52 79 PC11 IO FT PC11 USART3RX C8 B10 C5 53 80 PC12 IO FT PC12 USART3CK C9 C1 81 2 PD0 IO FT PD0 CANRX B9 D1 82 3 PD1 IO FT PD1 CANTX B7 C8 B5 54 83 PD2 IO FT PD2 TIM3ETR C7 B8 84 PD3 IO FT PD3 USART2CTS D7 B7 85 PD4 IO FT PD4 USART2RTS B6 A6 86 PD5 IO FT PD5 USART2TX C6 B6 87 PD6 IO FT PD6 USART2RX D6 A5 88 PD7 IO FT PD7 USART2CK A7 A8 39 A5 55 89 30 PB3 IO FT JTDO TIM2CH2 PB3 TRACESWO SPI1SCK A6 A7 40 A4 56 90 31 PB4 IO FT JNTRST TIM3CH1 PB4 SPI1MISO C5 C5 41 C4 57 91 32 PB5 IO PB5 I2C1SMBAl TIM3CH2 SPI1MOSI B5 B5 42 D3 58 92 33 PB6 IO FT PB6 I2C1SCL9 TIM4CH19 USART1TX A5 B4 43 C3 59 93 34 PB7 IO FT PB7 I2C1SDA9 TIM4CH29 USART1RX D5 A4 44 B4 60 94 35 BOOT0 I BOOT0 Table 5 Mediumdensity STM32F103xx pin definitions continued Pins Pin name Type1 I O Level2 Main function3 after reset Alternate functions4 LFBGA100 UFBG100 LQFP48UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Default Remap DocID13587 Rev 17 33117 STM32F103x8 STM32F103xB Pinouts and pin description 116 B4 A3 45 B3 61 95 PB8 IO FT PB8 TIM4CH39 I2C1SCL CANRX A4 B3 46 A3 62 96 PB9 IO FT PB9 TIM4CH49 I2C1SDA CANTX D4 C3 97 PE0 IO FT PE0 TIM4ETR C4 A2 98 PE1 IO FT PE1 E5 D3 47 D4 63 99 36 VSS3 S VSS3 F5 C4 48 E4 64 100 1 VDD3 S VDD3 1 I input O output S supply 2 FT 5 V tolerant 3 Function availability depends on the chosen device For devices having reduced peripheral counts it is always the lower number of peripheral that is included For example if a device has only one SPI and two USARTs they will be called SPI1 and USART1 USART2 respectively Refer to Table 2 on page 10 4 If several peripherals share the same IO pin to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit in the corresponding RCC peripheral clock enable register 5 PC13 PC14 and PC15 are supplied through the power switch Since the switch only sinks a limited amount of current 3 mA the use of GPIOs PC13 to PC15 in output mode is limited the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source eg to drive an LED 6 Main function after the first backup domain powerup Later on it depends on the contents of the Backup registers even after reset because these registers are not reset by the main reset For details on how to manage these IOs refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual available from the STMicroelectronics website wwwstcom 7 The pins number 2 and 3 in the VFQFPN36 package 5 and 6 in the LQFP48 UFQFP48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSCINOSCOUT after reset however the functionality of PD0 and PD1 can be remapped by software on these pins For the LQFP100 package PD0 and PD1 are available by default so there is no need for remapping For more details refer to the Alternate function IO and debug configuration section in the STM32F10xxx reference manual The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode 8 Unlike in the LQFP64 package there is no PC3 in the TFBGA64 package The VREF functionality is provided instead 9 This alternate function can be remapped by software to some other port pins if available on the used package For more details refer to the Alternate function IO and debug configuration section in the STM32F10xxx reference manual available from the STMicroelectronics website wwwstcom Table 5 Mediumdensity STM32F103xx pin definitions continued Pins Pin name Type1 I O Level2 Main function3 after reset Alternate functions4 LFBGA100 UFBG100 LQFP48UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Default Remap Memory mapping STM32F103x8 STM32F103xB 4 Memory mapping The memory map is shown in Figure 11 Figure 11 Memory map APB memory space OxFFFF FFFF 0xE010 0000 0x6000 0000 0x4002 3400 7 0x4002 3000 0xE010 0000 0x4002 2400 Cortex M3 Internal Flash Interface 0xE000 0000 Peripherals 0x4002 2000 0x4002 1400 0x4002 1000 6 0x4002 0400 0x4002 0000 0xc000 0000 0x4001 3c00 USART1 0x4001 3800 0x4001 3400 5 spit 0x4001 3000 TIM1 0x4001 2c00 0xA000 0000 ADC2 0x4001 2800 ADC1 0x4001 2400 4 Ox1FFF FFFF 9x4001 100 Ox1FFF F80F 0x4001 1800 0x8000 0000 Option Byt 0x4001 1400 Ox1FFF F800 0x4001 1000 0x4001 OC0O 3 System memory 0x4001 0800 EXTI 0x4001 0400 Ox1FFF F000 AFIO 0x6000 0000 0x4001 0000 0x4000 7400 0x4000 7000 0x4000 6C00 reserve 0x4000 0000 Peripherals oes00 8800 bxCAN 0x4000 6400 shared 512 byte ox4000 6000 USBCAN SRAM USB Registers 1 0x4000 5c00 12C2 0x4000 5800 12C1 0x4000 4c00 0x0801 FFFF USART3 0x4000 4800 USART2 0 0x4000 4400 0x4000 3c00 SPI2 0x0800 0000 0x4000 3800 00000 0000 Aliased to Flash or system memory depending on 0x4000 3400 BOOT pins W0G 0x0000 0000 0x4000 3000 0x4000 2Cc00 0x4000 2800 Reserved 0x4000 0c00 TIM4 0x4000 0800 TIM3 0x4000 0400 0x4000 0000 TIM2 ai14394f 34117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Electrical characteristics 5 Electrical characteristics 51 Parameter conditions Unless otherwise specified all voltages are referenced to Vgs 511 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T 25 C and Ty Tamax given by the selected temperature range Data based on characterization results design simulation andor technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean30 512 Typical values Unless otherwise specified typical data are based on Ty 25 C Vpp 33 V for the 2V Vpp 36 V voltage range They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean20 513 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested 514 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 12 515 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 13 Figure 12 Pin loading conditions Figure 13 Pin input voltage STM32F103xx pin STM32F103xx pin C 50 pF 7 aii4141 ai14142 ky DoclD13587 Rev 17 35117 Electrical characteristics STM32F103x8 STM32F103xB 516 Power supply scheme Figure 14 Power supply scheme VBAT r Backup circuitry 1836V A AL Power switch OSC32KRTC vr Wakeup logic Backup registers ees J OUT 5 10 GP IOs To Logic IN Kernel logic Cpu Digital VDD Vv Memories DD 12345 Regulator 5 x 100 nF Vss a 41 47 pF Ey234 ri Vv DD VpDA A eae WY REF 10nF 10 nF SNe lL Analog Vv 1uF THF REF 7 aed RCs PLL vosaly ai14125d Caution In Figure 14 the 47 uF capacitor must be connected to Vpp3 517 Current consumption measurement Figure 15 Current consumption measurement scheme g IDDVBAT C VBATHH IDD Ove 1 ai14126 36117 DoclD13587 Rev 17 ky DocID13587 Rev 17 37117 STM32F103x8 STM32F103xB Electrical characteristics 116 52 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6 Voltage characteristics Table 7 Current characteristics and Table 8 Thermal characteristics may cause permanent damage to the device These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 6 Voltage characteristics Symbol Ratings Min Max Unit VDD VSS External main supply voltage including VDDA and VDD1 1 All main power VDD VDDA and ground VSS VSSA pins must always be connected to the external power supply in the permitted range 03 40 V VIN 2 2 VIN maximum must always be respected Refer to Table 7 Current characteristics for the maximum allowed injected current values Input voltage on five volt tolerant pin VSS 03 VDD 40 Input voltage on any other pin VSS 03 40 ΔVDDx Variations between different VDD power pins 50 mV VSSX VSS Variations between all the different ground pins 50 VESDHBM Electrostatic discharge voltage human body model see Section 5311 Absolute maximum ratings electrical sensitivity Table 7 Current characteristics Symbol Ratings Max Unit IVDD Total current into VDDVDDA power lines source1 1 All main power VDD VDDA and ground VSS VSSA pins must always be connected to the external power supply in the permitted range 150 mA IVSS Total current out of VSS ground lines sink1 150 IIO Output current sunk by any IO and control pin 25 Output current source by any IOs and control pin 25 IINJPIN 2 2 Negative injection disturbs the analog performance of the device See note 2 on page 76 Injected current on five volt tolerant pins3 3 Positive injection is not possible on these IOs A negative injection is induced by VINVSS IINJPIN must never be exceeded Refer to Table 6 Voltage characteristics for the maximum allowed input voltage values 50 Injected current on any other pin4 4 A positive injection is induced by VINVDD while a negative injection is induced by VINVSS IINJPIN must never be exceeded Refer to Table 6 Voltage characteristics for the maximum allowed input voltage values 5 ΣIINJPIN Total injected current sum of all IO and control pins5 5 When several inputs are submitted to a current injection the maximum ΣIINJPIN is the absolute sum of the positive and negative injected currents instantaneous values 25 Electrical characteristics STM32F103x8 STM32F103xB 38117 DocID13587 Rev 17 53 Operating conditions 531 General operating conditions Table 8 Thermal characteristics Symbol Ratings Value Unit TSTG Storage temperature range 65 to 150 C TJ Maximum junction temperature 150 C Table 9 General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency 0 72 MHz fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 VDD Standard operating voltage 2 36 V VDDA 1 Analog operating voltage ADC not used Must be the same potential as VDD 2 2 36 Analog operating voltage ADC used 24 36 VBAT Backup operating voltage 18 36 VIN IO input voltage Standard IO 03 VDD 03 V FT IO3 2 V VDD 36 V 03 55 VDD 2 V 03 52 BOOT0 0 55 PD Power dissipation at TA 85 C for suffix 6 or TA 105 C for suffix 74 LFBGA100 454 mW LQFP100 434 UFBGA100 339 TFBGA64 308 LQFP64 444 LQFP48 363 UFQFPN48 624 VFQFPN36 1000 DocID13587 Rev 17 39117 STM32F103x8 STM32F103xB Electrical characteristics 116 532 Operating conditions at powerup powerdown Subject to general operating conditions for TA TA Ambient temperature for 6 suffix version Maximum power dissipation 40 85 C Lowpower dissipation5 40 105 Ambient temperature for 7 suffix version Maximum power dissipation 40 105 Lowpower dissipation5 40 125 TJ Junction temperature range 6 suffix version 40 105 7 suffix version 40 125 1 When the ADC is used refer to Table 46 ADC characteristics 2 It is recommended to power VDD and VDDA from the same source A maximum difference of 300 mV between VDD and VDDA can be tolerated during powerup and operation 3 To sustain a voltage higher than VDD03 V the internal pulluppulldown resistors must be disabled 4 If TA is lower higher PD values are allowed as long as TJ does not exceed TJmax see Table 69 Thermal characteristics on page 105 5 In lowpower dissipation state TA can be extended to this range as long as TJ does not exceed TJmax see Table 69 Thermal characteristics on page 105 Table 9 General operating conditions continued Symbol Parameter Conditions Min Max Unit Table 10 Operating conditions at powerup powerdown Symbol Parameter Conditions Min Max Unit tVDD VDD rise time rate 0 µsV VDD fall time rate 20 Electrical characteristics STM32F103x8 STM32F103xB 40117 DocID13587 Rev 17 533 Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9 Table 11 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit VPVD Programmable voltage detector level selection PLS20000 rising edge 21 218 226 V PLS20000 falling edge 2 208 216 PLS20001 rising edge 219 228 237 PLS20001 falling edge 209 218 227 PLS20010 rising edge 228 238 248 PLS20010 falling edge 218 228 238 PLS20011 rising edge 238 248 258 PLS20011 falling edge 228 238 248 PLS20100 rising edge 247 258 269 PLS20100 falling edge 237 248 259 PLS20101 rising edge 257 268 279 PLS20101 falling edge 247 258 269 PLS20110 rising edge 266 278 29 PLS20110 falling edge 256 268 28 PLS20111 rising edge 276 288 3 PLS20111 falling edge 266 278 29 VPVDhyst 2 PVD hysteresis 100 mV VPORPDR Power onpower down reset threshold Falling edge 181 1 The product behavior is guaranteed by design down to the minimum VPORPDR value 188 196 V Rising edge 184 192 20 VPDRhyst 2 PDR hysteresis 40 mV TRSTTEMPO 2 2 Guaranteed by design Reset temporization 1 25 45 ms DocID13587 Rev 17 41117 STM32F103x8 STM32F103xB Electrical characteristics 116 534 Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9 535 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage ambient temperature IO pin loading device software configuration operating frequencies IO pin switching rate program location in memory and executed binary code The current consumption is measured as described in Figure 15 Current consumption measurement scheme All Runmode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 21 code Maximum current consumption The MCU is placed under the following conditions All IO pins are in input mode with a static value at VDD or VSS no load All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency 0 wait state from 0 to 24 MHz 1 wait state from 24 to 48 MHz and 2 wait states above Prefetch in ON reminder this bit must be set before clock setting and bus prescaling When the peripherals are enabled fPCLK1 fHCLK2 fPCLK2 fHCLK The parameters given in Table 13 Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9 Table 12 Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage 40 C TA 105 C 116 120 126 V 40 C TA 85 C 116 120 124 TSvrefint 1 1 Shortest sampling time can be determined in the application by multiple iterations ADC sampling time when reading the internal reference voltage 51 1712 2 Guaranteed by design µs VRERINT 2 Internal reference voltage spread over the temperature range VDD 3 V 10 mV 10 mV TCoeff 2 Temperature coefficient 100 ppmC Electrical characteristics STM32F103x8 STM32F103xB 42117 DocID13587 Rev 17 Table 13 Maximum current consumption in Run mode code with data processing running from Flash Symbol Parameter Conditions fHCLK Max1 1 Guaranteed based on test during characterization Unit TA 85 C TA 105 C IDD Supply current in Run mode External clock2 all peripherals enabled 2 External clock is 8 MHz and PLL is on when fHCLK 8 MHz 72 MHz 50 503 mA 48 MHz 361 362 36 MHz 286 287 24 MHz 199 201 16 MHz 147 149 8 MHz 86 89 External clock2 all peripherals disabled 72 MHz 328 329 48 MHz 244 245 36 MHz 198 199 24 MHz 139 142 16 MHz 107 11 8 MHz 68 71 Table 14 Maximum current consumption in Run mode code with data processing running from RAM Symbol Parameter Conditions fHCLK Max1 1 Based on characterization tested in production at VDD max fHCLK max Unit TA 85 C TA 105 C IDD Supply current in Run mode External clock2 all peripherals enabled 2 External clock is 8 MHz and PLL is on when fHCLK 8 MHz 72 MHz 48 50 mA 48 MHz 315 32 36 MHz 24 255 24 MHz 175 18 16 MHz 125 13 8 MHz 75 8 External clock2 all peripherals disabled 72 MHz 29 295 48 MHz 205 21 36 MHz 16 165 24 MHz 115 12 16 MHz 85 9 8 MHz 55 6 DocID13587 Rev 17 43117 STM32F103x8 STM32F103xB Electrical characteristics 116 Figure 16 Typical current consumption in Run mode versus frequency at 36 V code with data processing running from RAM peripherals enabled Figure 17 Typical current consumption in Run mode versus frequency at 36 V code with data processing running from RAM peripherals disabled 0 5 10 15 20 25 30 35 40 45 40 0 25 70 85 105 Temperature C Consumption mA 72 MHz 36 MHz 16 MHz 8 MHz 0 5 10 15 20 25 30 40 0 25 70 85 105 Temperature C Consumption mA 72 MHz 36 MHz 16 MHz 8 MHz Electrical characteristics STM32F103x8 STM32F103xB 44117 DocID13587 Rev 17 Table 15 Maximum current consumption in Sleep mode code running from Flash or RAM Symbol Parameter Conditions fHCLK Max1 1 Based on characterization tested in production at VDD max fHCLK max with peripherals enabled Unit TA 85 C TA 105 C IDD Supply current in Sleep mode External clock2 all peripherals enabled 2 External clock is 8 MHz and PLL is on when fHCLK 8 MHz 72 MHz 30 32 mA 48 MHz 20 205 36 MHz 155 16 24 MHz 115 12 16 MHz 85 9 8 MHz 55 6 External clock2 all peripherals disabled 72 MHz 75 8 48 MHz 6 65 36 MHz 5 55 24 MHz 45 5 16 MHz 4 45 8 MHz 3 4 DocID13587 Rev 17 45117 STM32F103x8 STM32F103xB Electrical characteristics 116 Figure 18 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values Table 16 Typical and maximum current consumptions in Stop and Standby modes Symbol Parameter Conditions Typ1 Max Unit VDDVBAT 20 V VDDVBAT 24 V VDDVBAT 33 V TA 85 C TA 105 C IDD Supply current in Stop mode Regulator in Run mode lowspeed and highspeed internal RC oscillators and highspeed oscillator OFF no independent watchdog 235 24 200 370 µA Regulator in Lowpower mode low speed and highspeed internal RC oscillators and highspeed oscillator OFF no independent watchdog 135 14 180 340 Supply current in Standby mode Lowspeed internal RC oscillator and independent watchdog ON 26 34 Lowspeed internal RC oscillator ON independent watchdog OFF 24 32 Lowspeed internal RC oscillator and independent watchdog OFF low speed oscillator and RTC OFF 17 2 4 5 IDDVBAT Backup domain supply current Lowspeed oscillator and RTC ON 09 11 14 192 22 1 Typical values are measured at TA 25 C 2 Guaranteed based on test during characterization 0 05 1 15 2 25 40 C 25 C 70 C 85 C 105 C Temperature C Consumption µA 2 V 24 V 3 V 36 V ai17351 Electrical characteristics STM32F103x8 STM32F103xB 46117 DocID13587 Rev 17 Figure 19 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD 33 V and 36 V Figure 20 Typical current consumption in Stop mode with regulator in Lowpower mode versus temperature at VDD 33 V and 36 V 0 50 100 150 200 250 300 45 25 70 90 110 Temperature C Consumption µA 33 V 36 V 0 50 100 150 200 250 300 40 0 25 70 85 105 Temperature C Consumption µA 33 V 36 V DocID13587 Rev 17 47117 STM32F103x8 STM32F103xB Electrical characteristics 116 Figure 21 Typical current consumption in Standby mode versus temperature at VDD 33 V and 36 V Typical current consumption The MCU is placed under the following conditions All IO pins are in input mode with a static value at VDD or VSS no load All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency 0 wait state from 0 to 24 MHz 1 wait state from 24 to 48 MHz and 2 wait states above Ambient temperature and VDD supply voltage conditions summarized in Table 9 Prefetch is ON Reminder this bit must be set before clock setting and bus prescaling When the peripherals are enabled fPCLK1 fHCLK4 fPCLK2 fHCLK2 fADCCLK fPCLK24 0 05 1 15 2 25 3 35 4 45 45 C 25 C 85 C 105 C Temperature C Consumption µA 33 V 36 V Electrical characteristics STM32F103x8 STM32F103xB 48117 DocID13587 Rev 17 Table 17 Typical current consumption in Run mode code with data processing running from Flash Symbol Parameter Conditions fHCLK Typ1 1 Typical values are measures at TA 25 C VDD 33 V Unit All peripherals enabled2 2 Add an additional power consumption of 08 mA per ADC for the analog part In applications this consumption occurs only while the ADC is on ADON bit is set in the ADCCR2 register All peripherals disabled IDD Supply current in Run mode External clock3 3 External clock is 8 MHz and PLL is on when fHCLK 8 MHz 72 MHz 36 27 mA 48 MHz 242 186 36 MHz 19 148 24 MHz 129 101 16 MHz 93 74 8 MHz 55 46 4 MHz 33 28 2 MHz 22 19 1 MHz 16 145 500 kHz 13 125 125 kHz 108 106 Running on high speed internal RC HSI AHB prescaler used to reduce the frequency 64 MHz 314 239 mA 48 MHz 235 179 36 MHz 183 141 24 MHz 122 95 16 MHz 85 68 8 MHz 49 4 4 MHz 27 22 2 MHz 16 14 1 MHz 102 09 500 kHz 073 067 125 kHz 05 048 DocID13587 Rev 17 49117 STM32F103x8 STM32F103xB Electrical characteristics 116 Table 18 Typical current consumption in Sleep mode code running from Flash or RAM Symbol Parameter Conditions fHCLK Typ1 1 Typical values are measures at TA 25 C VDD 33 V Unit All peripherals enabled2 2 Add an additional power consumption of 08 mA per ADC for the analog part In applications this consumption occurs only while the ADC is on ADON bit is set in the ADCCR2 register All peripherals disabled IDD Supply current in Sleep mode External clock3 3 External clock is 8 MHz and PLL is on when fHCLK 8 MHz 72 MHz 144 55 mA 48 MHz 99 39 36 MHz 76 31 24 MHz 53 23 16 MHz 38 18 8 MHz 21 12 4 MHz 16 11 2 MHz 13 1 1 MHz 111 098 500 kHz 104 096 125 kHz 098 095 Running on high speed internal RC HSI AHB prescaler used to reduce the frequency 64 MHz 123 44 48 MHz 93 33 36 MHz 7 25 24 MHz 48 18 16 MHz 32 12 8 MHz 16 06 4 MHz 1 05 2 MHz 072 047 1 MHz 056 044 500 kHz 049 042 125 kHz 043 041 Electrical characteristics STM32F103x8 STM32F103xB 50117 DocID13587 Rev 17 Onchip peripheral current consumption The current consumption of the onchip peripherals is given in Table 19 The MCU is placed under the following conditions all IO pins are in input mode with a static value at VDD or VSS no load all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption with all peripherals clocked off with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Table 19 Peripheral current consumption Peripherals µAMHz AHB up to 72 MHz DMA1 1653 BusMatrix1 833 APB1 up to 36 MHz APB1Bridge 1028 TIM2 3250 TIM3 3139 TIM4 3194 SPI2 417 USART2 1222 USART3 1222 I2C1 1000 I2C2 1000 USB 1778 CAN1 1806 WWDG 250 PWR 167 BKP 250 IWDG 1167 DocID13587 Rev 17 51117 STM32F103x8 STM32F103xB Electrical characteristics 116 536 External clock source characteristics Highspeed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an highspeed external clock source and under ambient temperature and supply voltage conditions summarized in Table 9 APB2 up to 72 MHz APB2Bridge 375 GPIOA 667 GPIOB 653 GPIOC 653 GPIOD 653 GPIOE 639 SPI1 472 USART1 1194 TIM1 2333 ADC12 1750 ADC22 1607 1 The BusMatrix is automatically active when at least one master peripheral is ON CPU or DMA 2 Specific conditions for measuring ADC current consumption fHCLK 56 MHz fAPB1 fHCLK2 fAPB2 fHCLK fADCCLK fAPB24 When ADON bit in the ADCxCR2 register is set to 1 a current consumption of analog part equal to 065 mA must be added for each ADC Table 19 Peripheral current consumption continued Peripherals µAMHz Table 20 Highspeed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSEext User external clock source frequency1 1 8 25 MHz VHSEH OSCIN input pin high level voltage 07VDD VDD V VHSEL OSCIN input pin low level voltage VSS 03VDD twHSE twHSE OSCIN high or low time1 1 Guaranteed by design 5 ns trHSE tfHSE OSCIN rise or fall time1 20 CinHSE OSCIN input capacitance1 5 pF DuCyHSE Duty cycle 45 55 IL OSCIN Input leakage current VSS VIN VDD 1 µA Electrical characteristics STM32F103x8 STM32F103xB Lowspeed external user clock generated from an external source The characteristics given in Table 27 result from tests performed using an lowspeed external clock source and under ambient temperature and supply voltage conditions summarized in Table 9 Table 21 Lowspeed external user clock characteristics Sd User External clock source OSC32IN input pin high level voltage 07 Yeo V OSC32IN input pin low level bwLSE C32IN high or low time 450 twLSE ns tiLSE OSC32IN Input leakage Rear ions Vossvievoo et ae 1 Guaranteed by design Figure 22 Highspeed external clock source AC timing diagram VHSEH ween eee 90 Prnn nnn irr rrr e reer c cre fcc c cre enc c reece ccf n ence oe VHSEL torcccy ut ul tHSE a Hs pe i tiHSE e twHSE WHSE Tse EXTERNAL HSEext A I CLOCK SOURCE HOSCIN SLL STM32F103xx ai14143 52117 DoclD13587 Rev 17 kyy STM32F103x8 STM32F103xB Electrical characteristics Figure 23 Lowspeed external clock source AC timing diagram VLSEH 90 F fh 77 Yee 2 oo hen nnn ene een n fone e H 10 f ft VLSEL toss n vt ul trLSE phe Pht tLSE L twLSE WLSE t Tse f EXTERNAL LSEext A CLOCK SOURCE Hoscs2IN L SLL STM32F103xx ai14144b Highspeed external clock generated from a crystalceramic resonator The highspeed external HSE clock can be supplied with a 4 to 16 MHz crystalceramic resonator oscillator All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 22 HSE 416 MHz oscillator characteristics 2 So Recommended load capacitance Cc versus equivalent serial Rs 30 Q 30 pF resistance of the crystal Rg we Vpp 33 V VIN Vss ig HSE driving current with 30 pF load 1 mA Oscillator transconductance Startup 25 mav tsunse startup time Vpp is stabilized p 2 ms 1 Resonator characteristics given by the crystalceramic resonator manufacturer 2 Guaranteed based on test during characterization 3 The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment due to the induced leakage and the bias condition change However it is recommended to take this point into account if the MCU is used in tough humidity conditions 4 tsuHse is the startup time measured from the moment it is enabled by software to a stabilized 8 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer ky DoclD13587 Rev 17 53117 Electrical characteristics STM32F103x8 STM32F103xB For C 4 and C 9 it is recommended to use highquality external ceramic capacitors in the 5 pF to 25 pF range typ designed for highfrequency applications and selected to match the requirements of the crystal or resonator see Figure 24 C4 and C2 are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C 1 and C2 PCB and MCU pin capacitance must be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing C and C Refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website wwwstcom Figure 24 Typical application with an 8 MHz crystal Resonator with integrated capacitors Ms Sh o on OSCIN fHSE L Bias 18 MHz Re controlled resonator gain SUD Rey1 a OSCOUT STM32F103xx Cio EXT ai14145 1 Re yz value depends on the crystal characteristics Lowspeed external clock generated from a crystalceramic resonator The lowspeed external LSE clock can be supplied with a 32768 kHz crystalceramic resonator oscillator All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 23 LSE oscillator characteristics f s 32768 kHz 2 symbot Parameter concitions in Typ ax ni Re Fesibackresisor Recommended load capacitance Cc versus equivalent serial Rg 30 KQ 15 pF resistance of the crystal Rs I LSE driving current Vpp 33V 14 pA Vin Vss Gn Oeetatorwaneconausence S oa 54117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Electrical characteristics Table 23 LSE oscillator characteristics f s 32768 kHz 2 continued meso 1s Taras 25 Tmstoro 4 teurse Startup time Voo is A fete tazaore tanaore se Traore 60 1 Guaranteed based on test during characterization 2 Refer to the note and caution paragraphs below the table and to the application note AN2867 Oscillator design guide for ST microcontrollers 3 tsuLse is the startup time measured from the moment it is enabled by software to a stabilized 32768 kHz oscillation is reached This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note For C 4 and C 9 it is recommended to use highquality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator C 1 and C2 are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C4 and Cy Load capacitance C has the following formula C C4 x Ci2C1 C2 Cstray where Cstray is the pin capacitance and board or trace PCBrelated capacitance Typically it is between 2 pF and 7 pF Caution To avoid exceeding the maximum value of C4 and C9 15 pF it is strongly recommended to use a resonator with a load capacitance C 7 pF Never use a resonator with a load capacitance of 125 pF Example if you choose a resonator with a load capacitance of C 6 pF and Cgtray 2 pF then C4 Clo 8 pF Figure 25 Typical application with a 32768 kHz crystal Resonator with integrated capacitors Su oo sy OSC32IN Fr fLSE LI Bias Eq 82768 kHz Re controlled resonator gain ST J OSC32OUT STM32F103xx CL2 ai14146 537 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 9 ky DoclD13587 Rev 17 55117 Electrical characteristics STM32F103x8 STM32F103xB 56117 DocID13587 Rev 17 Highspeed internal HSI RC oscillator Lowspeed internal LSI RC oscillator Wakeup time from lowpower mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8MHz HSI RC oscillator The clock source used to wake up the device depends from the current operating mode Stop or Standby mode the clock source is the RC oscillator Sleep mode the clock source is the clock that was set before entering Sleep mode All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9 Table 24 HSI oscillator characteristics1 1 VDD 33 V TA 40 to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency 8 MHz DuCyHSI Duty cycle 45 55 ACCHSI Accuracy of the HSI oscillator Usertrimmed with the RCCCR register2 2 Refer to application note AN2868 STM32F10xxx internal RC oscillator HSI calibration available from the ST website wwwstcom 13 3 Guaranteed by design Factory calibrated 45 4 Guaranteed based on test during characterization 5 The actual frequency of HSI oscillator may be impacted by a reflow but does not drift out of the specified range TA 40 to 105 C 2 25 TA 10 to 85 C 15 22 TA 0 to 70 C 13 2 TA 25 C 11 18 tsuHSI 4 HSI oscillator startup time 1 2 µs IDDHSI 4 HSI oscillator power consumption 80 100 µA Table 25 LSI oscillator characteristics 1 1 VDD 3 V TA 40 to 105 C unless otherwise specified Symbol Parameter Min Typ Max Unit fLSI 2 2 Guaranteed based on test during characterization Frequency 30 40 60 kHz tsuLSI 3 3 Guaranteed by design LSI oscillator startup time 85 µs IDDLSI 3 LSI oscillator power consumption 065 12 µA DocID13587 Rev 17 57117 STM32F103x8 STM32F103xB Electrical characteristics 116 538 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9 539 Memory characteristics Flash memory The characteristics are given at TA 40 to 105 C unless otherwise specified Table 26 Lowpower mode wakeup timings Symbol Parameter Typ Unit tWUSLEEP 1 1 The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction Wakeup from Sleep mode 18 µs tWUSTOP 1 Wakeup from Stop mode regulator in run mode 36 Wakeup from Stop mode regulator in lowpower mode 54 tWUSTDBY 1 Wakeup from Standby mode 50 Table 27 PLL characteristics Symbol Parameter Value Unit Min1 1 Guaranteed based on test during characterization Typ Max1 fPLLIN PLL input clock2 2 Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLLOUT 1 80 25 MHz PLL input clock duty cycle 40 60 fPLLOUT PLL multiplier output clock 16 72 MHz tLOCK PLL lock time 200 µs Jitter Cycletocycle jitter 300 ps Table 28 Flash memory characteristics Symbol Parameter Conditions Min1 Typ Max1 Unit tprog 16bit programming time TA 40 to 105 C 40 525 70 µs tERASE Page 1 KB erase time TA 40 to 105 C 20 40 ms tME Mass erase time TA 40 to 105 C 20 40 Electrical characteristics STM32F103x8 STM32F103xB 58117 DocID13587 Rev 17 5310 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization Functional EMS electromagnetic susceptibility While a simple application is executed on the device toggling 2 LEDs through IO ports the device is stressed by two electromagnetic events until a failure occurs The failure is indicated by the LEDs Electrostatic discharge ESD positive and negative is applied to all device pins until a functional disturbance occurs This test is compliant with the IEC 6100042 standard FTB A Burst of Fast Transient voltage positive and negative is applied to VDD and VSS through a 100 pF capacitor until a functional disturbance occurs This test is compliant with the IEC 6100044 standard A device reset allows normal operations to be resumed The test results are given in Table 30 They are based on the EMS levels and classes defined in application note AN1709 IDD Supply current Read mode fHCLK 72 MHz with 2 wait states VDD 33 V 20 mA Write Erase modes fHCLK 72 MHz VDD 33 V 5 Powerdown mode Halt VDD 30 to 36 V 50 µA Vprog Programming voltage 2 36 V 1 Guaranteed by design Table 29 Flash memory endurance and data retention Symbol Parameter Conditions Value Unit Min1 1 Guaranteed based on test during characterization Typ Max NEND Endurance TA 40 to 85 C 6 suffix versions TA 40 to 105 C 7 suffix versions 10 kcycles tRET Data retention 1 kcycle2 at TA 85 C 2 Cycling performed over the whole temperature range 30 Years 1 kcycle2 at TA 105 C 10 10 kcycles2 at TA 55 C 20 Table 28 Flash memory characteristics continued Symbol Parameter Conditions Min1 Typ Max1 Unit DocID13587 Rev 17 59117 STM32F103x8 STM32F103xB Electrical characteristics 116 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as Corrupted program counter Unexpected reset Critical Data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Electromagnetic Interference EMI The electromagnetic field emitted by the device are monitored while a simple application is executed toggling 2 LEDs through the IO ports This emission test is compliant with IEC 619672 standard which specifies the test board and the pin loading Table 30 EMS characteristics Symbol Parameter Conditions Level Class VFESD Voltage limits to be applied on any IO pin to induce a functional disturbance VDD 33 V TA 25 C fHCLK 72 MHz conforms to IEC 6100042 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD 33 V TA 25 C fHCLK 72 MHz conforms to IEC 6100044 4A Table 31 EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs fHSEfHCLK Unit 848 MHz 872 MHz SEMI Peak level VDD 33 V TA 25 C LQFP100 package compliant with IEC 619672 01 to 30 MHz 12 12 dBµV 30 to 130 MHz 22 19 130 MHz to 1GHz 23 29 SAE EMI Level 4 4 Electrical characteristics STM32F103x8 STM32F103xB 60117 DocID13587 Rev 17 5311 Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU using specific measurement methods the device is stressed in order to determine its performance in terms of electrical sensitivity Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n1 supply pins This test conforms to the JESD22A114C101 standard Static latchup Two complementary static tests are required on six parts to assess the latchup performance A supply overvoltage is applied to each power supply pin A current injection is applied to each input output and configurable IO pin These tests are compliant with EIAJESD 78A IC latchup standard Table 32 ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value1 1 Guaranteed based on test during characterization Unit VESDHBM Electrostatic discharge voltage human body model TA 25 C conforming to JESD22A114 2 2000 V VESDCDM Electrostatic discharge voltage charge device model TA 25 C conforming to ANSIESD STM531 II 500 Table 33 Electrical sensitivities Symbol Parameter Conditions Class LU Static latchup class TA 105 C conforming to JESD78A II level A DocID13587 Rev 17 61117 STM32F103x8 STM32F103xB Electrical characteristics 116 5312 IO current injection characteristics As a general rule current injection to the IO pins due to external voltage below VSS or above VDD for standard 3 Vcapable IO pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization Functional susceptibilty to IO current injection While a simple application is executed on the device the device is stressed by injecting current into the IO pins programmed in floating input mode While current is injected into the IO pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error above a certain limit 5 LSB TUE out of spec current injection on adjacent pins or other functional failure for example reset oscillator frequency deviation The test results are given in Table 34 Table 34 IO current injection susceptibility Symbol Description Functional susceptibility Unit Negative injection Positive injection IINJ Injected current on OSCIN32 OSCOUT32 PA4 PA5 PC13 0 0 mA Injected current on all FT pins 5 0 Injected current on any other pin 5 5 Electrical characteristics STM32F103x8 STM32F103xB 62117 DocID13587 Rev 17 5313 IO port characteristics General inputoutput characteristics Unless otherwise specified the parameters given in Table 35 are derived from tests performed under the conditions summarized in Table 9 All IOs are CMOS and TTL compliant Table 35 IO static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Low level input voltage Standard IO input low level voltage 028VDD2 V08 V1 V IO FT3 input low level voltage 032VDD2V075 V1 All IOs except BOOT0 035VDD 2 VIH High level input voltage Standard IO input high level voltage 041VDD2 V13 V1 IO FT3 input high level voltage 042VDD2 V1 V1 All IOs except BOOT0 065VDD 2 Vhys Standard IO Schmitt trigger voltage hysteresis4 200 mV IO FT Schmitt trigger voltage hysteresis4 5 VDD 5 Ilkg Input leakage current 6 VSS VIN VDD Standard IOs 1 µA VIN 5 V IO FT 3 RPU Weak pullup equivalent resistor7 VIN VSS 30 40 50 kΩ RPD Weak pulldown equivalent resistor7 VIN VDD 30 40 50 CIO IO pin capacitance 5 pF 1 Data based on design simulation 2 Tested in production 3 FT Fivevolt tolerant In order to sustain a voltage higher than VDD03 the internal pulluppulldown resistors must be disabled 4 Hysteresis voltage between Schmitt trigger switching levels Guaranteed based on test during characterization 5 With a minimum of 100 mV 6 Leakage could be higher than max if negative current is injected on adjacent pins STM32F103x8 STM32F103xB Electrical characteristics 7 Pullup and pulldown resistors are designed with a true resistance in series with a switchable PMOSNMOS This PMOSNMOS contribution to the series resistance is minimum 10 order All Os are CMOS and TTL compliant no software configuration required Their characteristics cover more than the strict CMOStechnology or TTL parameters The coverage of these requirements is shown in Figure 26 and Figure 27 for standard lOs and in Figure 28 and Figure 29 for 5 V tolerant IOs Figure 26 Standard IO input characteristics CMOS port VIHVIL V Area not determined 065V pD srement Vit 13 gard require oAWVpp2tt mos stay Vin san simulations 756 Based on design S duction 171 7 Vann208 Tested in pr 1159 125 Vy2028D0 simulations Vinmin 13b 1 ee Based on design Tite eee eee iV 035Vpp Vitmax O8bk CMOS standard requiremen IL 07 tion 1 l Il 1 Tested in product 1 I I 1 1 1 1 1 1 Vpp V 2 27 3 33 36 Dp ai17277c Figure 27 Standard IO input characteristics TTL port ViHViL V Area not determined TTL requi ts Vyy2V 3 ViHmin 20 iceland vypcoa 002 Jations 796 Based on desion simu 028Vpp208 13 ee vie en design simulations 1 1 Vitmax 08 1 TTL requirements Vj 08V 1 1 1 1 2 216 36 Vpp V ai17278b ky DoclD13587 Rev 17 63117 Electrical characteristics STM32F103x8 STM32F103xB Figure 28 5 V tolerant IO input characteristics CMOS port VinVIL VY Area not determined 065V irements V H208 py cmos standard rool 21 Meer simulations guction 167 Bas 2075 ted in pro T551 1 032Vpp sons i3 ee ee 1 pked on design simulation 1295 1 1 art Vy 035VDD1 0975 rd requirmeny IL o7 278 Pree cMog standa 7 I 1 1 Tested in production I I I 1 1 1 Vpp V 2 27 3 33 36 VDD ai17279c Figure 29 5 V tolerant IO input characteristics TTL port ViHVIL VY Wy Area not Y determined ool Yi TTL requirement V42V seca 0 ons L V 2075 ct og tn Hmin coc orS9 Saaeaaan4 1 Vitmax nol one 075 TTL requirements Vj 08V 1 1 1 1 2 216 36 VDD V ai17280b 64117 DoclD13587 Rev 17 ky DocID13587 Rev 17 65117 STM32F103x8 STM32F103xB Electrical characteristics 116 Output driving current The GPIOs generalpurpose inputsoutputs can sink or source up to 8 mA and sink or source up to 20 mA with a relaxed VOLVOH except PC13 PC14 and PC15 which can sink or source up to 3mA When using the GPIOs PC13 to PC15 in output mode the speed should not exceed 2 MHz with a maximum load of 30 pF In the user application the number of IO pins which can drive current must be limited to respect the absolute maximum rating specified in Section 52 The sum of the currents sourced by all the IOs on VDD plus the maximum Run consumption of the MCU sourced on VDD cannot exceed the absolute maximum rating IVDD see Table 7 The sum of the currents sunk by all the IOs on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS see Table 7 Output voltage levels Unless otherwise specified the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9 All IOs are CMOS and TTL compliant Table 36 Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL 1 1 The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO IO ports and control pins must not exceed IVSS Output low level voltage for an IO pin when 8 pins are sunk at same time CMOS port2 IIO 8 mA 27 V VDD 36 V 2 TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52 04 V VOH 3 3 The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO IO ports and control pins must not exceed IVDD Output high level voltage for an IO pin when 8 pins are sourced at same time VDD04 VOL 1 Output low level voltage for an IO pin when 8 pins are sunk at same time TTL port2 IIO 8mA 27 V VDD 36 V 04 VOH 3 Output high level voltage for an IO pin when 8 pins are sourced at same time 24 VOL 14 4 Guaranteed based on test during characterization Output low level voltage for an IO pin when 8 pins are sunk at same time IIO 20 mA 27 V VDD 36 V 13 VOH 34 Output high level voltage for an IO pin when 8 pins are sourced at same time VDD13 VOL 14 Output low level voltage for an IO pin when 8 pins are sunk at same time IIO 6 mA 2 V VDD 27 V 04 VOH 34 Output high level voltage for an IO pin when 8 pins are sourced at same time VDD04 Electrical characteristics STM32F103x8 STM32F103xB 66117 DocID13587 Rev 17 Inputoutput AC characteristics The definition and values of inputoutput AC characteristics are given in Figure 30 and Table 37 respectively Unless otherwise specified the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9 Table 37 IO AC characteristics1 1 The IO speed is configured using the MODEx10 bits Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register MODEx10 bit value1 Symbol Parameter Conditions Min Max Unit 10 fmaxIOout Maximum frequency2 2 The maximum frequency is defined in Figure 30 CL 50 pF VDD 2 V to 36 V 2 MHz tfIOout Output high to low level fall time CL 50 pF VDD 2 V to 36 V 1253 3 Guaranteed by design ns trIOout Output low to high level rise time 1253 01 fmaxIOout Maximum frequency2 CL 50 pF VDD 2 V to 36 V 10 MHz tfIOout Output high to low level fall time CL 50 pF VDD 2 V to 36 V 253 ns trIOout Output low to high level rise time 253 11 FmaxIOout Maximum frequency2 CL 30 pF VDD 27 V to 36 V 50 MHz CL 50 pF VDD 27 V to 36 V 30 CL 50 pF VDD 2 V to 27 V 20 tfIOout Output high to low level fall time CL 30 pF VDD 27 V to 36 V 53 ns CL 50 pF VDD 27 V to 36 V 83 CL 50 pF VDD 2 V to 27 V 123 trIOout Output low to high level rise time CL 30 pF VDD 27 V to 36 V 53 CL 50 pF VDD 27 V to 36 V 83 CL 50 pF VDD 2 V to 27 V 123 tEXTIpw Pulse width of external signals detected by the EXTI controller 10 ns STM32F103x8 STM32F103xB Electrical characteristics Figure 30 IO AC characteristics definition 90 10 50 fF DQ50 10 90 I EXTERNAL tOout ttiojout OUTPUT ON 50pF AM SOT Maximum frequency is achieved if t ts 23T and if the duty cycle is 4555 when loaded by 50pF ai14131 5314 NRST pin characteristics The NRST pin input driver uses CMOS technology It is connected to a permanent pullup resistor Rpy see Table 35 Unless otherwise specified the parameters given in Table 38 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 9 Table 38 NRST pin characteristics sym Parmeter Conon in yp x Unt wRsT 08 NRST Schmitt trigger voltage VhysNRST hysteresis 200 mv 1 Guaranteed by design 2 The pullup is designed with a true resistance in series with a switchable PMOS This PMOS contribution to the series resistance must be minimum 10 order ky DoclD13587 Rev 17 67117 Electrical characteristics STM32F103x8 STM32F103xB Figure 31 Recommended NRST pin protection V External zp reset circuit Ber NRST2 RPU Internal reset i O Filter oh 01 UF SS STM32F10x ai14132d 2 The reset network protects the device against parasitic resets 3 The user must ensure that the level on the NRST pin can go below the Vi yrst Max level specified in Table 38 Otherwise the reset will not be taken into account by the device 5315 TIM timer characteristics The parameters given in Table 39 are guaranteed by design Refer to Section 5312 IO current injection characteristics for details on the inputoutput alternate function characteristics output compare input capture external clock PWM output Table 39 TIMx characteristics Symbol Peet condone win tox Unt ee es tresTIM Timer resolution time a tcouNTER when internal clock is tax count Maximum possible count 1 TIMx is used as a general term to refer to the TIM1 TIM2 TIM3 and TIM4 timers 68117 DoclD13587 Rev 17 kyy DocID13587 Rev 17 69117 STM32F103x8 STM32F103xB Electrical characteristics 116 5316 Communications interfaces I2C interface characteristics The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions the IO pins SDA and SCL are mapped to are not true opendrain When configured as opendrain the PMOS connected between the IO pin and VDD is disabled but is still present The I2C characteristics are described in Table 40 Refer also to Section 5312 IO current injection characteristics for more details on the inputoutput alternate function characteristics SDA and SCL Table 40 I2C characteristics Symbol Parameter Standard mode I2C12 1 Guaranteed by design Fast mode I2C12 2 fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies It must be at least 4 MHz to achieve fast mode I2C frequencies It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock Unit Min Max Min Max twSCLL SCL clock low time 47 13 µs twSCLH SCL clock high time 40 06 tsuSDA SDA setup time 250 100 ns thSDA SDA data hold time 34503 9003 3 The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal trSDA trSCL SDA and SCL rise time 1000 300 tfSDA tfSCL SDA and SCL fall time 300 300 thSTA Start condition hold time 40 06 µs tsuSTA Repeated Start condition setup time 47 06 tsuSTO Stop condition setup time 40 06 μs twSTOSTA Stop to Start condition time bus free 47 13 μs Cb Capacitive load for each bus line 400 400 pF tSP Pulse width of spikes that are suppressed by the analog filter 0 504 4 The minimum width of the spikes filtered by the analog filter is above tSPmax 0 504 ns Electrical characteristics STM32F103x8 STM32F103xB Figure 32 I7C bus AC waveforms and measurement circuit Vpbl2c YDD12c Rp Rp STM32F 10x Rs SDA wbes Start repeated Start ween 7 Start susTaA os MA XX NT 1 1 I 1 1 1 tSDA PH Pe tSDA tsuSDA me oy 1 Stbp 1 tsuSTOSTA r thSTA wSCltH thSDA 1 1 SCL i 1 uf twSCLL 7 SCL PM Pr tSCL suSTO ai14133g 1 Measurement points are done at CMOS levels 03Vpp and 07Vpp 2 Rs Series protection resistors Rp Pullup resistors Vpp jac 2C bus supply Table 41 SCL frequency fpcK1 36 MHZVpp jac 33 V I2CCCR value fsci KHz Rp 47 kQ 1 Rp External pullup resistance fgc IC speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges the tolerance on the achieved speed 42 These variations depend on the accuracy of the external components used to design the application 70117 DoclD13587 Rev 17 ky DocID13587 Rev 17 71117 STM32F103x8 STM32F103xB Electrical characteristics 116 SPI interface characteristics Unless otherwise specified the parameters given in Table 42 are derived from tests performed under the ambient temperature fPCLKx frequency and VDD supply voltage conditions summarized in Table 9 Refer to Section 5312 IO current injection characteristics for more details on the inputoutput alternate function characteristics NSS SCK MOSI MISO Table 42 SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK 1tcSCK SPI clock frequency Master mode 18 MHz Slave mode 18 trSCK tfSCK SPI clock rise and fall time Capacitive load C 30 pF 8 ns DuCySCK SPI slave input clock duty cycle Slave mode 30 70 tsuNSS 1 1 Guaranteed based on test during characterization NSS setup time Slave mode 4tPCLK ns thNSS 1 NSS hold time Slave mode 2tPCLK twSCKH 1 twSCKL 1 SCK high and low time Master mode fPCLK 36 MHz presc 4 50 60 tsuMI 1 tsuSI 1 Data input setup time Master mode 5 Slave mode 5 thMI 1 Data input hold time Master mode 5 thSI 1 Slave mode 4 taSO 12 2 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data Data output access time Slave mode fPCLK 20 MHz 0 3tPCLK tdisSO 13 3 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in HiZ Data output disable time Slave mode 2 10 tvSO 1 Data output valid time Slave mode after enable edge 25 tvMO 1 Data output valid time Master mode after enable edge 5 thSO 1 Data output hold time Slave mode after enable edge 15 thMO 1 Master mode after enable edge 2 Electrical characteristics STM32F103x8 STM32F103xB Figure 33 SPI timing diagram slave mode and CPHA 0 NSS input tSUNSS 1g ptg tesck thinss 1 1 1 oo 4 5 CPHA0 t 2 CPOL0 twSCKH 1 Nl 1 1 1 1 CPHA0 1 twSckL i 1 CPOL1 1 a TT y 1 r mM trisc 1 tvso thSO qpi png InSCK tdisSO gp taSo 1 thSCK 1 o 1 MISO MSB OUT BIT6 OUT LSB OUT OUTPUT tsuSl rd Mos INPUT ry MSB IN BIT1 IN XK issn XX IN tvs ai14134c Figure 34 SPI timing diagram slave mode and CPHA 41 NSS input tsUNSS 4 tcSCk thNSs 1 I I I 1 3 CPHA1 1 1 o S CPOL0 hScKny 7 1 1 CPHA1 twSCKL i r CPOL1 I I 1 tvSo ae thSO tSCk oe tdisSO taSO r iW tfSCk 1 ms ounPar MSB OUT é BIT6 OUT LSB OUT I tsuSl thSl 1 MOSI INPUT 1 MSB IN 1 BIT 1 IN LSB IN ai14135b 1 Measurement points are done at CMOS levels 03Vpp and 07Vpp 72117 DoclD13587 Rev 17 kyy STM32F103x8 STM32F103xB Electrical characteristics Figure 35 SPI timing diagram master mode High NSS input t tescky B CPOL0 i x CPHA0 i u B CPOL1 ey f r 3 cPHa1 jf CPOL0 SN x CPHA1 i 8 CPOL1 Vf F 1 1 1 1 1 twSCKH pp tWsck Miso tsuMI twSCKL 1 rit tsi th OUTPUT MSBOUT BIT1OUT 1 LSB OUT tyMO thMO ai14136c 1 Measurement points are done at CMOS levels 03Vpp and 07Vpp USB characteristics The USB interface is USBIF certified Full Speed Table 43 USB startup time 1 Guaranteed by design ky DoclD13587 Rev 17 73117 Electrical characteristics STM32F103x8 STM32F103xB Table 44 USB DC electrical characteristics Symi Parmer main win wn un Input levels Differential input sensitivity lUSBDP USBDM 02 Differential common mode range Includes Vp range os 25 Vv Output levels Static output level low R of 15 kQto 36 VO 03 V Static output level high Ry of 15 kQto Veg 1 All the voltages are measured from the local ground potential 2 To be compliant with the USB 20 fullspeed electrical specification the USBDP D pin should be pulled up with a 15 kQ resistor to a 30to36 V voltage range 3 The STM32F103xx USB functionality is ensured down to 27 V but not the full USB electrical characteristics which are degraded in the 27to30 V Vpp voltage range 4 Guaranteed by design 5 R is the load connected on the USB drivers Figure 36 USB timings definition of data signal rise and fall time Crossover points Differential data lines Vers na Vss ee eee ee tf p tr p ai14137 Table 45 USB Fullspeed electrical characteristics Driver characteristics 1 Guaranteed by design 2 Measured from 10 to 90 of the data signal For more detailed informations please refer to USB Specification Section 7 version 20 5317 CAN controller area network interface Refer to Section 5312 IO current injection characteristics for more details on the inputoutput alternate function characteristics CANTX and CANRX 74117 DoclD13587 Rev 17 ky DocID13587 Rev 17 75117 STM32F103x8 STM32F103xB Electrical characteristics 116 5318 12bit ADC characteristics Unless otherwise specified the parameters given in Table 46 are derived from tests performed under the ambient temperature fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9 Note It is recommended to perform a calibration after each powerup Table 46 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 24 36 V VREF Positive reference voltage 24 VDDA V IVREF Current on the VREF input pin 1601 2201 µA fADC ADC clock frequency 06 14 MHz fS 2 Sampling rate 005 1 MHz fTRIG 2 External trigger frequency fADC 14 MHz 823 kHz 17 1fADC VAIN 3 Conversion voltage range 0 VSSA or VREF tied to ground VREF V RAIN 2 External input impedance See Equation 1 and Table 47 for details 50 kΩ RADC 2 Sampling switch resistance 1 kΩ CADC 2 Internal sample and hold capacitor 8 pF tCAL 2 Calibration time fADC 14 MHz 59 µs 83 1fADC tlat 2 Injection trigger conversion latency fADC 14 MHz 0214 µs 34 1fADC tlatr 2 Regular trigger conversion latency fADC 14 MHz 0143 µs 24 1fADC tS 2 Sampling time fADC 14 MHz 0107 171 µs 15 2395 1fADC tSTAB 2 Powerup time 0 0 1 µs tCONV 2 Total conversion time including sampling time fADC 14 MHz 1 18 µs 14 to 252 tS for sampling 125 for successive approximation 1fADC 1 Guaranteed based on test during characterization 2 Guaranteed by design 3 In devices delivered in VFQFPN and LQFP packages VREF is internally connected to VDDA and VREF is internally connected to VSSA Devices that come in the TFBGA64 package have a VREF pin but no VREF pin VREF is internally connected to VSSA see Table 5 and Figure 7 4 For external triggers a delay of 1fPCLK2 must be added to the latency specified in Table 46 Electrical characteristics STM32F103x8 STM32F103xB 76117 DocID13587 Rev 17 Equation 1 RAIN max formula The formula above Equation 1 is used to determine the maximum external impedance allowed for an error below 14 of LSB Here N 12 from 12bit resolution Table 47 RAIN max for fADC 14 MHz1 1 Guaranteed based on test during characterization Ts cycles tS µs RAIN max kΩ 15 011 04 75 054 59 135 096 114 285 204 252 415 296 372 555 396 50 715 511 NA 2395 171 NA Table 48 ADC accuracy limited test conditions1 2 1 ADC DC accuracy values are measured after internal calibration 2 ADC Accuracy vs Negative Injection Current Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to analog pins which may potentially inject negative currents Any positive injection current within the limits specified for IINJPIN and ΣIINJPIN in Section 5312 does not affect the ADC accuracy Symbol Parameter Test conditions Typ Max3 3 Guaranteed based on test during characterization Unit ET Total unadjusted error fPCLK2 56 MHz fADC 14 MHz RAIN 10 kΩ VDDA 3 V to 36 V TA 25 C Measurements made after ADC calibration 13 2 LSB EO Offset error 1 15 EG Gain error 05 15 ED Differential linearity error 07 1 EL Integral linearity error 08 15 RAIN TS fADC CADC 2 N 2 ln RADC STM32F103x8 STM32F103xB Electrical characteristics Table 49 ADC accuracy 2 3 fpciK2 56 MHz Differential linearity error Measurements made after ADC calibration 1 ADC DC accuracy values are measured after internal calibration 2 Better performance could be achieved in restricted Vpp frequency and temperature ranges 3 ADC Accuracy vs Negative Injection Current Injecting negative current on any of the standard non robust analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for lijjpiny AN ZlingPiny in Section 5312 does not affect the ADC accuracy 4 Guaranteed based on test during characterization Figure 37 ADC accuracy characteristics VREF VDDA 1LSB IDEAL 4096 or 096 depending on package 4095 e 4 Ec 1 Example of an actu al transfer curve 7 fi 2 The ideal transfer cu rve 4094 TT 3 End point correlation line 4093 zo ey oO Et Total unadjusted Error maximum deviation Er vo 1 between the actual and the ideal transfer curves 7 3 Eo Offset Error deviation between the first actual nr transition and the last actual one 6 yy 7 1 Ec Gain Error deviation between the last ideal 5 rd transition and the last actual one Eo A477 EL Ep Differential Linearity Error maximum deviation 4 Z 1 y UC 1 between actual steps and the ideal one 3 7 e Ed EL Integral Linearity Error maximum deviation 2 1 2 z 1 between any actual transition and the endpoint 1 a and 1 LSB IDEAL correlation line 0 12 3 4 5 6 7 4093 4094 4095 4096 VSsA VDDA ai14395e ky DoclD13587 Rev 17 77117 Electrical characteristics STM32F103x8 STM32F103xB Figure 38 Typical connection diagram using the ADC Vpp STM32F103xx V Sample and hold ADC T converter 1 oS 08 Rape RAIN AINx ADC 12bit I 1 A converter Gain Cparasitic aN VT GC TL 06 V Capo ai14150c 1 Refer to Table 46 for the values of Rain Rapc and Capc 2 Coarasitic represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance roughly 7 pF A high Cparasitic Value will downgrade conversion accuracy To remedy this fapc should be reduced General PCB design guidelines Power supply decoupling should be performed as shown in Figure 39 or Figure 40 depending on whether Vref is connected to Vpp or not The 10 nF capacitors should be ceramic good quality They should be placed them as close as possible to the chip Figure 39 Power supply and reference decoupling Vpers not connected to Vppa STM32F103xx VREF T see note 1 1 UF 10 nF Vppa a 1 uF 10 nF Vssa VREF see note 1 ai14388b 1 Vper and Veer inputs are available only on 100pin packages 78117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Electrical characteristics Figure 40 Power supply and reference decoupling Vpers connected to Vppa STM32F103xx VrerVppa I See note 1 1 UF 10 nF VrerVssa See note 1 ai14389 1 Vper and Veer inputs are available only on 100pin packages 5319 Temperature sensor characteristics Table 50 TS characteristics sym Paar r ye Max Oat ADC sampling time when reading the 32 Ts temp temperature 171 HS 1 Guaranteed based on test during characterization 2 Guaranteed by design 3 Shortest sampling time can be determined in the application by multiple iterations ky DoclD13587 Rev 17 79117 Package information STM32F103x8 STM32F103xB 6 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at wwwstcom ECOPACK is an ST trademark 61 VFQFPN36 6 x 6 mm 05 mm pitch package information Figure 41 VFQFPN36 36pin 6x6 mm 05 mm pitch very thin profile fine pitch quad flat package outline Seating plane laad Cc Lj fj f fj fj 4 CI A3 A1 FE oe b 27 19 28 Cc CT CT e C D Cc C Cc CT K 36 Anannannn t Pin 1 1D 9 Lf R020 E ZRMEV2 1 Drawing is not to scale 80117 DoclD13587 Rev 17 kyy DocID13587 Rev 17 81117 STM32F103x8 STM32F103xB Package information 116 Table 51 VFQFPN36 36pin 6x6 mm 05 mm pitch very thin profile fine pitch quad flat package mechanical data Symbol millimeters inches1 1 Values in inches are converted from mm and rounded to 4 decimal digits Min Typ Max Min Typ Max A 0800 0900 1000 00315 00354 00394 A1 0020 0050 00008 00020 A2 0650 1000 00256 00394 A3 0250 00098 b 0180 0230 0300 00071 00091 00118 D 5875 6000 6125 02313 02362 02411 D2 1750 3700 4250 00689 01457 01673 E 5875 6000 6125 02313 02362 02411 E2 1750 3700 4250 00689 01457 01673 e 0450 0500 0550 00177 00197 00217 L 0350 0550 0750 00138 00217 00295 K 0250 00098 ddd 0080 00031 Package information STM32F103x8 STM32F103xB Figure 42 VFQFPN36 36pin 6x6 mm 05 mm pitch very thin profile fine pitch quad flat package recommended footprint ANN 100 TT 60 430 E ca co 480 1 o30et be 630 ZRFPV1 82117 DoclD13587 Rev 17 kyy STM32F103x8 STM32F103xB Package information Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 43 VFPFPN36 package top view example Product identification NX STM32 FLOSTSUB Date code Revision code Pin 1 indentifier WI R MSv37531V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity ky DoclD13587 Rev 17 83117 Package information STM32F103x8 STM32F103xB 62 UFQFPN48 7 x 7 mm 05 mm pitch package information Figure 44 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package outline Pin 1 identifier laser marking area D A E E i seating al ddd TA a1 Pe Jv Vv 2 oy Detail Y D TO Y ae Yi 5 Exposed pad L Na OTK t LY Y pint comer NS R 0125 typ CJ pin1 corner p y Yi Y d e Detail Z 0 00 nhoolo DODD D z A0B9MEV3 1 Drawing is not to scale 2 There is an exposed die pad on the underside of the QFPN package this pad is not internally connected to the VSS or VDD power pads It is recommended to connect it to VSS 3 All leadspads should also be soldered to the PCB to improve the lead solder joint life Table 52 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package mechanical data min Pe mex min e e ee 7000 7s00 ara oars ores 84117 DocID13587 Rev 17 ky STM32F103x8 STM32F103xB Package information Table 52 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package mechanical data continued ee ee ee a 9200 oaso oa0o eaare couse acne ef e800 footer Fe 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 45 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package recommended footprint 730 620 goooooocoo0s C9 GI 4 Co Co CI Co o20L 560 oO iS Co 730 oO Co 620 co co 580 Co Co CO 4 560 a 03074 oO fo Co f He 050 075 580 AOB9FPV2 1 Dimensions are expressed in millimeters ky DoclD13587 Rev 17 85117 Package information STM32F103x8 STM32F103xB Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 46 UFQFPN48 7 x 7 mm 05 mm pitch package top view example Product identification 1 SJ STM32F LOSCBUL Date code Pin 1 wo identifier kaw yj C Revision code MS37524V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity 86117 DocID13587 Rev 17 ky STM32F103x8 STM32F103xB Package information 63 LFBGA100 10 x 10 mm lowprofile fine pitch ball grid array package information Figure 47 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x10 mm 08 mm pitch package outline ZSeating plane Pp yf Sddd Z 7 uuu UU UU UU A4 A2 MOA EI Al ball A1 ball F identifier index area E co LT a Wi Al PO0000000G Wy OODOODO0O00O0 F LA OODOOVO0O00O0 OOOOOO0O000 OOO00O0000 D1 D OOOOOO0O0C0O OOOOO0O00CO0O e OODOOVO0O00O0 COO0O00000 rt K OOOO0000Q0 10 1 BOTTOM VIEW b 100 balls TOP VIEW Z HOMEV2 1 Drawing is not to scale Table 53 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x 10 mm 08 mm pitch package mechanical data min tye ax min e x Aro a ear foros Faas Fo s00 asso oni aviary ona er fram foes er foes a a aes oar ky DoclD13587 Rev 17 87117 Package information STM32F103x8 STM32F103xB Table 53 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x 10 mm 08 mm pitch package mechanical data continued min tye amin e x ee 80009 nn toa 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 48 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x 10 mm 08 mm pitch package recommended footprint ODODODODOO 09000000000 joa 0000000000 ODODODDDDODO sm OOD0D00OO OODDDDO0OODO OODOD0000O OODDDDO0ODOO OOO0O0O00OO OOD00000009O Ho FP V1 Table 54 LFBGA100 recommended PCB design rules 08 mm pitch BGA Bimamon Racormended vane a maton rcpenss on me selsemesk 0 Dsm istration tolerance 88117 DoclD13587 Rev 17 kyy STM32F103x8 STM32F103xB Package information Marking of engineering samples The following figure gives an example of topside marking orientation versus ball A1 identifier location Figure 49 LFBGA100 package top view example Product identification Revision code STM32F103 VHE Date code year week TL Ball A1 Cw Cy ee WJ C MSv37525V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity ky DoclD13587 Rev 17 89117 Package information STM32F103x8 STM32F103xB 64 LQFP100 14 x 14 mm 100pin lowprofile quad flat package information Figure 50 LQFP100 14 x 14 mm 100pin lowprofile quad flat package outline SEATING PLANE clare ax al eel TY rE dCs z vy D1 4 D3 74 5 76 q i rs ee uu 1 10Gamj p PIN 1 5 IDENTIFICATION He 1LMEV5 Table 55 LQPF100 14 x 14 mm 100pin lowprofile quad flat package mechanical data A nn pomin tye mex min typ x PA 800 80880 ooo 0150 00020 00089 1350 1400 1450 00531 00551 00571 ob 0170 0220 0270 00067 00087 00106 a es 2 Dp 15800 16000 16200 06220 06299 06378 13800 14000 14200 05433 05512 05591 pos e000 tree 15800 1600 16200 06220 06299 06378 13800 14000 14200 05433 05512 05591 a ne ee 90117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Package information Table 55 LQPF100 14 x 14 mm 100pin lowprofile quad flat package mechanical data continued Min e ain ex a a eo a oa a 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 51 LQFP100 100pin 14 x 14 mm lowprofile quad flat package recommended footprint 75 51 ODD000000000000000000000 05 cc SS SS SS 03 SS SS 167 143 C3 SS ca cc SS SS SS ca cc SS SS SS SS 100 26 DOONDDOUODODOUUODDOOUoL 12 123 167 ai14906c 1 Dimensions are expressed in millimeters ky DoclD13587 Rev 17 91117 Package information STM32F103x8 STM32F103xB Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 52 LQFP100 package top view example Product identification STMS3e2F1L03 VTE R Revision code Ld Pin 1 o indentifier MSv37526V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity 92117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Package information 65 UFBGA100 7x 7 mm ultra fine pitch ball grid array package information Figure 53 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package outline Seating plane Addd Z ee A4 3 A2 ALA E1 Al ball A1 ball r e F 5 identifier index area E 7 Al 000000000 UY OO0O0O000000000 O0000 O0000 F LL Oo0oOo Oo0Oo Oooo Oooo OOo oOo 00 00 D1 D O0OO O0OO Oooo Oo0oo e O0000 Oo0000 CO0000000C0O0CG Y M O0O000000O0C0CCG Y 12 1 BOTTOM VIEW b 100 balls TOP VIEW oS eta AO0C2MEV4 1 Drawing is not to scale Table 56 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package mechanical data A nn we te we wn e oe 0460 0530 0600 00181 00209 00236 0050 0080 0110 00020 00031 00043 0400 0450 0500 00157 00177 00197 0080 0130 0180 00031 00051 00071 0270 0320 0370 00106 00126 00146 ob 0200 0250 0300 00079 00098 00118 oD 6950 7000 7050 02736 02756 02776 5450 5500 5550 02146 02165 02185 6950 7000 7050 02736 02756 02776 5450 5500 5550 02146 02165 02185 0700 0750 0800 00276 00295 00315 ky DoclD13587 Rev 17 93117 Package information STM32F103x8 STM32F103xB Table 56 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package mechanical data continued Min tye mex min tye Mex we mt a a 0500020 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 54 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package recommended footprint OODDDDDODDODO ODODDDDOODDODO 00000 O0000 o09O 0090 8388 Dpad Ooo OO 000 ooo ws o09O Ooo 00000 00000 ODDDDDDODDODO ODDDDDD0DDODO AOC2FPV1 Table 57 UFBGA100 recommended PCB design rules 05 mm pitch BGA Bimenson Racommondatvaes pm 0370 mm typ depends on the soldermask reg Dsm istration tolerance 94117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Package information Marking of engineering samples The following figure gives an example of topside marking orientation versus ball A1 identifier location Figure 55 UFBGA100 package top view example Product identification SS STM32F LOSVBIb Date code Ball A1 Revision code identifier A yj IR Visi MS37527V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity ky DoclD13587 Rev 17 95117 Package information STM32F103x8 STM32F103xB 66 LQFP64 10 x 10 mm 64pin lowprofile quad flat package information Figure 56 LQFP64 64pin 10 x 10 mm lowprofile quad flat package outline SEATING PLANE x JIT 7 nN Pe IS D St k D1 L D3 L1 48 33 Ga AULT ILI LL AQ ae Le bp 3 g gu FI Sy 64 W y 17 THTTTT TUT Toon Oooo oo OOOO PIN 1 1 il 16 IDENTIFICATION ely 5WMEV3 1 Drawing is not to scale Table 58 LQFP64 64pin 10 x 10 mm lowprofile quad flat package mechanical data ee ee Pp oA fT Teo fF 0680 at oso ots0 ooo20 00089 b otro 0220 0270 00067 0087 00106 pe oo 0200 oooss 00079 a a a a a Poe f 2000 mre per tooo scar 96117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Package information Table 58 LQFP64 64pin 10 x 10 mm lowprofile quad flat package mechanical data continued min tye Mee in tye a ef asc fete ef eas oe Te ae eT 000 cna ee fff aoe Pe 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 57 LQFP64 64pin 10 x 10 mm lowprofile quad flat package recommended footprint 48 33 eli 1 49 05 Sie PSE co co co co co co co co 127 co co co co co co 103 co co co co co 10353 64 17 LODOUOU00000000 12 1 16 127 ai14909c 1 Dimensions are expressed in millimeters ky DoclD13587 Rev 17 97117 Package information STM32F103x8 STM32F103xB Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 58 LQFP64 package top view example Product identification code STMS32F1L03 RTE Date code LI Pin 1 er ky C MSv37530V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity 98117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Package information 67 TFBGA64 5 x 5 mn thin profile fine pitch package information Figure 59 TFBGA64 64ball 5 x 5 mm 05 mm pitch thin profile fine pitch ball grid array package outline E1 E F Pre H PBOOOOOC OOOOC0O0O0 FE OOOO0O000O D OOO OO OOO D4 Ob 6A ball OOOOO0C0O0O as OOOCOOC0O e 77 letatcl QQCO0C0S4 B Uy Al COOO00O0 Ze 1 8 TOP VIEW A1 ball A1 ball BOTTOM VIEW index area identifier Seating plane yf id Sax Se ae ee en A4 Ae SIDE VIEW Al A R8MEV4 1 Drawing is not to scale Table 59 TFBGA64 64ball 5 x 5 mm 05 mm pitch thin profile fine pitch ball grid array package mechanical data ee ae mr SO a mf 000 Foca es ee a a Sn a a ky DoclD13587 Rev 17 99117 Package information STM32F103x8 STM32F103xB Table 59 TFBGA64 64ball 5 x 5 mm 05 mm pitch thin profile fine pitch ball grid array package mechanical data continued ee a pee oso ns Oe 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 60 TFBGA64 64ball 5 x 5 mm 05 mm pitch thin profile fine pitch ball grid array package recommended footprint ODDDD0D0DOO O909000000 Dpad OD0000D0D0O D 933989881 sm O000000 OO00000D0O OO0D00DO0DO O0000000 R8FPV1 Table 60 TFBGA64 recommended PCB design rules 05 mm pitch BGA Bimason Racorended vane Pm reget Biers one seeemask Dsm registration tolerance 100117 DoclD13587 Rev 17 ky STM32F103x8 STM32F103xB Package information Marking of engineering samples The following gives an example of topside marking orientation versus ball A1 identifier location Figure 61 TFBGA64 package top view example Product identification 3e2FL0386 Date code Revision code Ball A1 indentifier WI MSv37528V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity ky DoclD13587 Rev 17 101117 Package information STM32F103x8 STM32F103xB 68 LQFP48 7 x 7 mm 48pin lowprofile quad flat package information Figure 62 LQFP48 48pin 7 x 7 mm lowprofile quad flat package outline SEATING PLANE 42 m4 JIT elec j LL D nl K D1 A mae 37 i 48 PIN 1 TA AAA IDENTIFICATION 4 uu mt 0 1 the 5BMEV2 1 Drawing is not to scale Table 61 LQFP48 48pin 7 x 7 mm lowprofile quad flat package mechanical data win e main ex a Oe Ss 2 200 900 ones 00070 p 8000 9000 900 oaees oases oasze ee ff 8800 oats 102117 DoclD13587 Rev 17 kyy STM32F103x8 STM32F103xB Package information Table 61 LQFP48 48pin 7 x 7 mm lowprofile quad flat package mechanical data continued min te me wn e 8800 9000 9200 03465 03543 03622 6800 7000 7200 02677 02756 02835 0450 0600 0750 00177 00236 00295 SS 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 63 LQFP48 48pin 7 x 7 mm lowprofile quad flat package recommended footprint 050 120 36 25 030 c37 J cc Cc cH SS Cc 730 020 Co 970 580 co co 730 ZL a C48 130 ONO 120 580 9790 ai14911d 1 Dimensions are expressed in millimeters ky DoclD13587 Rev 17 103117 Package information STM32F103x8 STM32F103xB Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 64 LQFP48 package top view example Product identification SJ STM3e2 FIO3SCBTb Date code Pin 1 Revision code identification f yj R Visi MS37529V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity 104117 DoclD13587 Rev 17 ky DocID13587 Rev 17 105117 STM32F103x8 STM32F103xB Package information 116 69 Thermal characteristics The maximum chip junction temperature TJmax must never exceed the values given in Table 9 General operating conditions on page 38 The maximum chipjunction temperature TJ max in degrees Celsius may be calculated using the following equation TJ max TA max PD max ΘJA Where TA max is the maximum ambient temperature in C ΘJA is the package junctiontoambient thermal resistance in CW PD max is the sum of PINT max and PIO max PD max PINT max PIOmax PINT max is the product of IDD and VDD expressed in Watts This is the maximum chip internal power PIO max represents the maximum power dissipation on output pins where PIO max Σ VOL IOL ΣVDD VOH IOH taking into account the actual VOL IOL and VOH IOH of the IOs at low and high level in the application 691 Reference document JESD512 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from wwwjedecorg Table 62 Package thermal characteristics Symbol Parameter Value Unit ΘJA Thermal resistance junctionambient LFBGA100 10 10 mm 08 mm pitch 44 CW Thermal resistance junctionambient LQFP100 14 14 mm 05 mm pitch 46 Thermal resistance junctionambient UFBGA100 7 7 mm 05 mm pitch 59 Thermal resistance junctionambient LQFP64 10 10 mm 05 mm pitch 45 Thermal resistance junctionambient TFBGA64 5 5 mm 05 mm pitch 65 Thermal resistance junctionambient LQFP48 7 x 7 mm 05 mm pitch 55 Thermal resistance junctionambient UFQFPN 48 7 7 mm 05 mm pitch 32 Thermal resistance junctionambient VFQFPN 36 6 6 mm 05 mm pitch 18 Package information STM32F103x8 STM32F103xB 106117 DocID13587 Rev 17 692 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the ordering information scheme shown in Table 63 Ordering information scheme Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and to a specific maximum junction temperature As applications do not commonly use the STM32F103xx at maximum dissipation it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application The following examples show how to calculate the temperature range needed for a given application Example 1 Highperformance application Assuming the following application conditions Maximum ambient temperature TAmax 82 C measured according to JESD512 IDDmax 50 mA VDD 35 V maximum 20 IOs used at the same time in output at low level with IOL 8 mA VOL 04 V and maximum 8 IOs used at the same time in output at low level with IOL 20 mA VOL 13 V PINTmax 50 mA 35 V 175 mW PIOmax 20 8 mA 04 V 8 20 mA 13 V 272 mW This gives PINTmax 175 mW and PIOmax 272 mW PDmax 175 272 447 mW Thus PDmax 447 mW Using the values obtained in Table 62 TJmax is calculated as follows For LQFP100 46 CW TJmax 82 C 46 CW 447 mW 82 C 206 C 1026 C This is within the range of the suffix 6 version parts 40 TJ 105 C In this case parts must be ordered at least with the temperature range suffix 6 see Table 63 Ordering information scheme Example 2 Hightemperature application Using the same rules it is possible to address applications that run at high ambient temperatures with a low dissipation as long as junction temperature TJ remains within the specified range Assuming the following application conditions Maximum ambient temperature TAmax 115 C measured according to JESD512 IDDmax 20 mA VDD 35 V maximum 20 IOs used at the same time in output at low level with IOL 8 mA VOL 04 V PINTmax 20 mA 35 V 70 mW PIOmax 20 8 mA 04 V 64 mW This gives PINTmax 70 mW and PIOmax 64 mW PDmax 70 64 134 mW Thus PDmax 134 mW DocID13587 Rev 17 107117 STM32F103x8 STM32F103xB Package information 116 Using the values obtained in Table 62 TJmax is calculated as follows For LQFP100 46 CW TJmax 115 C 46 CW 134 mW 115 C 62 C 1212 C This is within the range of the suffix 7 version parts 40 TJ 125 C In this case parts must be ordered at least with the temperature range suffix 7 see Table 63 Ordering information scheme Figure 65 LQFP100 PD max vs TA 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 TA C PD mW Suffix 6 Suffix 7 Ordering information scheme STM32F103x8 STM32F103xB 108117 DocID13587 Rev 17 7 Ordering information scheme For a list of available options speed package etc or for further information on any aspect of this device please contact your nearest ST sales office Table 63 Ordering information scheme Example STM32 F 103 C 8 T 7 xxx Device family STM32 ARMbased 32bit microcontroller Product type F generalpurpose Device subfamily 103 performance line Pin count T 36 pins C 48 pins R 64 pins V 100 pins Flash memory size 8 64 Kbytes of Flash memory B 128 Kbytes of Flash memory Package H BGA I UFBGA T LQFP U VFQFPN or UFQFPN Temperature range 6 Industrial temperature range 40 to 85 C 7 Industrial temperature range 40 to 105 C Options xxx programmed parts TR tape and real DocID13587 Rev 17 109117 STM32F103x8 STM32F103xB Revision history 116 8 Revision history Table 64 Document revision history Date Revision Changes 01jun2007 1 Initial release 20Jul2007 2 Flash memory size modified in Note 9 Note 5 Note 7 Note 7 and BGA100 pins added to Table 5 Mediumdensity STM32F103xx pin definitions Figure 3 STM32F103xx performance line LFBGA100 ballout added THSE changed to TLSE in Figure 23 Lowspeed external clock source AC timing diagram VBAT ranged modified in Power supply schemes tSULSE changed to tSUHSE in Table 22 HSE 416 MHz oscillator characteristics IDDHSI max value added to Table 24 HSI oscillator characteristics Sample size modified and machine model removed in Electrostatic discharge ESD Number of parts modified and standard reference updated in Static latchup 25 C and 85 C conditions removed and class name modified in Table 33 Electrical sensitivities RPU and RPD min and max values added to Table 35 IO static characteristics RPU min and max values added to Table 38 NRST pin characteristics Figure 32 I2C bus AC waveforms and measurement circuit and Figure 31 Recommended NRST pin protection corrected Notes removed below Table 9 Table 38 Table 44 IDD typical values changed in Table 11 Maximum current consumption in Run and Sleep modes Table 39 TIMx characteristics modified tSTAB VREF value tlat and fTRIG added to Table 46 ADC characteristics In Table typical endurance and data retention for TA 85 C added data retention for TA 25 C removed VBG changed to VREFINT in Table 12 Embedded internal reference voltage Document title changed Controller area network CAN section modified Figure 14 Power supply scheme modified Features on page 1 list optimized Small text changes Revision history STM32F103x8 STM32F103xB 110117 DocID13587 Rev 17 18Oct2007 3 STM32F103CBT6 STM32F103T6 and STM32F103T8 root part numbers added see Table 2 STM32F103xx mediumdensity device features and peripheral counts VFQFPN36 package added see Section 6 Package information All packages are ECOPACK compliant Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits see Section 6 Package information Table 5 Mediumdensity STM32F103xx pin definitions updated and clarified Table 26 Lowpower mode wakeup timings updated TA min corrected in Table 12 Embedded internal reference voltage Note 2 added below Table 22 HSE 416 MHz oscillator characteristics VESDCDM value added to Table 32 ESD absolute maximum ratings Note 4 added and VOH parameter description modified in Table 36 Output voltage characteristics Note 1 modified under Table 37 IO AC characteristics Equation 1 and Table 47 RAIN max for fADC 14 MHz added to Section 5318 12bit ADC characteristics VAIN tS max tCONV VREF min and tlat max modified notes modified and tlatr added in Table 46 ADC characteristics Figure 37 ADC accuracy characteristics updated Note 1 modified below Figure 38 Typical connection diagram using the ADC Electrostatic discharge ESD on page 60 modified Number of TIM4 channels modified in Figure 1 STM32F103xx performance line block diagram Maximum current consumption Table 13 Table 14 and Table 15 updated Vhysmodified in Table 35 IO static characteristics Table 49 ADC accuracy updated VFESD value added in Table 30 EMS characteristics Values corrected note 2 modified and note 3 removed in Table 26 Lowpower mode wakeup timings Table 16 Typical and maximum current consumptions in Stop and Standby modes Typical values added for VDDVBAT 24 V Note 2 modified Note 2 added Table 21 Typical current consumption in Standby mode added On chip peripheral current consumption on page 50 added ACCHSI values updated in Table 24 HSI oscillator characteristics Vprog added to Table 28 Flash memory characteristics Upper option byte address modified in Figure 11 Memory map Typical fLSI value added in Table 25 LSI oscillator characteristics and internal RC value corrected from 32 to 40 kHz in entire document TStemp added to Table 50 TS characteristics NEND modified in Table TSvrefint added to Table 12 Embedded internal reference voltage Handling of unused pins specified in General inputoutput characteristics on page 62 All IOs are CMOS and TTL compliant Figure 39 Power supply and reference decoupling VREF not connected to VDDA modified tJITTER and fVCO removed from Table 27 PLL characteristics Appendix A Important notes on page 81 added Added Figure 16 Figure 17 Figure 19 and Figure 21 Table 64 Document revision history continued Date Revision Changes DocID13587 Rev 17 111117 STM32F103x8 STM32F103xB Revision history 116 22Nov2007 4 Document status promoted from preliminary data to datasheet The STM32F103xx is USB certified Small text changes Power supply schemes on page 15 modified Number of communication peripherals corrected for STM32F103Tx and number of GPIOs corrected for LQFP package in Table 2 STM32F103xx mediumdensity device features and peripheral counts Main function and default alternate function modified for PC14 and PC15 in Note 6 added and Remap column added in Table 5 Medium density STM32F103xx pin definitions VDDVSS ratings and Note 1 modified in Table 6 Voltage characteristics Note 1 modified in Table 7 Current characteristics Note 1 and Note 2 added in Table 11 Embedded reset and power control block characteristics IDD value at 72 MHz with peripherals enabled modified in Table 14 Maximum current consumption in Run mode code with data processing running from RAM IDD value at 72 MHz with peripherals enabled modified in Table 15 Maximum current consumption in Sleep mode code running from Flash or RAM on page 44 IDDVBAT typical value at 24 V modified and IDDVBAT maximum values added in Table 16 Typical and maximum current consumptions in Stop and Standby modes Note added in Table 17 on page 48 and Table 18 on page 49 ADC1 and ADC2 consumption and notes modified in Table 19 Peripheral current consumption tSUHSE and tSULSE conditions modified in Table 22 and Table 23 respectively Maximum values removed from Table 26 Lowpower mode wakeup timings tRET conditions modified in Table Figure 14 Power supply scheme corrected Figure 20 Typical current consumption in Stop mode with regulator in Lowpower mode versus temperature at VDD 33 V and 36 V added Note removed below Figure 33 SPI timing diagram slave mode and CPHA 0 Note added below Figure 34 SPI timing diagram slave mode and CPHA 11 Details on unused pins removed from General inputoutput characteristics on page 62 Table 42 SPI characteristics updated Table 43 USB startup time added VAIN tlat and tlatr modified note added and Ilkg removed in Table 46 ADC characteristics Test conditions modified and note added in Table 49 ADC accuracy Note added below Table 47 and Table 50 Inch values corrected in Table 55 LQPF100 14 x 14 mm 100pin low profile quad flat package mechanical data Table 58 LQFP64 64pin 10 x 10 mm lowprofile quad flat package mechanical data and Table 60 LQFP48 7 x 7 mm 48pin lowprofile quad flat package mechanical data ΘJAvalue for VFQFPN36 package added in Table 62 Package thermal characteristics Order codes replaced by Section 7 Ordering information scheme MCU s operating conditions modified in Typical current consumption on page 47 AvgSlope and V25 modified in Table 50 TS characteristics I2C interface characteristics on page 69 modified Impedance specified in A4 Voltage glitch on ADC input 0 on page 81 Table 64 Document revision history continued Date Revision Changes Revision history STM32F103x8 STM32F103xB 112117 DocID13587 Rev 17 14Mar2008 5 Figure 2 Clock tree on page 12 added Maximum TJ value given in Table 8 Thermal characteristics on page 38 CRC feature added see CRC cyclic redundancy check calculation unit on page 9 and Figure 11 Memory map on page 34 for address IDD modified in Table 16 Typical and maximum current consumptions in Stop and Standby modes ACCHSI modified in Table 24 HSI oscillator characteristics on page 56 note 2 removed PD TA and TJ added tprog values modified and tprog description clarified in Table 28 Flash memory characteristics on page 57 tRET modified in Table VNFNRST unit corrected in Table 38 NRST pin characteristics on page 67 Table 42 SPI characteristics on page 71 modified IVREF added to Table 46 ADC characteristics on page 75 Table 48 ADC accuracy limited test conditions added Table 49 ADC accuracy modified LQFP100 package specifications updated see Section 6 Package information on page 80 Recommended LQFP100 LQFP 64 LQFP48 and VFQFPN36 footprints added see Figure 55 Figure 60 Figure 64 and Figure 44 Section 69 Thermal characteristics on page 105 modified Section 691 and Section 692 added Appendix A Important notes on page 81 removed 21Mar2008 6 Small text changes Figure 11 Memory map clarified In Table NEND tested over the whole temperature range cycling conditions specified for tRET tRET min modified at TA 55 C V25 AvgSlope and TL modified in Table 50 TS characteristics CRC feature removed 22May2008 7 CRC feature added back Small text changes Section 1 Introduction modified Section 22 Full compatibility throughout the family added IDD at TA max 105 C added to Table 16 Typical and maximum current consumptions in Stop and Standby modes on page 45 IDDVBAT removed from Table 21 Typical current consumption in Standby mode on page 47 Values added to Table 41 SCL frequency fPCLK1 36 MHzVDDI2C 33 V on page 70 Figure 33 SPI timing diagram slave mode and CPHA 0 on page 72 modified Equation 1 corrected tRET at TA 105 C modified in Table on page 58 VUSB added to Table 44 USB DC electrical characteristics on page 74 Figure 65 LQFP100 PD max vs TA on page 107 modified Axx option added to Table 63 Ordering information scheme on page 108 Table 64 Document revision history continued Date Revision Changes DocID13587 Rev 17 113117 STM32F103x8 STM32F103xB Revision history 116 21Jul2008 8 Power supply supervisor updated and VDDA added to Table 9 General operating conditions Capacitance modified in Figure 14 Power supply scheme on page 36 Table notes revised in Section 5 Electrical characteristics Table 16 Typical and maximum current consumptions in Stop and Standby modes modified Data added to Table 16 Typical and maximum current consumptions in Stop and Standby modes and Table 21 Typical current consumption in Standby mode removed fHSEext modified in Table 20 Highspeed external user clock characteristics on page 51 fPLLIN modified in Table 27 PLL characteristics on page 57 Minimum SDA and SCL fall time value for Fast mode removed from Table 40 I2C characteristics on page 69 note 1 modified thNSS modified in Table 42 SPI characteristics on page 71 and Figure 33 SPI timing diagram slave mode and CPHA 0 on page 72 CADC modified in Table 46 ADC characteristics on page 75 and Figure 38 Typical connection diagram using the ADC modified Typical TStemp value removed from Table 50 TS characteristics on page 79 LQFP48 package specifications updated see Table 60 and Table 64 Section 6 Package information revised Axx option removed from Table 63 Ordering information scheme on page 108 Small text changes 22Sep2008 9 STM32F103x6 part numbers removed see Table 63 Ordering information scheme Small text changes Generalpurpose timers TIMx and Advancedcontrol timer TIM1 on page 18 updated Notes updated in Table 5 Mediumdensity STM32F103xx pin definitions on page 28 Note 2 modified below Table 6 Voltage characteristics on page 37 ΔVDDx min and ΔVDDx min removed Measurement conditions specified in Section 535 Supply current characteristics on page 41 IDD in standby mode at 85 C modified in Table 16 Typical and maximum current consumptions in Stop and Standby modes on page 45 General inputoutput characteristics on page 62 modified fHCLK conditions modified in Table 30 EMS characteristics on page 59 ΘJA and pitch value modified for LFBGA100 package in Table 62 Package thermal characteristics Small text changes Table 64 Document revision history continued Date Revision Changes Revision history STM32F103x8 STM32F103xB 114117 DocID13587 Rev 17 23Apr2009 10 IO information clarified on page 1 Figure 3 STM32F103xx performance line LFBGA100 ballout modified Figure 11 Memory map modified Table 4 Timer feature comparison added PB4 PB13 PB14 PB15 PB3TRACESWO moved from Default column to Remap column in Table 5 Mediumdensity STM32F103xx pin definitions PD for LFBGA100 corrected in Table 9 General operating conditions Note modified in Table 13 Maximum current consumption in Run mode code with data processing running from Flash and Table 15 Maximum current consumption in Sleep mode code running from Flash or RAM Table 20 Highspeed external user clock characteristics and Table 21 Lowspeed external user clock characteristics modified Figure 20 shows a typical curve title modified ACCHSI max values modified in Table 24 HSI oscillator characteristics TFBGA64 package added see Table 59 and Table 60 Small text changes 22Sep2009 11 Note 5 updated and Note 4 added in Table 5 Mediumdensity STM32F103xx pin definitions VRERINT and TCoeff added to Table 12 Embedded internal reference voltage IDDVBAT value added to Table 16 Typical and maximum current consumptions in Stop and Standby modes Figure 18 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added fHSEext min modified in Table 20 Highspeed external user clock characteristics CL1 and CL2 replaced by C in Table 22 HSE 416 MHz oscillator characteristics and Table 23 LSE oscillator characteristics fLSE 32768 kHz notes modified and moved below the tables Table 24 HSI oscillator characteristics modified Conditions removed from Table 26 Lowpower mode wakeup timings Note 1 modified below Figure 24 Typical application with an 8 MHz crystal IEC 1000 standard updated to IEC 61000 and SAE J17523 updated to IEC 619672 in Section 5310 EMC characteristics on page 58 Jitter added to Table 27 PLL characteristics Table 42 SPI characteristics modified CADC and RAIN parameters modified in Table 46 ADC characteristics RAIN max values modified in Table 47 RAIN max for fADC 14 MHz Figure 47 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x10 mm 08 mm pitch package outline updated 03Jun2010 12 Added STM32F103TB devices Added VFQFPN48 package Updated note 2 below Table 40 I2C characteristics Updated Figure 32 I2C bus AC waveforms and measurement circuit Updated Figure 31 Recommended NRST pin protection Updated Section 5312 IO current injection characteristics Table 64 Document revision history continued Date Revision Changes DocID13587 Rev 17 115117 STM32F103x8 STM32F103xB Revision history 116 19Apr2011 13 Updated footnotes below Table 6 Voltage characteristics on page 37 and Table 7 Current characteristics on page 37 Updated tw min in Table 20 Highspeed external user clock characteristics on page 51 Updated startup time in Table 23 LSE oscillator characteristics fLSE 32768 kHz on page 54 Added Section 5312 IO current injection characteristics Updated Section 5313 IO port characteristics 07Dec2012 14 Added UFBGA100 7 x 7 mm Updated Figure 59 LQFP64 10 x 10 mm 64pin lowprofile quad flat package outline to add pin 1 identification 14May2013 15 Replaced VQFN48 package with UQFN48 in cover page packages Table 2 STM32F103xx mediumdensity device features and peripheral counts Figure 9 STM32F103xx performance line UFQFPN48 pinout Table 2 STM32F103xx mediumdensity device features and peripheral counts Table 56 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package mechanical data Table 63 Ordering information scheme and updated Table 62 Package thermal characteristics Added footnote for TFBGA ADC channels in Table 2 STM32F103xx mediumdensity device features and peripheral counts Updated All GPIOs are high current in Section 2321 GPIOs generalpurpose inputsoutputs Updated Table 5 Mediumdensity STM32F103xx pin definitions Corrected Sigma letter in Section 511 Minimum and maximum values Removed the first sentence in Section 5316 Communications interfaces Added VIN in Table 9 General operating conditions Updated first sentence in Output driving current Added note 5 in Table 24 HSI oscillator characteristics Updated VIL and VIH in Table 35 IO static characteristics Added notes to Figure 26 Standard IO input characteristics CMOS port Figure 27 Standard IO input characteristics TTL port Figure 28 5 V tolerant IO input characteristics CMOS port and Figure 29 5 V tolerant IO input characteristics TTL port Updated Figure 32 I2C bus AC waveforms and measurement circuit Updated note 2 and 3removed note the device must internally in Table 40 I2C characteristics Updated title of Table 41 SCL frequency fPCLK1 36 MHzVDDI2C 33 V Updated note 2 in Table 49 ADC accuracy Table 64 Document revision history continued Date Revision Changes Revision history STM32F103x8 STM32F103xB 116117 DocID13587 Rev 17 14May2013 15 continued Updated Figure 53 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package outline and Table 56 UFBGA100 100ball 7 x 7 mm 050 mm pitch ultra fine pitch ball grid array package mechanical data Updated Figure 47 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x10 mm 08 mm pitch package outline and Table 53 LFBGA100 100ball lowprofile fine pitch ball grid array 10 x 10 mm 08 mm pitch package mechanical data Updated Figure 60 TFBGA64 8 x 8 active ball array 5 x 5 mm 05 mm pitch package outline and Table 59 TFBGA64 8 x 8 active ball array 5 x 5 mm 05 mm pitch package mechanical data 05Aug2013 16 Updated the reference for VESDCDM in Table 32 ESD absolute maximum ratings Corrected tfIOout in Figure 30 IO AC characteristics definition Updated Table 52 UFQFPN48 48lead 7x7 mm 05 mm pitch ultra thin fine pitch quad flat package mechanical data 21Aug2015 17 Updated Table 3 STM32F103xx family removing the note Updated Table 63 Ordering information scheme removing the note Updated Section 6 Package information and added Section Marking of engineering samples for all packages Updated I2C characteristics added tSP parameter and note 4 in Table 40 I2C characteristics Updated Figure 32 I2C bus AC waveforms and measurement circuit swapping SCLL and SCLH Updated Figure 33 SPI timing diagram slave mode and CPHA 0 Updated minmax value notes replacing Guaranteed by design not tested in production by guaranteed by design Updated minmax value notes replacing based on characterization not tested in production by Guaranteed based on test during characterization Updated Table 19 Peripheral current consumption Table 64 Document revision history continued Date Revision Changes DocID13587 Rev 17 117117 STM32F103x8 STM32F103xB 117 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products andor to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to STs terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved