ARM and Thumb2 Instruction Set Quick Reference

ARM and Thumb2 Instruction Set Quick Reference Card Key to Tables Rm opsh See Table Register optionally shifted by constant Operand2 See Table Flexible Operand 2 Shift and rotate are only available as part of Operand2 reglist A commaseparated list of registers enclosed in braces and fields See Table PSR fields reglistPC As reglist must not include the PC PSR Either CPSR Current Processor Status Register or SPSR Saved Processor Status Register reglistPC As reglist including the PC C V Flag is unpredictable in Architecture v4 and earlier unchanged in Architecture v5 and later or may be omitted Rssh Can be Rs or an immediate shift value The values allowed for each shift type are the same as those See Table ARM architecture versions shown in Table Register optionally shifted by constant iflags Interrupt flags One or more of a i f abort interrupt fast interrupt xy B meaning halfregister 150 or T meaning 3116 pmode See Table Processor Modes imm8m ARM a 32bit constant formed by rightrotating an 8bit value by an even number of bits SPm SP for the processor mode specified by pmode Thumb a 32bit constant formed by leftshifting an 8bit value by any number of bits or a bit lsb Least significant bit of bitfield pattern of one of the forms 0xXYXYXYXY 0x00XY00XY or 0xXY00XY00 width Width of bitfield width lsb must be 32 prefix See Table Prefixes for Parallel instructions X RsX is Rs rotated 16 bits if X present Otherwise RsX is Rs IAIBDADB Increment After Increment Before Decrement After or Decrement Before Updates base register after data transfer if present preindexed IB and DA are not available in Thumb state If omitted defaults to IA S Updates condition flags if S present size B SB H or SH meaning Byte Signed Byte Halfword and Signed Halfword respectively T User mode privilege if T present SB and SH are not available in STR instructions R Rounds result to nearest if R present otherwise truncates result Operation Assembler S updates Action Notes Add Add ADDS Rd Rn Operand2 N Z C V Rd Rn Operand2 N with carry ADCS Rd Rn Operand2 N Z C V Rd Rn Operand2 Carry N wide T2 ADD Rd Rn imm12 Rd Rn imm12 imm12 range 04095 T P saturating doubled 5E QDADD Rd Rm Rn Rd SATRm Rn doubled Rd SATRm SATRn 2 Q Address Form PCrelative address ADR Rd label Rd label for label range from current instruction see Note L N L Subtract Subtract SUBS Rd Rn Operand2 N Z C V Rd Rn Operand2 N with carry SBCS Rd Rn Operand2 N Z C V Rd Rn Operand2 NOTCarry N wide T2 SUB Rd Rn imm12 N Z C V Rd Rn imm12 imm12 range 04095 T P reverse subtract RSBS Rd Rn Operand2 N Z C V Rd Operand2 Rn N reverse subtract with carry RSCS Rd Rn Operand2 N Z C V Rd Operand2 Rn NOTCarry A saturating doubled 5E QDSUB Rd Rm Rn Rd SATRm Rn doubled Rd SATRm SATRn 2 Q Exception return without stack SUBS PC LR imm8 PC LR imm8 CPSR SPSRcurrent mode imm8 range 0255 T Parallel arithmetic Halfwordwise addition 6 prefixADD16 Rd Rn Rm Rd3116 Rn3116 Rm3116 Rd150 Rn150 Rm150 G Halfwordwise subtraction 6 prefixSUB16 Rd Rn Rm Rd3116 Rn3116 Rm3116 Rd150 Rn150 Rm150 G Bytewise addition 6 prefixADD8 Rd Rn Rm Rd3124 Rn3124 Rm3124 Rd2316 Rn2316 Rm2316 Rd158 Rn158 Rm158 Rd70 Rn70 Rm70 G Bytewise subtraction 6 prefixSUB8 Rd Rn Rm Rd3124 Rn3124 Rm3124 Rd2316 Rn2316 Rm2316 Rd158 Rn158 Rm158 Rd70 Rn70 Rm70 G Halfwordwise exchange add subtract 6 prefixASX Rd Rn Rm Rd3116 Rn3116 Rm150 Rd150 Rn150 Rm3116 G Halfwordwise exchange subtract add 6 prefixSAX Rd Rn Rm Rd3116 Rn3116 Rm150 Rd150 Rn150 Rm3116 G Unsigned sum of absolute differences 6 USAD8 Rd Rm Rs Rd AbsRm3124 Rs3124 AbsRm2316 Rs2316 AbsRm158 Rs158 AbsRm70 Rs70 and accumulate 6 USADA8 Rd Rm Rs Rn Rd Rn AbsRm3124 Rs3124 AbsRm2316 Rs2316 AbsRm158 Rs158 AbsRm70 Rs70 Saturate Signed saturate word right shift 6 SSAT Rd sat Rm ASR sh Rd SignedSatRm ASR sh sat sat range 132 sh range 131 Q R Signed saturate word left shift 6 SSAT Rd sat Rm LSL sh Rd SignedSatRm LSL sh sat sat range 132 sh range 031 Q Signed saturate two halfwords 6 SSAT16 Rd sat Rm Rd3116 SignedSatRm3116 sat Rd150 SignedSatRm150 sat sat range 116 Q Unsigned saturate word right shift 6 USAT Rd sat Rm ASR sh Rd UnsignedSatRm ASR sh sat sat range 031 sh range 131 Q R Unsigned saturate word left shift 6 USAT Rd sat Rm LSL sh Rd UnsignedSatRm LSL sh sat sat range 031 sh range 031 Q Unsigned saturate two halfwords 6 USAT16 Rd sat Rm Rd3116 UnsignedSatRm3116 sat Rd150 UnsignedSatRm150 sat sat range 015 Q ARM and Thumb2 Instruction Set Quick Reference Card Operation Assembler S updates Action Notes Multiply Multiply MULS Rd Rm Rs N Z C Rd Rm Rs310 If Rm is Rd S can be used in Thumb2 N S and accumulate MLAS Rd Rm Rs Rn N Z C Rd Rn Rm Rs310 S and subtract T2 MLS Rd Rm Rs Rn Rd Rn Rm Rs310 unsigned long UMULLS RdLo RdHi Rm Rs N Z C V RdHiRdLo unsignedRm Rs S unsigned accumulate long UMLALS RdLo RdHi Rm Rs N Z C V RdHiRdLo unsignedRdHiRdLo Rm Rs S unsigned double accumulate long 6 UMAAL RdLo RdHi Rm Rs RdHiRdLo unsignedRdHi RdLo Rm Rs Signed multiply long SMULLS RdLo RdHi Rm Rs N Z C V RdHiRdLo signedRm Rs S and accumulate long SMLALS RdLo RdHi Rm Rs N Z C V RdHiRdLo signedRdHiRdLo Rm Rs S 16 16 bit 5E SMULxy Rd Rm Rs Rd Rmx Rsy 32 16 bit 5E SMULWy Rd Rm Rs Rd Rm Rsy4716 16 16 bit and accumulate 5E SMLAxy Rd Rm Rs Rn Rd Rn Rmx Rsy Q 32 16 bit and accumulate 5E SMLAWy Rd Rm Rs Rn Rd Rn Rm Rsy4716 Q 16 16 bit and accumulate long 5E SMLALxy RdLo RdHi Rm Rs RdHiRdLo RdHiRdLo Rmx Rsy Dual signed multiply add 6 SMUADX Rd Rm Rs Rd Rm150 RsX150 Rm3116 RsX3116 Q and accumulate 6 SMLADX Rd Rm Rs Rn Rd Rn Rm150 RsX150 Rm3116 RsX3116 Q and accumulate long 6 SMLALDX RdLo RdHi Rm Rs RdHiRdLo RdHiRdLo Rm150 RsX150 Rm3116 RsX3116 Dual signed multiply subtract 6 SMUSDX Rd Rm Rs Rd Rm150 RsX150 Rm3116 RsX3116 Q and accumulate 6 SMLSDX Rd Rm Rs Rn Rd Rn Rm150 RsX150 Rm3116 RsX3116 Q and accumulate long 6 SMLSLDX RdLo RdHi Rm Rs RdHiRdLo RdHiRdLo Rm150 RsX150 Rm3116 RsX3116 Signed top word multiply 6 SMMULR Rd Rm Rs Rd Rm Rs6332 and accumulate 6 SMMLAR Rd Rm Rs Rn Rd Rn Rm Rs6332 and subtract 6 SMMLSR Rd Rm Rs Rn Rd Rn Rm Rs6332 with internal 40bit accumulate XS MIA Ac Rm Rs Ac Ac Rm Rs packed halfword XS MIAPH Ac Rm Rs Ac Ac Rm150 Rs150 Rm3116 Rs3116 halfword XS MIAxy Ac Rm Rs Ac Ac Rmx Rsy Divide Signed or Unsigned RM op Rd Rn Rm Rd Rn Rm op is SDIV signed or UDIV unsigned Move data Move MOVS Rd Operand2 N Z C Rd Operand2 See also Shift instructions N NOT MVNS Rd Operand2 N Z C Rd 0xFFFFFFFF EOR Operand2 N top T2 MOVT Rd imm16 Rd3116 imm16 Rd150 unaffected imm16 range 065535 wide T2 MOV Rd imm16 Rd150 imm16 Rd3116 0 imm16 range 065535 40bit accumulator to register XS MRA RdLo RdHi Ac RdLo Ac310 RdHi Ac3932 register to 40bit accumulator XS MAR Ac RdLo RdHi Ac310 RdLo Ac3932 RdHi Shift Arithmetic shift right ASRS Rd Rm Rssh N Z C Rd ASRRm Rssh Same as MOVS Rd Rm ASR Rssh N Logical shift left LSLS Rd Rm Rssh N Z C Rd LSLRm Rssh Same as MOVS Rd Rm LSL Rssh N Logical shift right LSRS Rd Rm Rssh N Z C Rd LSRRm Rssh Same as MOVS Rd Rm LSR Rssh N Rotate right RORS Rd Rm Rssh N Z C Rd RORRm Rssh Same as MOVS Rd Rm ROR Rssh N Rotate right with extend RRXS Rd Rm N Z C Rd RRXRm Same as MOVS Rd Rm RRX Count leading zeros 5 CLZ Rd Rm Rd number of leading zeros in Rm Compare Compare CMP Rn Operand2 N Z C V Update CPSR flags on Rn Operand2 N negative CMN Rn Operand2 N Z C V Update CPSR flags on Rn Operand2 N Logical Test TST Rn Operand2 N Z C Update CPSR flags on Rn AND Operand2 N Test equivalence TEQ Rn Operand2 N Z C Update CPSR flags on Rn EOR Operand2 AND ANDS Rd Rn Operand2 N Z C Rd Rn AND Operand2 N EOR EORS Rd Rn Operand2 N Z C Rd Rn EOR Operand2 N ORR ORRS Rd Rn Operand2 N Z C Rd Rn OR Operand2 N ORN T2 ORNS Rd Rn Operand2 N Z C Rd Rn OR NOT Operand2 T Bit Clear BICS Rd Rn Operand2 N Z C Rd Rn AND NOT Operand2 N ARM and Thumb2 Instruction Set Quick Reference Card Operation Assembler Action Notes Bit field Bit Field Clear T2 BFC Rd lsb width Rdwidthlsb1lsb 0 other bits of Rd unaffected Bit Field Insert T2 BFI Rd Rn lsb width Rdwidthlsb1lsb Rnwidth10 other bits of Rd unaffected Signed Bit Field Extract T2 SBFX Rd Rn lsb width Rdwidth10 Rnwidthlsb1lsb Rd31width Replicate Rnwidthlsb1 Unsigned Bit Field Extract T2 UBFX Rd Rn lsb width Rdwidth10 Rnwidthlsb1lsb Rd31width Replicate 0 Pack Pack halfword bottom top 6 PKHBT Rd Rn Rm LSL sh Rd150 Rn150 Rd3116 Rm LSL sh3116 sh 031 Pack halfword top bottom 6 PKHTB Rd Rn Rm ASR sh Rd3116 Rn3116 Rd150 Rm ASR sh150 sh 132 Signed extend Halfword to word 6 SXTH Rd Rm ROR sh Rd310 SignExtendRm ROR 8 sh150 sh 03 N Two bytes to halfwords 6 SXTB16 Rd Rm ROR sh Rd3116 SignExtendRm ROR 8 sh2316 Rd150 SignExtendRm ROR 8 sh70 sh 03 Byte to word 6 SXTB Rd Rm ROR sh Rd310 SignExtendRm ROR 8 sh70 sh 03 N Unsigned extend Halfword to word 6 UXTH Rd Rm ROR sh Rd310 ZeroExtendRm ROR 8 sh150 sh 03 N Two bytes to halfwords 6 UXTB16 Rd Rm ROR sh Rd3116 ZeroExtendRm ROR 8 sh2316 Rd150 ZeroExtendRm ROR 8 sh70 sh 03 Byte to word 6 UXTB Rd Rm ROR sh Rd310 ZeroExtendRm ROR 8 sh70 sh 03 N Signed extend with add Halfword to word add 6 SXTAH Rd Rn Rm ROR sh Rd310 Rn310 SignExtendRm ROR 8 sh150 sh 03 Two bytes to halfwords add 6 SXTAB16 Rd Rn Rm ROR sh Rd3116 Rn3116 SignExtendRm ROR 8 sh2316 Rd150 Rn150 SignExtendRm ROR 8 sh70 sh 03 Byte to word add 6 SXTAB Rd Rn Rm ROR sh Rd310 Rn310 SignExtendRm ROR 8 sh70 sh 03 Unsigned extend with add Halfword to word add 6 UXTAH Rd Rn Rm ROR sh Rd310 Rn310 ZeroExtendRm ROR 8 sh150 sh 03 Two bytes to halfwords add 6 UXTAB16 Rd Rn Rm ROR sh Rd3116 Rn3116 ZeroExtendRm ROR 8 sh2316 Rd150 Rn150 ZeroExtendRm ROR 8 sh70 sh 03 Byte to word add 6 UXTAB Rd Rn Rm ROR sh Rd310 Rn310 ZeroExtendRm ROR 8 sh70 sh 03 Reverse Bits in word T2 RBIT Rd Rm For i 0 i 32 i Rdi Rm31 i Bytes in word 6 REV Rd Rm Rd3124 Rm70 Rd2316 Rm158 Rd158 Rm2316 Rd70 Rm3124 N Bytes in both halfwords 6 REV16 Rd Rm Rd158 Rm70 Rd70 Rm158 Rd3124 Rm2316 Rd2316 Rm3124 N Bytes in low halfword sign extend 6 REVSH Rd Rm Rd158 Rm70 Rd70 Rm158 Rd3116 Rm7 FFFF N Select Select bytes 6 SEL Rd Rn Rm Rd70 Rn70 if GE0 1 else Rd70 Rm70 Bits158 2316 3124 selected similarly by GE1 GE2 GE3 IfThen IfThen T2 ITpattern cond Makes up to four following instructions conditional according to pattern pattern is a string of up to three letters Each letter can be T Then or E Else The first instruction after IT has condition cond The following instructions have condition cond if the corresponding letter is T or the inverse of cond if the corresponding letter is E See Table Condition Field for available condition codes T U Branch Branch B label PC label label is this instruction 32MB T2 16MB T 252 256B N B with link BL label LR address of next instruction PC label label is this instruction 32MB T2 16MB and exchange 4T BX Rm PC Rm Target is Thumb if Rm0 is 1 ARM if Rm0 is 0 N with link and exchange 1 5T BLX label LR address of next instruction PC label Change instruction set label is this instruction 32MB T2 16MB C with link and exchange 2 5 BLX Rm LR address of next instruction PC Rm311 Change to Thumb if Rm0 is 1 to ARM if Rm0 is 0 N and change to Jazelle state 5J BXJ Rm Change to Jazelle state if available Compare branch if non zero T2 CBNZ Rnlabel If Rn or 0 then PC label label is this instruction 4130 N T U Table Branch Byte T2 TBB Rn Rm PC PC ZeroExtend Memory Rn Rm 1 1 Branch range 4512 Rn can be PC T U Table Branch Halfword T2 TBH Rn Rm LSL 1 PC PC ZeroExtend Memory Rn Rm 1 2 1 Branch range 4131072 Rn can be PC T U Move to or from PSR PSR to register MRS Rd PSR Rd PSR register to PSR MSR PSRfields Rm PSR Rm selected bytes only immediate to PSR MSR PSRfields imm8m PSR immed8r selected bytes only Processor state change Change processor state 6 CPSID iflags pmode Disable specified interrupts optional change mode U N 6 CPSIE iflags pmode Enable specified interrupts optional change mode U N Change processor mode 6 CPS pmode U Set endianness 6 SETEND endianness Sets endianness for loads and saves endianness can be BE Big Endian or LE Little Endian U N ARM Instruction Set Quick Reference Card Single data item loads and stores Assembler Action if op is LDR Action if op is STR Notes Load or store word byte or halfword Immediate offset opsizeT Rd Rn offset Rd address size address size Rd 1 N Postindexed immediate opsizeT Rd Rn offset Rd address size address size Rd 2 Register offset opsize Rd Rn Rm opsh Rd address size address size Rd 3 N Postindexed register opsizeT Rd Rn Rm opsh Rd address size address size Rd 4 PCrelative opsize Rd label Rd label size Not available 5 N Load or store doubleword Immediate offset 5E opD Rd1 Rd2 Rn offset Rd1 address Rd2 address 4 address Rd1 address 4 Rd2 6 9 Postindexed immediate 5E opD Rd1 Rd2 Rn offset Rd1 address Rd2 address 4 address Rd1 address 4 Rd2 6 9 Register offset 5E opD Rd1 Rd2 Rn Rm opsh Rd1 address Rd2 address 4 address Rd1 address 4 Rd2 7 9 Postindexed register 5E opD Rd1 Rd2 Rn Rm opsh Rd1 address Rd2 address 4 address Rd1 address 4 Rd2 7 9 PCrelative 5E opD Rd1 Rd2 label Rd1 label Rd2 label 4 Not available 8 9 Preload data or instruction PLD PLI Assembler Action if op is PLD Action if op is PLI Notes Immediate offset 5E 7 op Rn offset Preload address 32 data Preload address 32 instruction 1 C Register offset 5E 7 op Rn Rm opsh Preload address 32 data Preload address 32 instruction 3 C PCrelative 5E 7 op label Preload label 32 data Preload label 32 instruction 5 C Other memory operations Assembler Action Notes Load multiple Block data load LDMIAIBDADB Rn reglistPC Load list of registers from Rn N I return and exchange LDMIAIBDADB Rn reglistPC Load registers PC address311 5T Change to Thumb if address0 is 1 I and restore CPSR LDMIAIBDADB Rn reglistPC Load registers branch 5T and exchange CPSR SPSR Exception modes only I User mode registers LDMIAIBDADB Rn reglistPC Load list of User mode registers from Rn Privileged modes only I Pop POP reglist Canonical form of LDM SP reglist N Load exclusive Semaphore operation 6 LDREX Rd Rn Rd Rn tag address as exclusive access Outstanding tag set if not shared address Rd Rn not PC Halfword or Byte 6K LDREXHB Rd Rn Rd150 Rn or Rd70 Rn tag address as exclusive access Outstanding tag set if not shared address Rd Rn not PC Doubleword 6K LDREXD Rd1 Rd2 Rn Rd1 Rn Rd2 Rn4 tag addresses as exclusive access Outstanding tags set if not shared addresses Rd1 Rd2 Rn not PC 9 Store multiple Push or Block data store STMIAIBDADB Rn reglist Store list of registers to Rn N I User mode registers STMIAIBDADB Rn reglist Store list of User mode registers to Rn Privileged modes only I Push PUSH reglist Canonical form of STMDB SP reglist N Store exclusive Semaphore operation 6 STREX Rd Rm Rn If allowed Rn Rm clear exclusive tag Rd 0 Else Rd 1 Rd Rm Rn not PC Halfword or Byte 6K STREXHB Rd Rm Rn If allowed Rn Rm150 or Rn Rm70 clear exclusive tag Rd 0 Else Rd 1 Rd Rm Rn not PC Doubleword 6K STREXD Rd Rm1 Rm2 Rn If allowed Rn Rm1 Rn4 Rm2 clear exclusive tags Rd 0 Else Rd 1 Rd Rm1 Rm2 Rn not PC 9 Clear exclusive 6K CLREX Clear local processor exclusive tag C Notes availability and range of options for Load Store and Preload operations Note ARM Word B D ARM SB H SH ARM T BT Thumb2 Word B SB H SH D Thumb2 T BT SBT HT SHT 1 offset 4095 to 4095 offset 255 to 255 Not available offset 255 to 255 if writeback 255 to 4095 otherwise offset 0 to 255 writeback not allowed 2 offset 4095 to 4095 offset 255 to 255 offset 4095 to 4095 offset 255 to 255 Not available 3 Full range of opsh opsh not allowed Not available opsh restricted to LSL sh sh range 0 to 3 Not available 4 Full range of opsh opsh not allowed Full range of opsh Not available Not available 5 label within 4092 of current instruction Not available Not available label within 4092 of current instruction Not available 6 offset 255 to 255 offset 1020 to 1020 must be multiple of 4 7 opsh not allowed Not available 8 label within 252 of current instruction Not available 9 Rd1 even and not r14 Rd2 Rd1 1 Rd1 PC Rd2 PC ARM Instruction Set Quick Reference Card Coprocessor operations Assembler Action Notes Data operations CDP2 copr op1 CRd CRn CRm op2 Coprocessor defined C2 Move to ARM register from coprocessor MRC2 copr op1 Rd CRn CRm op2 Coprocessor defined C2 Two ARM register move 5E MRRC copr op1 Rd Rn CRm Coprocessor defined Alternative two ARM register move 6 MRRC2 copr op1 Rd Rn CRm Coprocessor defined C Move to coproc from ARM reg MCR2 copr op1 Rd CRn CRm op2 Coprocessor defined C2 Two ARM register move 5E MCRR copr op1 Rd Rn CRm Coprocessor defined Alternative two ARM register move 6 MCRR2 copr op1 Rd Rn CRm Coprocessor defined C Loads and stores preindexed op2 copr CRd Rn offset84 op LDC or STC offset multiple of 4 in range 0 to 1020 Coprocessor defined C2 Loads and stores zero offset op2 copr CRd Rn 8bit copro option op LDC or STC Coprocessor defined C2 Loads and stores postindexed op2 copr CRd Rn offset84 op LDC or STC offset multiple of 4 in range 0 to 1020 Coprocessor defined C2 Miscellaneous operations Assembler Action Notes Swap word SWP Rd Rm Rn temp Rn Rn Rm Rd temp D Swap byte SWPB Rd Rm Rn temp ZeroExtendRn70 Rn70 Rm70 Rd temp D Store return state 6 SRSIAIBDADB SP pmode SPm LR SPm 4 CPSR C I Return from exception 6 RFEIAIBDADB Rn PC Rn CPSR Rn 4 C I Breakpoint 5 BKPT imm16 Prefetch abort or enter debug state 16bit bitfield encoded in instruction C N Secure Monitor Call Z SMC imm16 Secure Monitor Call exception 16bit bitfield encoded in instruction Formerly SMI Supervisor Call SVC imm24 Supervisor Call exception 24bit bitfield encoded in instruction Formerly SWI N No operation 6 NOP None might not even consume any time N Hints Debug Hint 7 DBG Provide hint to debug and related systems Data Memory Barrier 7 DMB Ensure the order of observation of memory accesses C Data Synchronization Barrier 7 DSB Ensure the completion of memory accesses C Instruction Synchronization Barrier 7 ISB Flush processor pipeline and branch prediction logic C Set event T2 SEV Signal event in multiprocessor system NOP if not implemented N Wait for event T2 WFE Wait for event IRQ FIQ Imprecise abort or Debug entry request NOP if not implemented N Wait for interrupt T2 WFI Wait for IRQ FIQ Imprecise abort or Debug entry request NOP if not implemented N Yield T2 YIELD Yield control to alternative thread NOP if not implemented N Notes A Not available in Thumb state N Some or all forms of this instruction are 16bit Narrow instructions in Thumb2 code For details see the Thumb 16bit Instruction Set UAL Quick Reference Card B Can be conditional in Thumb state without having to be in an IT block C Condition codes are not allowed in ARM state P Rn can be the PC in Thumb state in this instruction C2 The optional 2 is available from ARMv5 It provides an alternative operation Condition codes are not allowed for the alternative form in ARM state Q Sets the Q flag if saturation addition or substraction or overflow multiplication occurs Read and reset the Q flag using MRS and MSR D Deprecated Use LDREX and STREX instead R sh range is 132 in the ARM instruction G Updates the four GE flags in the CPSR based on the results of the individual operations S The S modifier is not available in the Thumb2 instruction I IA is the default and is normally omitted T Not available in ARM state L ARM imm8m 16bit Thumb multiple of 4 in range 01020 32bit Thumb 04095 U Not allowed in an IT block Condition codes not allowed in either ARM or Thumb state ARM Instruction Set Quick Reference Card ARM architecture versions Condition Field n ARM architecture version n and above Mnemonic Description Description VFP nT nJ T or J variants of ARM architecture version n and above EQ Equal Equal 5E ARM v5E and 6 and above NE Not equal Not equal or unordered T2 All Thumb2 versions of ARM v6 and above CS HS Carry Set Unsigned higher or same Greater than or equal or unordered 6K ARMv6K and above for ARM instructions ARMv7 for Thumb CC LO Carry Clear Unsigned lower Less than Z All Security extension versions of ARMv6 and above MI Negative Less than RM ARMv7R and ARMv7M only PL Positive or zero Greater than or equal or unordered XS XScale coprocessor instruction VS Overflow Unordered at least one NaN operand VC No overflow Not unordered Flexible Operand 2 HI Unsigned higher Greater than or unordered Immediate value imm8m LS Unsigned lower or same Less than or equal Register optionally shifted by constant see below Rm opsh GE Signed greater than or equal Greater than or equal Register logical shift left by register Rm LSL Rs LT Signed less than Less than or unordered Register logical shift right by register Rm LSR Rs GT Signed greater than Greater than Register arithmetic shift right by register Rm ASR Rs LE Signed less than or equal Less than or equal or unordered Register rotate right by register Rm ROR Rs AL Always normally omitted Always normally omitted All ARM instructions except those with Note C or Note U can have any one of these condition codes after the instruction mnemonic that is before the first space in the instruction as shown on this card This condition is encoded in the instruction All Thumb2 instructions except those with Note U can have any one of these condition codes after the instruction mnemonic This condition is encoded in a preceding IT instruction except in the case of conditional Branch instructions Condition codes in instructions must match those in the preceding IT instruction On processors without Thumb2 the only Thumb instruction that can have a condition code is B label Register optionally shifted by constant No shift Rm Same as Rm LSL 0 Logical shift left Rm LSL shift Allowed shifts 031 Logical shift right Rm LSR shift Allowed shifts 132 Arithmetic shift right Rm ASR shift Allowed shifts 132 Rotate right Rm ROR shift Allowed shifts 131 Rotate right with extend Rm RRX Processor Modes Prefixes for Parallel Instructions 16 User S Signed arithmetic modulo 28 or 216 sets CPSR GE bits PSR fields use at least one suffix 17 FIQ Fast Interrupt Q Signed saturating arithmetic Suffix Meaning 18 IRQ Interrupt SH Signed arithmetic halving results c Control field mask byte PSR70 19 Supervisor U Unsigned arithmetic modulo 28 or 216 sets CPSR GE bits f Flags field mask byte PSR3124 23 Abort UQ Unsigned saturating arithmetic s Status field mask byte PSR2316 27 Undefined UH Unsigned arithmetic halving results x Extension field mask byte PSR158 31 System Proprietary Notice Words and logos marked with or are registered trademarks or trademarks owned by ARM Limited Other brands and names mentioned herein may be the trademarks of their respective owners Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This reference card is intended only to assist the reader in the use of the product ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this reference card or any error or omission in such information or any incorrect use of the product Document Number ARM QRC 0001L Change Log Issue Date Change Issue Date Change A June 1995 First Release B Sept 1996 Second Release C Nov 1998 Third Release D Oct 1999 Fourth Release E Oct 2000 Fifth Release F Sept 2001 Sixth Release G Jan 2003 Seventh Release H Oct 2003 Eighth Release I Dec 2004 Ninth Release J May 2005 RVCT 22 SP1 K March 2006 RVCT 30 L March 2007 RVCT 31