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2008 Microchip Technology Inc DS39631E PIC18F2420252044204520 Data Sheet 284044Pin Enhanced Flash Microcontrollers with 10Bit AD and nanoWatt Technology DS39631Epage ii 2008 Microchip Technology Inc Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip devices in life support andor safety applications is entirely at the buyers risk and the buyer agrees to defend indemnify and hold harmless Microchip from any and all damages claims suits or expenses resulting from such use No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights Trademarks The Microchip name and logo the Microchip logo Accuron dsPIC KEELOQ KEELOQ logo MPLAB PIC PICmicro PICSTART rfPIC SmartShunt and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries FilterLab Linear Active Thermistor MXDEV MXLAB SEEVAL SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the USA AnalogfortheDigital Age Application Maestro CodeGuard dsPICDEM dsPICDEMnet dsPICworks dsSPEAK ECAN ECONOMONITOR FanSense InCircuit Serial Programming ICSP ICEPIC Mindi MiWi MPASM MPLAB Certified logo MPLIB MPLINK mTouch PICkit PICDEM PICDEMnet PICtail PIC32 logo PowerCal PowerInfo PowerMate PowerTool REAL ICE rfLAB Select Mode Total Endurance WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries SQTP is a service mark of Microchip Technology Incorporated in the USA All other trademarks mentioned herein are property of their respective companies 2008 Microchip Technology Incorporated Printed in the USA All Rights Reserved Printed on recycled paper Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchips Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act Microchip received ISOTS169492002 certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs KEELOQ code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchips quality system for the design and manufacture of development systems is ISO 90012000 certified 2008 Microchip Technology Inc DS39631Epage 1 PIC18F2420252044204520 Power Management Features Run CPU on Peripherals on Idle CPU off Peripherals on Sleep CPU off Peripherals off Ultra Low 50nA Input Leakage Run mode Currents Down to 11 μA Typical Idle mode Currents Down to 25 μA Typical Sleep mode Current Down to 100 nA Typical Timer1 Oscillator 900 nA 32 kHz 2V Watchdog Timer 14 μA 2V Typical TwoSpeed Oscillator Startup Flexible Oscillator Structure Four Crystal modes up to 40 MHz 4x Phase Lock Loop PLL Available for Crystal and Internal Oscillators Two External RC modes up to 4 MHz Two External Clock modes up to 40 MHz Internal Oscillator Block Fast wake from Sleep and Idle 1 μs typical 8 useselectable frequencies from 31 kHz to 8 MHz Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL Usertunable to compensate for frequency drift Secondary Oscillator using Timer1 32 kHz FailSafe Clock Monitor Allows for safe shutdown if peripheral clock stops Peripheral Highlights HighCurrent SinkSource 25 mA25 mA Three Programmable External Interrupts Four Input Change Interrupts Up to 2 CaptureComparePWM CCP modules one with AutoShutdown 28pin devices Enhanced CaptureComparePWM ECCP module 4044pin devices only One two or four PWM outputs Selectable polarity Programmable dead time Autoshutdown and autorestart Peripheral Highlights Continued Master Synchronous Serial Port MSSP module Supporting 3Wire SPI all 4 modes and I2C Master and Slave modes Enhanced Addressable USART module Supports RS485 RS232 and LINJ2602 RS232 operation using internal oscillator block no external crystal required Autowakeup on Start bit AutoBaud Detect 10Bit up to 13Channel AnalogtoDigital AD Converter module Autoacquisition capability Conversion available during Sleep Dual Analog Comparators with Input Multiplexing Programmable 16Level HighLowVoltage Detection HLVD module Supports interrupt on HighLowVoltage Detection Special Microcontroller Features C Compiler Optimized Architecture Optional extended instruction set designed to optimize reentrant code 100000 EraseWrite Cycle Enhanced Flash Program Memory Typical 1000000 EraseWrite Cycle Data EEPROM Memory Typical FlashData EEPROM Retention 100 Years Typical SelfProgrammable under Software Control Priority Levels for Interrupts 8 x 8 SingleCycle Hardware Multiplier Extended Watchdog Timer WDT Programmable period from 4 ms to 131s SingleSupply 5V InCircuit Serial Programming ICSP via Two Pins InCircuit Debug ICD via Two Pins Wide Operating Voltage Range 20V to 55V Programmable Brownout Reset BOR with Software Enable Option Device Program Memory Data Memory IO 10Bit AD ch CCP ECCP PWM MSSP EUSART Comp Timers 816Bit Flash bytes SingleWord Instructions SRAM bytes EEPROM bytes SPI Master I2C PIC18F2420 16K 8192 768 256 25 10 20 Y Y 1 2 13 PIC18F2520 32K 16384 1536 256 25 10 20 Y Y 1 2 13 PIC18F4420 16K 8192 768 256 36 13 11 Y Y 1 2 13 PIC18F4520 32K 16384 1536 256 36 13 11 Y Y 1 2 13 284044Pin Enhanced Flash Microcontrollers with 10Bit AD and nanoWatt Technology PIC18F2420252044204520 DS39631Epage 2 2008 Microchip Technology Inc Pin Diagrams PIC18F2520 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 MCLRVPPRE3 RA0AN0 RA1AN1 RA2AN2VREFCVREF RA3AN3VREF RA4T0CKIC1OUT RA5AN4SSHLVDINC2OUT VSS OSC1CLKIRA7 OSC2CLKORA6 RC0T1OSOT13CKI RC1T1OSICCP21 RC2CCP1 RC3SCKSCL RB7KBI3PGD RB6KBI2PGC RB5KBI1PGM RB4KBI0AN11 RB3AN9CCP21 RB2INT2AN8 RB1INT1AN10 RB0INT0FLT0AN12 VDD VSS RC7RXDT RC6TXCK RC5SDO RC4SDISDA 28Pin SPDIP SOIC PIC18F2420 Note 1 RB3 is the alternate pin for CCP2 multiplexing 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 27 2625 2423 28 9 PIC18F2420 RC0T1OSOT13CKI 5 4 RB7KBI3PGD RB6KBI2PGC RB5KBI1PGM RB4KBI0AN11 RB3AN9CCP21 RB2INT2AN8 RB1INT1AN10 RB0INT0FLT0AN12 VDD VSS RC7RXDT RC6TXCK RC5SDO RC4SDISDA MCLRVPPRE3 RA0AN0 RA1AN1 RA2AN2VREFCVREF RA3AN3VREF RA4T0CKIC1OUT RA5AN4SSHLVDINC2OUT VSS OSC1CLKIRA7 OSC2CLKORA6 RC1T1OSICCP21 RC2CCP1 RC3SCKSCL PIC18F2520 28Pin QFN RB7KBI3PGD RB6KBI2PGC RB5KBI1PGM RB4KBI0AN11 RB3AN9CCP21 RB2INT2AN8 RB1INT1AN10 RB0INT0FLT0AN12 VDD VSS RD7PSP7P1D RD6PSP6P1C RD5PSP5P1B RD4PSP4 RC7RXDT RC6TXCK RC5SDO RC4SDISDA RD3PSP3 RD2PSP2 MCLRVPPRE3 RA0AN0 RA1AN1 RA2AN2VREFCVREF RA3AN3VREF RA4T0CKIC1OUT RA5AN4SSHLVDINC2OUT RE0RDAN5 RE1WRAN6 RE2CSAN7 VDD VSS OSC1CLKIRA7 OSC2CLKORA6 RC0T1OSOT13CKI RC1T1OSICCP21 RC2CCP1P1A RC3SCKSCL RD0PSP0 RD1PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC18F4520 40Pin PDIP PIC18F4420 2008 Microchip Technology Inc DS39631Epage 3 PIC18F2420252044204520 Pin Diagrams Contd Note 1 RB3 is the alternate pin for CCP2 multiplexing 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 PIC18F4420 37 RA3AN3VREF RA2AN2VREFCVREF RA1AN1 RA0AN0 MCLRVPPRE3 RB3AN9CCP21 RB7KBI3PGD RB6KBI2PGC RB5KBI1PGM RB4KBI0AN11 NC RC6TXCK RC5SDO RC4SDISDA RD3PSP3 RD2PSP2 RD1PSP1 RD0PSP0 RC3SCKSCL RC2CCP1P1A RC1T1OSICCP21 RC0T1OSOT13CKI OSC2CLKORA6 OSC1CLKIRA7 VSS VSS VDD VDD RE2CSAN7 RE1WRAN6 RE0RDAN5 RA5AN4SSHLVDINC2OUT RA4T0CKIC1OUT RC7RXDT RD4PSP4 RD5PSP5P1B RD6PSP6P1C RD7PSP7P1D VSS VDD VDD RB0INT0FLT0AN12 RB1INT1AN10 RB2INT2AN8 44pin QFN PIC18F4520 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 PIC18F4420 37 RA3AN3VREF RA2AN2VREFCVREF RA1AN1 RA0AN0 MCLRVPPRE3 NC RB7KBI3PGD RB6KBI2PGC RB5KBI1PGM RB4KBI0AN11 NC RC6TXCK RC5SDO RC4SDISDA RD3PSP3 RD2PSP2 RD1PSP1 RD0PSP0 RC3SCKSCL RC2CCP1P1A RC1T1OSICCP21 NC NC RC0T1OSOT13CKI OSC2CLKORA6 OSC1CLKIRA7 VSS VDD RE2CSAN7 RE1WRAN6 RE0RDAN5 RA5AN4SSHLVDINC2OUT RA4T0CKIC1OUT RC7RXDT RD4PSP4 RD5PSP5P1B RD6PSP6P1C RD7PSP7P1D VSS VDD RB0INT0FLT0AN12 RB1INT1AN10 RB2INT2AN8 RB3AN9CCP21 44pin TQFP PIC18F4520 PIC18F2420252044204520 DS39631Epage 4 2008 Microchip Technology Inc Table of Contents 10 Device Overview 7 20 Oscillator Configurations 23 30 PowerManaged Modes 33 40 Reset 41 50 Memory Organization 53 60 Flash Program Memory 73 70 Data EEPROM Memory 83 80 8 x 8 Hardware Multiplier 89 90 Interrupts 91 100 IO Ports 105 110 Timer0 Module 123 120 Timer1 Module 127 130 Timer2 Module 133 140 Timer3 Module 135 150 CaptureComparePWM CCP Modules 139 160 Enhanced CaptureComparePWM ECCP Module 147 170 Master Synchronous Serial Port MSSP Module 161 180 Enhanced Universal Synchronous Asynchronous Receiver Transmitter EUSART 201 190 10Bit AnalogtoDigital Converter AD Module 223 200 Comparator Module 233 210 Comparator Voltage Reference Module 239 220 HighLowVoltage Detect HLVD 243 230 Special Features of the CPU 249 240 Instruction Set Summary 267 250 Development Support 317 260 Electrical Characteristics 321 270 DC and AC Characteristics Graphs and Tables 361 280 Packaging Information 383 Appendix A Revision History 395 Appendix B Device Differences 395 Appendix C Migration from MidRange to Enhanced Devices 396 Appendix D Migration from HighEnd to Enhanced Devices 396 Index 397 The Microchip Web Site 407 Customer Change Notification Service 407 Customer Support 407 Reader Response 408 PIC18F2420252044204520 Product Identification System 409 2008 Microchip Technology Inc DS39631Epage 5 PIC18F2420252044204520 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products To this end we will continue to improve our publications to better suit your needs Our publications will be refined and enhanced as new volumes and updates are introduced If you have any questions or comments regarding this publication please contact the Marketing Communications Department via Email at docerrorsmicrochipcom or fax the Reader Response Form in the back of this data sheet to 480 7924150 We welcome your feedback Most Current Data Sheet To obtain the most uptodate version of this data sheet please register at our Worldwide Web site at httpwwwmicrochipcom You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature number is the version number eg DS30000A is version A of document DS30000 Errata An errata sheet describing minor operational differences from the data sheet and recommended workarounds may exist for current devices As devicedocumentation issues become known to us we will publish an errata sheet The errata will specify the revision of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device please check with one of the following Microchips Worldwide Web site httpwwwmicrochipcom Your local Microchip sales office see last page When contacting a sales office please specify which device revision of silicon and data sheet include literature number you are using Customer Notification System Register on our web site at wwwmicrochipcom to receive the most current information on all of our products PIC18F2420252044204520 DS39631Epage 6 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 7 PIC18F2420252044204520 10 DEVICE OVERVIEW This document contains devicespecific information for the following devices This family offers the advantages of all PIC18 microcontrollers namely high computational perfor mance at an economical price with the addition of highendurance Enhanced Flash program memory On top of these features the PIC18F242025204420 4520 family introduces design enhancements that make these microcontrollers a logical choice for many highperformance power sensitive applications 11 New Core Features 111 nanoWatt TECHNOLOGY All of the devices in the PIC18F2420252044204520 family incorporate a range of features that can signifi cantly reduce power consumption during operation Key items include Alternate Run Modes By clocking the controller from the Timer1 source or the internal oscillator block power consumption during code execution can be reduced by as much as 90 Multiple Idle Modes The controller can also run with its CPU core disabled but the peripherals still active In these states power consumption can be reduced even further to as little as 4 of normal operation requirements OntheFly Mode Switching The power managed modes are invoked by user code during operation allowing the user to incorporate powersaving ideas into their applications software design Low Consumption in Key Modules The power requirements for both Timer1 and the Watchdog Timer are minimized See Section 260 Electrical Characteristics for values 112 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2420252044204520 family offer ten different oscillator options allowing users a wide range of choices in developing application hardware These include Four Crystal modes using crystals or ceramic resonators Two External Clock modes offering the option of using two pins oscillator input and a divideby4 clock output or one pin oscillator input with the second pin reassigned as general IO Two External RC Oscillator modes with the same pin options as the External Clock modes An internal oscillator block which provides an 8 MHz clock and an INTRC source approximately 31 kHz as well as a range of 6 userselectable clock frequencies between 125 kHz to 4 MHz for a total of 8 clock frequencies This option frees the two oscillator pins for use as additional general purpose IO A Phase Lock Loop PLL frequency multiplier available to both the HighSpeed Crystal and Inter nal Oscillator modes which allows clock speeds of up to 40 MHz Used with the internal oscillator the PLL gives users a complete selection of clock speeds from 31 kHz to 32 MHz all without using an external crystal or clock circuit Besides its availability as a clock source the internal oscillator block provides a stable reference source that gives the family additional features for robust operation FailSafe Clock Monitor This option constantly monitors the main clock source against a refer ence signal provided by the internal oscillator If a clock failure occurs the controller is switched to the internal oscillator block allowing for continued lowspeed operation or a safe application shutdown TwoSpeed Startup This option allows the internal oscillator to serve as the clock source from Poweron Reset or wakeup from Sleep mode until the primary clock source is available PIC18F2420 PIC18LF2420 PIC18F2520 PIC18LF2520 PIC18F4420 PIC18LF4420 PIC18F4520 PIC18LF4520 PIC18F2420252044204520 DS39631Epage 8 2008 Microchip Technology Inc 12 Other Special Features Memory Endurance The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erasewrite cycles up to 100000 for program memory and 1000000 for EEPROM Data retention without refresh is conservatively estimated to be greater than 40 years SelfProgrammability These devices can write to their own program memory spaces under internal software control By using a bootloader routine located in the protected Boot Block at the top of program memory it becomes possible to create an application that can update itself in the field Extended Instruction Set The PIC18F2420 252044204520 family introduces an optional extension to the PIC18 instruction set which adds 8 new instructions and an Indexed Addressing mode This extension enabled as a device con figuration option has been specifically designed to optimize reentrant application code originally developed in highlevel languages such as C Enhanced CCP Module In PWM mode this module provides 1 2 or 4 modulated outputs for controlling halfbridge and fullbridge drivers Other features include autoshutdown for dis abling PWM outputs on interrupt or other select conditions and autorestart to reactivate outputs once the condition has cleared Enhanced Addressable USART This serial communication module is capable of standard RS232 operation and provides support for the LIN bus protocol Other enhancements include automatic baud rate detection and a 16bit Baud Rate Generator for improved resolution When the microcontroller is using the internal oscillator block the EUSART provides stable operation for applications that talk to the outside world without using an external crystal or its accompanying power requirement 10Bit AD Converter This module incorporates programmable acquisition time allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus reducing code overhead Extended Watchdog Timer WDT This enhanced version incorporates a 16bit prescaler allowing an extended timeout range that is stable across operating voltage and temperature See Section 260 Electrical Characteristics for timeout periods 13 Details on Individual Family Members Devices in the PIC18F2420252044204520 family are available in 28pin and 4044pin packages Block diagrams for the two groups are shown in Figure 11 and Figure 12 The devices are differentiated from each other in five ways 1 Flash program memory 16 Kbytes for PIC18F24204420 devices and 32 Kbytes for PIC18F25204520 devices 2 AD channels 10 for 28pin devices 13 for 4044pin devices 3 IO ports 3 bidirectional ports on 28pin devices 5 bidirectional ports on 4044pin devices 4 CCP and Enhanced CCP implementation 28pin devices have 2 standard CCP modules 4044pin devices have one standard CCP module and one ECCP module 5 Parallel Slave Port present only on 4044pin devices All other features for devices in this family are identical These are summarized in Table 11 The pinouts for all devices are listed in Table 12 and Table 13 Like all Microchip PIC18 devices members of the PIC18F2420252044204520 family are available as both standard and lowvoltage devices Standard devices with Enhanced Flash memory designated with an F in the part number such as PIC18F2420 accommodate an operating VDD range of 42V to 55V Lowvoltage parts designated by LF such as PIC18LF2420 function over an extended VDD range of 20V to 55V 2008 Microchip Technology Inc DS39631Epage 9 PIC18F2420252044204520 TABLE 11 DEVICE FEATURES Features PIC18F2420 PIC18F2520 PIC18F4420 PIC18F4520 Operating Frequency DC 40 MHz DC 40 MHz DC 40 MHz DC 40 MHz Program Memory Bytes 16384 32768 16384 32768 Program Memory Instructions 8192 16384 8192 16384 Data Memory Bytes 768 1536 768 1536 Data EEPROM Memory Bytes 256 256 256 256 Interrupt Sources 19 19 20 20 IO Ports Ports A B C E Ports A B C E Ports A B C D E Ports A B C D E Timers 4 4 4 4 CaptureComparePWM Modules 2 2 1 1 Enhanced CaptureComparePWM Modules 0 0 1 1 Serial Communications MSSP Enhanced USART MSSP Enhanced USART MSSP Enhanced USART MSSP Enhanced USART Parallel Communications PSP No No Yes Yes 10Bit AnalogtoDigital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Resets and Delays POR BOR RESET Instruction Stack Full Stack Underflow PWRT OST MCLR optional WDT POR BOR RESET Instruction Stack Full Stack Underflow PWRT OST MCLR optional WDT POR BOR RESET Instruction Stack Full Stack Underflow PWRT OST MCLR optional WDT POR BOR RESET Instruction Stack Full Stack Underflow PWRT OST MCLR optional WDT Programmable HighLowVoltage Detect Yes Yes Yes Yes Programmable Brownout Reset Yes Yes Yes Yes Instruction Set 75 Instructions 83 with Extended Instruction Set Enabled 75 Instructions 83 with Extended Instruction Set Enabled 75 Instructions 83 with Extended Instruction Set Enabled 75 Instructions 83 with Extended Instruction Set Enabled Packages 28Pin SPDIP 28Pin SOIC 28Pin QFN 28Pin SPDIP 28Pin SOIC 28Pin QFN 40Pin PDIP 44Pin QFN 44Pin TQFP 40Pin PDIP 44Pin QFN 44Pin TQFP PIC18F2420252044204520 DS39631Epage 10 2008 Microchip Technology Inc FIGURE 11 PIC18F24202520 28PIN BLOCK DIAGRAM Instruction Decode and Control PORTA PORTB PORTC RA4T0CKIC1OUT RA5AN4SSHLVDINC2OUT RB0INT0FLT0AN12 RC0T1OSOT13CKI RC1T1OSICCP21 RC2CCP1 RC3SCKSCL RC4SDISDA RC5SDO RC6TXCK RC7RXDT RA3AN3VREF RA2AN2VREFCVREF RA1AN1 RA0AN0 RB1INT1AN10 Data Latch Data Memory 39 Kbytes Address Latch Data Address12 12 Access BSR FSR0 FSR1 FSR2 incdec logic Address 4 12 4 PCH PCL PCLATH 8 31Level Stack Program Counter PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU8 Address Latch Program Memory 1632 Kbytes Data Latch 20 8 8 Table Pointer21 incdec logic 21 8 Data Bus8 Table Latch 8 IR 12 3 ROM Latch RB2INT2AN8 RB3AN9CCP21 PCLATU PCU OSC2CLKO3RA6 Note 1 CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set or RB3 when CCP2MX is not set 2 RE3 is only available when MCLR functionality is disabled 3 OSC1CLKI and OSC2CLKO are only available in select oscillator modes and when these pins are not being used as digital IO Refer to Section 20 Oscillator Configurations for additional information RB4KBI0AN11 RB5KBI1PGM RB6KBI2PGC RB7KBI3PGD EUSART Comparator MSSP 10Bit ADC Timer2 Timer1 Timer3 Timer0 CCP2 HLVD CCP1 BOR Data EEPROM W Instruction Bus 16 STKPTR Bank 8 State Machine Control Signals Decode 8 8 Powerup Timer Oscillator Startup Timer Poweron Reset Watchdog Timer OSC13 OSC23 VDD Brownout Reset Internal Oscillator FailSafe Clock Monitor Precision Reference Band Gap VSS MCLR2 Block INTRC Oscillator 8 MHz Oscillator SingleSupply Programming InCircuit Debugger T1OSO OSC1CLKI3RA7 T1OSI PORTE MCLRVPPRE32 2008 Microchip Technology Inc DS39631Epage 11 PIC18F2420252044204520 FIGURE 12 PIC18F44204520 4044PIN BLOCK DIAGRAM Instruction Decode and Control Data Latch Data Memory 39 Kbytes Address Latch Data Address12 12 Access BSR FSR0 FSR1 FSR2 incdec logic Address 4 12 4 PCH PCL PCLATH 8 31Level Stack Program Counter PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU8 Address Latch Program Memory 1632 Kbytes Data Latch 20 8 8 Table Pointer21 incdec logic 21 8 Data Bus8 Table Latch 8 IR 12 3 ROM Latch PORTD RD0PSP0 PCLATU PCU PORTE MCLRVPPRE32 RE2CSAN7 RE0RDAN5 RE1WRAN6 Note 1 CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set or RB3 when CCP2MX is not set 2 RE3 is only available when MCLR functionality is disabled 3 OSC1CLKI and OSC2CLKO are only available in select oscillator modes and when these pins are not being used as digital IO Refer to Section 20 Oscillator Configurations for additional information RD4PSP4 EUSART Comparator MSSP 10Bit ADC Timer2 Timer1 Timer3 Timer0 CCP2 HLVD ECCP1 BOR Data EEPROM W Instruction Bus 16 STKPTR Bank 8 State Machine Control Signals Decode 8 8 Powerup Timer Oscillator Startup Timer Poweron Reset Watchdog Timer OSC13 OSC23 VDD Brownout Reset Internal Oscillator FailSafe Clock Monitor Precision Reference Band Gap VSS MCLR2 Block INTRC Oscillator 8 MHz Oscillator SingleSupply Programming InCircuit Debugger T1OSI T1OSO RD5PSP5P1B RD6PSP6P1C RD7PSP7P1D PORTA PORTB PORTC RA4T0CKIC1OUT RA5AN4SSHLVDINC2OUT RB0INT0FLT0AN12 RC0T1OSOT13CKI RC1T1OSICCP21 RC2CCP1P1A RC3SCKSCL RC4SDISDA RC5SDO RC6TXCK RC7RXDT RA3AN3VREF RA2AN2VREFCVREF RA1AN1 RA0AN0 RB1INT1AN10 RB2INT2AN8 RB3AN9CCP21 OSC2CLKO3RA6 RB4KBI0AN11 RB5KBI1PGM RB6KBI2PGC RB7KBI3PGD OSC1CLKI3RA7 PIC18F2420252044204520 DS39631Epage 12 2008 Microchip Technology Inc TABLE 12 PIC18F24202520 PINOUT IO DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description SPDIP SOIC QFN MCLRVPPRE3 MCLR VPP RE3 1 26 I P I ST ST Master Clear input or programming voltage input Master Clear Reset input This pin is an activelow Reset to the device Programming voltage input Digital input OSC1CLKIRA7 OSC1 CLKI RA7 9 6 I I IO ST CMOS TTL Oscillator crystal or external clock input Oscillator crystal input or external clock source input ST buffer when configured in RC mode CMOS otherwise External clock source input Always associated with pin function OSC1 See related OSC1CLKI OSC2CLKO pins General purpose IO pin OSC2CLKORA6 OSC2 CLKO RA6 10 7 O O IO TTL Oscillator crystal or clock output Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode In RC mode OSC2 pin outputs CLKO which has 14 the frequency of OSC1 and denotes the instruction cycle rate General purpose IO pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared 2008 Microchip Technology Inc DS39631Epage 13 PIC18F2420252044204520 PORTA is a bidirectional IO port RA0AN0 RA0 AN0 2 27 IO I TTL Analog Digital IO Analog input 0 RA1AN1 RA1 AN1 3 28 IO I TTL Analog Digital IO Analog input 1 RA2AN2VREFCVREF RA2 AN2 VREF CVREF 4 1 IO I I O TTL Analog Analog Analog Digital IO Analog input 2 AD reference voltage low input Comparator reference voltage output RA3AN3VREF RA3 AN3 VREF 5 2 IO I I TTL Analog Analog Digital IO Analog input 3 AD reference voltage high input RA4T0CKIC1OUT RA4 T0CKI C1OUT 6 3 IO I O ST ST Digital IO Timer0 external clock input Comparator 1 output RA5AN4SSHLVDIN C2OUT RA5 AN4 SS HLVDIN C2OUT 7 4 IO I I I O TTL Analog TTL Analog Digital IO Analog input 4 SPI slave select input HighLowVoltage Detect input Comparator 2 output RA6 See the OSC2CLKORA6 pin RA7 See the OSC1CLKIRA7 pin TABLE 12 PIC18F24202520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description SPDIP SOIC QFN Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared PIC18F2420252044204520 DS39631Epage 14 2008 Microchip Technology Inc PORTB is a bidirectional IO port PORTB can be software programmed for internal weak pullups on all inputs RB0INT0FLT0AN12 RB0 INT0 FLT0 AN12 21 18 IO I I I TTL ST ST Analog Digital IO External interrupt 0 PWM Fault input for CCP1 Analog input 12 RB1INT1AN10 RB1 INT1 AN10 22 19 IO I I TTL ST Analog Digital IO External interrupt 1 Analog input 10 RB2INT2AN8 RB2 INT2 AN8 23 20 IO I I TTL ST Analog Digital IO External interrupt 2 Analog input 8 RB3AN9CCP2 RB3 AN9 CCP21 24 21 IO I IO TTL Analog ST Digital IO Analog input 9 Capture 2 inputCompare 2 outputPWM2 output RB4KBI0AN11 RB4 KBI0 AN11 25 22 IO I I TTL TTL Analog Digital IO Interruptonchange pin Analog input 11 RB5KBI1PGM RB5 KBI1 PGM 26 23 IO I IO TTL TTL ST Digital IO Interruptonchange pin LowVoltage ICSP Programming enable pin RB6KBI2PGC RB6 KBI2 PGC 27 24 IO I IO TTL TTL ST Digital IO Interruptonchange pin InCircuit Debugger and ICSP programming clock pin RB7KBI3PGD RB7 KBI3 PGD 28 25 IO I IO TTL TTL ST Digital IO Interruptonchange pin InCircuit Debugger and ICSP programming data pin TABLE 12 PIC18F24202520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description SPDIP SOIC QFN Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared 2008 Microchip Technology Inc DS39631Epage 15 PIC18F2420252044204520 PORTC is a bidirectional IO port RC0T1OSOT13CKI RC0 T1OSO T13CKI 11 8 IO O I ST ST Digital IO Timer1 oscillator output Timer1Timer3 external clock input RC1T1OSICCP2 RC1 T1OSI CCP22 12 9 IO I IO ST Analog ST Digital IO Timer1 oscillator input Capture 2 inputCompare 2 outputPWM2 output RC2CCP1 RC2 CCP1 13 10 IO IO ST ST Digital IO Capture 1 inputCompare 1 outputPWM1 output RC3SCKSCL RC3 SCK SCL 14 11 IO IO IO ST ST ST Digital IO Synchronous serial clock inputoutput for SPI mode Synchronous serial clock inputoutput for I2C mode RC4SDISDA RC4 SDI SDA 15 12 IO I IO ST ST ST Digital IO SPI data in I2C data IO RC5SDO RC5 SDO 16 13 IO O ST Digital IO SPI data out RC6TXCK RC6 TX CK 17 14 IO O IO ST ST Digital IO EUSART asynchronous transmit EUSART synchronous clock see related RXDT RC7RXDT RC7 RX DT 18 15 IO I IO ST ST ST Digital IO EUSART asynchronous receive EUSART synchronous data see related TXCK RE3 See MCLRVPPRE3 pin VSS 8 19 5 16 P Ground reference for logic and IO pins VDD 20 17 P Positive supply for logic and IO pins TABLE 12 PIC18F24202520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description SPDIP SOIC QFN Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared PIC18F2420252044204520 DS39631Epage 16 2008 Microchip Technology Inc TABLE 13 PIC18F44204520 PINOUT IO DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP MCLRVPPRE3 MCLR VPP RE3 1 18 18 I P I ST ST Master Clear input or programming voltage input Master Clear Reset input This pin is an activelow Reset to the device Programming voltage input Digital input OSC1CLKIRA7 OSC1 CLKI RA7 13 32 30 I I IO ST CMOS TTL Oscillator crystal or external clock input Oscillator crystal input or external clock source input ST buffer when configured in RC mode analog otherwise External clock source input Always associated with pin function OSC1 See related OSC1CLKI OSC2CLKO pins General purpose IO pin OSC2CLKORA6 OSC2 CLKO RA6 14 33 31 O O IO TTL Oscillator crystal or clock output Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode In RC mode OSC2 pin outputs CLKO which has 14 the frequency of OSC1 and denotes the instruction cycle rate General purpose IO pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared 2008 Microchip Technology Inc DS39631Epage 17 PIC18F2420252044204520 PORTA is a bidirectional IO port RA0AN0 RA0 AN0 2 19 19 IO I TTL Analog Digital IO Analog input 0 RA1AN1 RA1 AN1 3 20 20 IO I TTL Analog Digital IO Analog input 1 RA2AN2VREFCVREF RA2 AN2 VREF CVREF 4 21 21 IO I I O TTL Analog Analog Analog Digital IO Analog input 2 AD reference voltage low input Comparator reference voltage output RA3AN3VREF RA3 AN3 VREF 5 22 22 IO I I TTL Analog Analog Digital IO Analog input 3 AD reference voltage high input RA4T0CKIC1OUT RA4 T0CKI C1OUT 6 23 23 IO I O ST ST Digital IO Timer0 external clock input Comparator 1 output RA5AN4SSHLVDIN C2OUT RA5 AN4 SS HLVDIN C2OUT 7 24 24 IO I I I O TTL Analog TTL Analog Digital IO Analog input 4 SPI slave select input HighLowVoltage Detect input Comparator 2 output RA6 See the OSC2CLKORA6 pin RA7 See the OSC1CLKIRA7 pin TABLE 13 PIC18F44204520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared PIC18F2420252044204520 DS39631Epage 18 2008 Microchip Technology Inc PORTB is a bidirectional IO port PORTB can be software programmed for internal weak pullups on all inputs RB0INT0FLT0AN12 RB0 INT0 FLT0 AN12 33 9 8 IO I I I TTL ST ST Analog Digital IO External interrupt 0 PWM Fault input for Enhanced CCP1 Analog input 12 RB1INT1AN10 RB1 INT1 AN10 34 10 9 IO I I TTL ST Analog Digital IO External interrupt 1 Analog input 10 RB2INT2AN8 RB2 INT2 AN8 35 11 10 IO I I TTL ST Analog Digital IO External interrupt 2 Analog input 8 RB3AN9CCP2 RB3 AN9 CCP21 36 12 11 IO I IO TTL Analog ST Digital IO Analog input 9 Capture 2 inputCompare 2 outputPWM2 output RB4KBI0AN11 RB4 KBI0 AN11 37 14 14 IO I I TTL TTL Analog Digital IO Interruptonchange pin Analog input 11 RB5KBI1PGM RB5 KBI1 PGM 38 15 15 IO I IO TTL TTL ST Digital IO Interruptonchange pin LowVoltage ICSP Programming enable pin RB6KBI2PGC RB6 KBI2 PGC 39 16 16 IO I IO TTL TTL ST Digital IO Interruptonchange pin InCircuit Debugger and ICSP programming clock pin RB7KBI3PGD RB7 KBI3 PGD 40 17 17 IO I IO TTL TTL ST Digital IO Interruptonchange pin InCircuit Debugger and ICSP programming data pin TABLE 13 PIC18F44204520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared 2008 Microchip Technology Inc DS39631Epage 19 PIC18F2420252044204520 PORTC is a bidirectional IO port RC0T1OSOT13CKI RC0 T1OSO T13CKI 15 34 32 IO O I ST ST Digital IO Timer1 oscillator output Timer1Timer3 external clock input RC1T1OSICCP2 RC1 T1OSI CCP22 16 35 35 IO I IO ST CMOS ST Digital IO Timer1 oscillator input Capture 2 inputCompare 2 outputPWM2 output RC2CCP1P1A RC2 CCP1 P1A 17 36 36 IO IO O ST ST Digital IO Capture 1 inputCompare 1 outputPWM1 output Enhanced CCP1 output RC3SCKSCL RC3 SCK SCL 18 37 37 IO IO IO ST ST ST Digital IO Synchronous serial clock inputoutput for SPI mode Synchronous serial clock inputoutput for I2C mode RC4SDISDA RC4 SDI SDA 23 42 42 IO I IO ST ST ST Digital IO SPI data in I2C data IO RC5SDO RC5 SDO 24 43 43 IO O ST Digital IO SPI data out RC6TXCK RC6 TX CK 25 44 44 IO O IO ST ST Digital IO EUSART asynchronous transmit EUSART synchronous clock see related RXDT RC7RXDT RC7 RX DT 26 1 1 IO I IO ST ST ST Digital IO EUSART asynchronous receive EUSART synchronous data see related TXCK TABLE 13 PIC18F44204520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared PIC18F2420252044204520 DS39631Epage 20 2008 Microchip Technology Inc PORTD is a bidirectional IO port or a Parallel Slave Port PSP for interfacing to a microprocessor port These pins have TTL input buffers when PSP module is enabled RD0PSP0 RD0 PSP0 19 38 38 IO IO ST TTL Digital IO Parallel Slave Port data RD1PSP1 RD1 PSP1 20 39 39 IO IO ST TTL Digital IO Parallel Slave Port data RD2PSP2 RD2 PSP2 21 40 40 IO IO ST TTL Digital IO Parallel Slave Port data RD3PSP3 RD3 PSP3 22 41 41 IO IO ST TTL Digital IO Parallel Slave Port data RD4PSP4 RD4 PSP4 27 2 2 IO IO ST TTL Digital IO Parallel Slave Port data RD5PSP5P1B RD5 PSP5 P1B 28 3 3 IO IO O ST TTL Digital IO Parallel Slave Port data Enhanced CCP1 output RD6PSP6P1C RD6 PSP6 P1C 29 4 4 IO IO O ST TTL Digital IO Parallel Slave Port data Enhanced CCP1 output RD7PSP7P1D RD7 PSP7 P1D 30 5 5 IO IO O ST TTL Digital IO Parallel Slave Port data Enhanced CCP1 output TABLE 13 PIC18F44204520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared 2008 Microchip Technology Inc DS39631Epage 21 PIC18F2420252044204520 PORTE is a bidirectional IO port RE0RDAN5 RE0 RD AN5 8 25 25 IO I I ST TTL Analog Digital IO Read control for Parallel Slave Port see also WR and CS pins Analog input 5 RE1WRAN6 RE1 WR AN6 9 26 26 IO I I ST TTL Analog Digital IO Write control for Parallel Slave Port see CS and RD pins Analog input 6 RE2CSAN7 RE2 CS AN7 10 27 27 IO I I ST TTL Analog Digital IO Chip Select control for Parallel Slave Port see related RD and WR Analog input 7 RE3 See MCLRVPPRE3 pin VSS 12 31 6 30 31 6 29 P Ground reference for logic and IO pins VDD 11 32 7 8 28 29 7 28 P Positive supply for logic and IO pins NC 13 12 13 33 34 No Connect TABLE 13 PIC18F44204520 PINOUT IO DESCRIPTIONS CONTINUED Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels I Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared PIC18F2420252044204520 DS39631Epage 22 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 23 PIC18F2420252044204520 20 OSCILLATOR CONFIGURATIONS 21 Oscillator Types PIC18F2420252044204520 devices can be operated in ten different oscillator modes The user can program the Configuration bits FOSC30 in Configuration Register 1H to select one of these ten modes 1 LP LowPower Crystal 2 XT CrystalResonator 3 HS HighSpeed CrystalResonator 4 HSPLL HighSpeed CrystalResonator with PLL Enabled 5 RC External ResistorCapacitor with FOSC4 Output on RA6 6 RCIO External ResistorCapacitor with IO on RA6 7 INTIO1 Internal Oscillator with FOSC4 Output on RA6 and IO on RA7 8 INTIO2 Internal Oscillator with IO on RA6 and RA7 9 EC External Clock with FOSC4 Output 10 ECIO External Clock with IO on RA6 22 Crystal OscillatorCeramic Resonators In XT LP HS or HSPLL Oscillator modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation Figure 21 shows the pin connections The oscillator design requires the use of a parallel cut crystal FIGURE 21 CRYSTALCERAMIC RESONATOR OPERATION XT LP HS OR HSPLL CONFIGURATION TABLE 21 CAPACITOR SELECTION FOR CERAMIC RESONATORS Note Use of a series cut crystal may give a fre quency out of the crystal manufacturers specifications Typical Capacitor Values Used Mode Freq OSC1 OSC2 XT 358 MHz 419 MHz 4 MHz 4 MHz 15 pF 15 pF 30 pF 50 pF 15 pF 15 pF 30 pF 50 pF Capacitor values are for design guidance only Different capacitor values may be required to produce acceptable oscillator operation The user should test the performance of the oscillator over the expected VDD and temperature range for the application See the notes following Table 22 for additional information Note When using resonators with frequencies above 35 MHz the use of HS mode rather than XT mode is recommended HS mode may be used at any VDD for which the controller is rated If HS is selected it is possible that the gain of the oscillator will overdrive the resonator Therefore a series resistor should be placed between the OSC2 pin and the resonator As a good starting point the recommended value of RS is 330Ω Note 1 See Table 21 and Table 22 for initial values of C1 and C2 2 A series resistor RS may be required for AT strip cut crystals 3 RF varies with the oscillator mode chosen C11 C21 XTAL OSC2 OSC1 RF3 Sleep To Logic PIC18FXXXX RS2 Internal PIC18F2420252044204520 DS39631Epage 24 2008 Microchip Technology Inc TABLE 22 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR An external clock source may also be connected to the OSC1 pin in the HS mode as shown in Figure 22 FIGURE 22 EXTERNAL CLOCK INPUT OPERATION HS OSC CONFIGURATION 23 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin There is no oscillator startup time required after a Poweron Reset or after an exit from Sleep mode In the EC Oscillator mode the oscillator frequency divided by 4 is available on the OSC2 pin This signal may be used for test purposes or to synchronize other logic Figure 23 shows the pin connections for the EC Oscillator mode FIGURE 23 EXTERNAL CLOCK INPUT OPERATION EC CONFIGURATION The ECIO Oscillator mode functions like the EC mode except that the OSC2 pin becomes an additional gen eral purpose IO pin The IO pin becomes bit 6 of PORTA RA6 Figure 24 shows the pin connections for the ECIO Oscillator mode FIGURE 24 EXTERNAL CLOCK INPUT OPERATION ECIO CONFIGURATION Osc Type Crystal Freq Typical Capacitor Values Tested C1 C2 LP 32 kHz 30 pF 30 pF XT 1 MHz 4 MHz 15 pF 15 pF 15 pF 15 pF HS 4 MHz 10 MHz 20 MHz 25 MHz 25 MHz 15 pF 15 pF 15 pF 0 pF 15 pF 15 pF 15 pF 15 pF 5 pF 15 pF Capacitor values are for design guidance only These capacitors were tested with the crystals listed below for basic startup and operation These values are not optimized Different capacitor values may be required to produce acceptable oscillator operation The user should test the performance of the oscillator over the expected VDD and temperature range for the application See the notes following this table for additional information Crystals Used 32 kHz 4 MHz 25 MHz 10 MHz 1 MHz 20 MHz Note 1 Higher capacitance increases the stability of the oscillator but also increases the startup time 2 When operating below 3V VDD or when using certain ceramic resonators at any voltage it may be necessary to use the HS mode or switch to a crystal oscillator 3 Since each resonatorcrystal has its own characteristics the user should consult the resonatorcrystal manufacturer for appropriate values of external components 4 Rs may be required to avoid overdriving crystals with low drive level specification 5 Always verify oscillator performance over the VDD and temperature range that is expected for the application OSC1 OSC2 Open Clock from Ext System PIC18FXXXX HS Mode OSC1CLKI OSC2CLKO FOSC4 Clock from Ext System PIC18FXXXX OSC1CLKI IO OSC2 RA6 Clock from Ext System PIC18FXXXX 2008 Microchip Technology Inc DS39631Epage 25 PIC18F2420252044204520 24 RC Oscillator For timing insensitive applications the RC and RCIO device options offer additional cost savings The actual oscillator frequency is a function of several factors supply voltage values of the external resistor REXT and capacitor CEXT operating temperature Given the same device operating voltage and tempera ture and component values there will also be unittounit frequency variations These are due to factors such as normal manufacturing variation difference in lead frame capacitance between package types especially for low CEXT values variations within the tolerance of limits of REXT and CEXT In the RC Oscillator mode the oscillator frequency divided by 4 is available on the OSC2 pin This signal may be used for test purposes or to synchronize other logic Figure 25 shows how the RC combination is connected FIGURE 25 RC OSCILLATOR MODE The RCIO Oscillator mode Figure 26 functions like the RC mode except that the OSC2 pin becomes an additional general purpose IO pin The IO pin becomes bit 6 of PORTA RA6 FIGURE 26 RCIO OSCILLATOR MODE 25 PLL Frequency Multiplier A Phase Locked Loop PLL circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator This may be useful for customers who are concerned with EMI due to highfrequency crystals or users who require higher clock speeds from an internal oscillator 251 HSPLL OSCILLATOR MODE The HSPLL mode makes use of the HS Oscillator mode for frequencies up to 10 MHz A PLL then multi plies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz The PLLEN bit is not available in this oscillator mode The PLL is only available to the crystal oscillator when the FOSC30 Configuration bits are programmed for HSPLL mode 0110 FIGURE 27 PLL BLOCK DIAGRAM HS MODE 252 PLL AND INTOSC The PLL is also available to the internal oscillator block in selected oscillator modes In this configuration the PLL is enabled in software and generates a clock out put of up to 32 MHz The operation of INTOSC with the PLL is described in Section 264 PLL in INTOSC Modes OSC2CLKO CEXT REXT PIC18FXXXX OSC1 FOSC4 Internal Clock VDD VSS Recommended values 3 kΩ REXT 100 kΩ CEXT 20 pF CEXT REXT PIC18FXXXX OSC1 Internal Clock VDD VSS Recommended values 3 kΩ REXT 100 kΩ CEXT 20 pF IO OSC2 RA6 MUX VCO Loop Filter Crystal Osc OSC2 OSC1 PLL Enable FIN FOUT SYSCLK Phase Comparator HS Oscillator Enable 4 from Configuration Register 1H HS Mode PIC18F2420252044204520 DS39631Epage 26 2008 Microchip Technology Inc 26 Internal Oscillator Block The PIC18F2420252044204520 devices include an internal oscillator block which generates two different clock signals either can be used as the micro controllers clock source This may eliminate the need for external oscillator circuits on the OSC1 andor OSC2 pins The main output INTOSC is an 8 MHz clock source which can be used to directly drive the device clock It also drives a postscaler which can provide a range of clock frequencies from 31 kHz to 4 MHz The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected The other clock source is the internal RC oscillator INTRC which provides a nominal 31 kHz output INTRC is enabled if it is selected as the device clock source it is also enabled automatically when any of the following are enabled Powerup Timer FailSafe Clock Monitor Watchdog Timer TwoSpeed Startup These features are discussed in greater detail in Section 230 Special Features of the CPU The clock source frequency INTOSC direct INTRC direct or INTOSC postscaler is selected by configuring the IRCF bits of the OSCCON register page 30 261 INTIO MODES Using the internal oscillator as the clock source elimi nates the need for up to two external oscillator pins which can then be used for digital IO Two distinct configurations are available In INTIO1 mode the OSC2 pin outputs FOSC4 while OSC1 functions as RA7 for digital input and output In INTIO2 mode OSC1 functions as RA7 and OSC2 functions as RA6 both for digital input and output 262 INTOSC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 80 MHz The INTRC oscillator operates independently of the INTOSC source Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa 263 OSCTUNE REGISTER The internal oscillators output has been calibrated at the factory but can be adjusted in the users applica tion This is done by writing to the OSCTUNE register Register 21 When the OSCTUNE register is modified the INTOSC frequency will begin shifting to the new frequency The INTRC clock will reach the new frequency within 8 clock cycles approximately 8 32 μs 256 μs The INTOSC clock will stabilize within 1 ms Code execu tion continues during this shift There is no indication that the shift has occurred The OSCTUNE register also implements the INTSRC and PLLEN bits which control certain features of the internal oscillator block The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected This is covered in greater detail in Section 271 Oscillator Control Register The PLLEN bit controls the operation of the frequency multiplier PLL in internal oscillator modes 264 PLL IN INTOSC MODES The 4x frequency multiplier can be used with the inter nal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator When enabled the PLL produces a clock speed of up to 32 MHz Unlike HSPLL mode the PLL is controlled through software The control bit PLLEN OSCTUNE6 is used to enable or disable its operation The PLL is available when the device is configured to use the internal oscillator block as its primary clock source FOSC30 1001 or 1000 Additionally the PLL will only function when the selected output fre quency is either 4 MHz or 8 MHz OSCCON64 111 or 110 If both of these conditions are not met the PLL is disabled The PLLEN control bit is only functional in those inter nal oscillator modes where the PLL is available In all other modes it is forced to 0 and is effectively unavailable 265 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output INTOSC for 8 MHz However this frequency may drift as VDD or temperature changes which can affect the controller operation in a variety of ways It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register This has no effect on the INTRC clock source frequency Tuning the INTOSC source requires knowing when to make the adjustment in which direction it should be made and in some cases how large a change is needed Three compensation techniques are discussed in Section 2651 Compensating with the EUSART Section 2652 Compensating with the Timers and Section 2653 Compensating with the CCP Module in Capture Mode but other techniques may be used 2008 Microchip Technology Inc DS39631Epage 27 PIC18F2420252044204520 2651 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode Framing errors indicate that the device clock frequency is too high To adjust for this decrement the value in OSCTUNE to reduce the clock frequency On the other hand errors in data may suggest that the clock speed is too low To compensate increment OSCTUNE to increase the clock frequency 2652 Compensating with the Timers This technique compares device clock speed to some reference clock Two timers may be used one timer is clocked by the peripheral clock while the other is clocked by a fixed reference source such as the Timer1 oscillator Both timers are cleared but the timer clocked by the reference generates interrupts When an interrupt occurs the internally clocked timer is read and both timers are cleared If the internally clocked timer value is greater than expected then the internal oscillator block is running too fast To adjust for this decrement the OSCTUNE register 2653 Compensating with the CCP Module in Capture Mode A CCP module can use freerunning Timer1 or Timer3 clocked by the internal oscillator block and an external event with a known period ie AC power fre quency The time of the first event is captured in the CCPRxHCCPRxL registers and is recorded for use later When the second event causes a capture the time of the first event is subtracted from the time of the second event Since the period of the external event is known the time difference between events can be calculated If the measured time is much greater than the calcu lated time the internal oscillator block is running too fast to compensate decrement the OSCTUNE register If the measured time is much less than the calculated time the internal oscillator block is running too slow to compensate increment the OSCTUNE register REGISTER 21 OSCTUNE OSCILLATOR TUNING REGISTER RW0 RW01 U0 RW0 RW0 RW0 RW0 RW0 INTSRC PLLEN1 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 INTSRC Internal Oscillator LowFrequency Source Select bit 1 3125 kHz device clock derived from 8 MHz INTOSC source divideby256 enabled 0 31 kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN Frequency Multiplier PLL for INTOSC Enable bit1 1 PLL enabled for INTOSC 4 MHz and 8 MHz only 0 PLL disabled bit 5 Unimplemented Read as 0 bit 40 TUN40 Frequency Tuning bits 011111 Maximum frequency 000001 000000 Center frequency Oscillator module is running at the calibrated frequency 111111 100000 Minimum frequency Note 1 Available only in certain oscillator configurations otherwise this bit is unavailable and reads as 0 See Section 264 PLL in INTOSC Modes for details PIC18F2420252044204520 DS39631Epage 28 2008 Microchip Technology Inc 27 Clock Sources and Oscillator Switching Like previous PIC18 devices the PIC18F24202520 44204520 family includes a feature that allows the device clock source to be switched from the main oscil lator to an alternate lowfrequency clock source PIC18F2420252044204520 devices offer two alternate clock sources When an alternate clock source is enabled the various powermanaged operating modes are available Essentially there are three clock sources for these devices Primary oscillators Secondary oscillators Internal oscillator block The primary oscillators include the External Crystal and Resonator modes the External RC modes the External Clock modes and the internal oscillator block The particular mode is defined by the FOSC30 Con figuration bits The details of these modes are covered earlier in this chapter The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins These sources may continue to operate even after the controller is placed in a powermanaged mode PIC18F2420252044204520 devices offer the Timer1 oscillator as a secondary oscillator This oscillator in all powermanaged modes is often the time base for functions such as a RealTime Clock RTC Most often a 32768 kHz watch crystal is connected between the RC0T1OSOT13CKI and RC1T1OSI pins Like the LP Oscillator mode circuit loading capacitors are also connected from each pin to ground The Timer1 oscillator is discussed in greater detail in Section 123 Timer1 Oscillator In addition to being a primary clock source the internal oscillator block is available as a powermanaged mode clock source The INTRC source is also used as the clock source for several special features such as the WDT and FailSafe Clock Monitor The clock sources for the PIC18F2420252044204520 devices are shown in Figure 28 See Section 230 Special Features of the CPU for Configuration register details FIGURE 28 PIC18F2420252044204520 CLOCK DIAGRAM 4 x PLL FOSC30 Secondary Oscillator T1OSCEN Enable Oscillator T1OSO T1OSI Clock Source Option for Other Modules OSC1 OSC2 Sleep HSPLL INTOSCPLL LP XT HS RC EC T1OSC CPU Peripherals IDLEN Postscaler MUX MUX 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 250 kHz OSCCON64 111 110 101 100 011 010 001 000 31 kHz INTRC Source Internal Oscillator Block WDT PWRT FSCM 8 MHz Internal Oscillator INTOSC OSCCON64 Clock Control OSCCON10 Source 8 MHz 31 kHz INTRC OSCTUNE6 0 1 OSCTUNE7 and TwoSpeed Startup Primary Oscillator PIC18F2420252044204520 2008 Microchip Technology Inc DS39631Epage 29 PIC18F2420252044204520 271 OSCILLATOR CONTROL REGISTER The OSCCON register Register 22 controls several aspects of the device clocks operation both in fullpower operation and in powermanaged modes The System Clock Select bits SCS10 select the clock source The available clock sources are the primary clock defined by the FOSC30 Configura tion bits the secondary clock Timer1 oscillator and the internal oscillator block The clock source changes immediately after one or more of the bits is written to following a brief clock transition interval The SCS bits are cleared on all forms of Reset The Internal Oscillator Frequency Select bits IRCF20 select the frequency output of the internal oscillator block to drive the device clock The choices are the INTRC source the INTOSC source 8 MHz or one of the frequencies derived from the INTOSC post scaler 3125 kHz to 4 MHz If the internal oscillator block is supplying the device clock changing the states of these bits will have an immediate change on the internal oscillators output On device Resets the default output frequency of the internal oscillator block is set at 1 MHz When a nominal output frequency of 31 kHz is selected IRCF20 000 users may choose which internal oscillator acts as the source This is done with the INTSRC bit in the OSCTUNE register OSCTUNE7 Setting this bit selects INTOSC as a 3125 kHz clock source by enabling the divideby256 output of the INTOSC postscaler Clearing INTSRC selects INTRC nominally 31 kHz as the clock source This option allows users to select the tunable and more precise INTOSC as a clock source while maintaining power savings with a very low clock speed Regardless of the setting of INTSRC INTRC always remains the clock source for features such as the Watchdog Timer and the FailSafe Clock Monitor The OSTS IOFS and T1RUN bits indicate which clock source is currently providing the device clock The OSTS bit indicates that the Oscillator Startup Timer OST has timed out and the primary clock is providing the device clock in primary clock modes The IOFS bit indicates when the internal oscillator block has stabi lized and is providing the device clock in RC Clock modes The T1RUN bit T1CON6 indicates when the Timer1 oscillator is providing the device clock in secondary clock modes In powermanaged modes only one of these three bits will be set at any time If none of these bits are set the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 30 PowerManaged Modes 272 OSCILLATOR TRANSITIONS PIC18F2420252044204520 devices contain circuitry to prevent clock glitches when switching between clock sources A short pause in the device clock occurs during the clock switch The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source This formula assumes that the new clock source is stable Clock transitions are discussed in greater detail in Section 312 Entering PowerManaged Modes Note 1 The Timer1 oscillator must be enabled to select the secondary clock source The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control regis ter T1CON3 If the Timer1 oscillator is not enabled then any attempt to select a secondary clock source will be ignored 2 It is recommended that the Timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts PIC18F2420252044204520 DS39631Epage 30 2008 Microchip Technology Inc REGISTER 22 OSCCON OSCILLATOR CONTROL REGISTER RW0 RW1 RW0 RW0 R1 R0 RW0 RW0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 IDLEN Idle Enable bit 1 Device enters an Idle mode on SLEEP instruction 0 Device enters Sleep mode on SLEEP instruction bit 64 IRCF20 Internal Oscillator Frequency Select bits 111 8 MHz INTOSC drives clock directly 110 4 MHz 101 2 MHz 100 1 MHz3 011 500 kHz 010 250 kHz 001 125 kHz 000 31 kHz from either INTOSC256 or INTRC directly2 bit 3 OSTS Oscillator Startup Timer Timeout Status bit1 1 Oscillator Startup Timer OST timeout has expired primary oscillator is running 0 Oscillator Startup Timer OST timeout is running primary oscillator is not ready bit 2 IOFS INTOSC Frequency Stable bit 1 INTOSC frequency is stable 0 INTOSC frequency is not stable bit 10 SCS10 System Clock Select bits 1x Internal oscillator block 01 Secondary Timer1 oscillator 00 Primary oscillator Note 1 Reset state depends on state of the IESO Configuration bit 2 Source selected by the INTSRC bit OSCTUNE7 see text 3 Default output frequency of INTOSC on Reset 2008 Microchip Technology Inc DS39631Epage 31 PIC18F2420252044204520 28 Effects of PowerManaged Modes on the Various Clock Sources When PRIIDLE mode is selected the designated pri mary oscillator continues to run without interruption For all other powermanaged modes the oscillator using the OSC1 pin is disabled The OSC1 pin and OSC2 pin if used by the oscillator will stop oscillating In secondary clock modes SECRUN and SECIDLE the Timer1 oscillator is operating and pro viding the device clock The Timer1 oscillator may also run in all powermanaged modes if required to clock Timer1 or Timer3 In internal oscillator modes RCRUN and RCIDLE the internal oscillator block provides the device clock source The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features regardless of the power managed mode see Section 232 Watchdog Timer WDT Section 233 TwoSpeed Startup and Section 234 FailSafe Clock Monitor for more information on WDT FailSafe Clock Monitor and Two Speed Startup The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler The INTOSC output is disabled if the clock is provided directly from the INTRC output If Sleep mode is selected all clock sources are stopped Since all the transistor switching currents have been stopped Sleep mode achieves the lowest current consumption of the device only leakage currents Enabling any onchip feature that will operate during Sleep will increase the current consumed during Sleep The INTRC is required to support WDT operation The Timer1 oscillator may be operating to support a Real Time Clock Other features may be operating that do not require a device clock source ie MSSP slave PSP INTx pins and others Peripherals that may add significant current consumption are listed in Section 262 DC Characteristics 29 Powerup Delays Powerup delays are controlled by two timers so that no external Reset circuitry is required for most applica tions The delays ensure that the device is kept in Reset until the device power supply is stable under nor mal circumstances and the primary clock is operating and stable For additional information on powerup delays see Section 45 Device Reset Timers The first timer is the Powerup Timer PWRT which provides a fixed delay on powerup parameter 33 Table 2610 It is enabled by clearing 0 the PWRTEN Configuration bit The second timer is the Oscillator Startup Timer OST intended to keep the chip in Reset until the crystal oscillator is stable LP XT and HS modes The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device When the HSPLL Oscillator mode is selected the device is kept in Reset for an additional 2 ms following the HS mode OST delay so the PLL can lock to the incoming clock frequency There is a delay of interval TCSD parameter 38 Table 2610 following POR while the controller becomes ready to execute instructions This delay runs concurrently with any other delays This may be the only delay that occurs when any of the EC RC or INTIO modes are used as the primary clock source TABLE 23 OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC INTIO1 Floating external resistor should pull high At logic low clock4 output RCIO Floating external resistor should pull high Configured as PORTA bit 6 INTIO2 Configured as PORTA bit 7 Configured as PORTA bit 6 ECIO Floating pulled by external clock Configured as PORTA bit 6 EC Floating pulled by external clock At logic low clock4 output LP XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note See Table 42 in Section 40 Reset for timeouts due to Sleep and MCLR Reset PIC18F2420252044204520 DS39631Epage 32 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc Advance Information DS39631Epage 33 PIC18F2420252044204520 30 POWERMANAGED MODES PIC18F2420252044204520 devices offer a total of seven operating modes for more efficient power management These modes provide a variety of options for selective power conservation in applications where resources may be limited ie batterypowered devices There are three categories of powermanaged modes Run modes Idle modes Sleep mode These categories define which portions of the device are clocked and sometimes what speed The Run and Idle modes may use any of the three available clock sources primary secondary or internal oscillator block the Sleep mode does not use a clock source The powermanaged modes include several power saving features offered on previous PIC devices One is the clock switching feature offered in other PIC18 devices allowing the controller to use the Timer1 oscillator in place of the primary oscillator Also included is the Sleep mode offered by all PIC devices where all device clocks are stopped 31 Selecting PowerManaged Modes Selecting a powermanaged mode requires two decisions if the CPU is to be clocked or not and the selection of a clock source The IDLEN bit OSCCON7 controls CPU clocking while the SCS10 bits OSCCON10 select the clock source The individual modes bit settings clock sources and affected modules are summarized in Table 31 311 CLOCK SOURCES The SCS10 bits allow the selection of one of three clock sources for powermanaged modes They are the primary clock as defined by the FOSC30 Configuration bits the secondary clock the Timer1 oscillator the internal oscillator block for RC modes 312 ENTERING POWERMANAGED MODES Switching from one powermanaged mode to another begins by loading the OSCCON register The SCS10 bits select the clock source and determine which Run or Idle mode is to be used Changing these bits causes an immediate switch to the new clock source assuming that it is running The switch may also be subject to clock transition delays These are discussed in Section 313 Clock Transitions and Status Indicators and subsequent sections Entry to the powermanaged Idle or Sleep modes is triggered by the execution of a SLEEP instruction The actual mode that results depends on the status of the IDLEN bit Depending on the current mode and the mode being switched to a change to a powermanaged mode does not always require setting all of these bits Many transitions may be done by changing the oscillator select bits or changing the IDLEN bit prior to issuing a SLEEP instruction If the IDLEN bit is already configured correctly it may only be necessary to perform a SLEEP instruction to switch to the desired mode TABLE 31 POWERMANAGED MODES Mode OSCCON710 Bits Module Clocking Available Clock and Oscillator Source IDLEN1 SCS10 CPU Peripherals Sleep 0 NA Off Off None All clocks are disabled PRIRUN NA 00 Clocked Clocked Primary LP XT HS HSPLL RC EC and Internal Oscillator Block2 This is the normal fullpower execution mode SECRUN NA 01 Clocked Clocked Secondary Timer1 Oscillator RCRUN NA 1x Clocked Clocked Internal Oscillator Block2 PRIIDLE 1 00 Off Clocked Primary LP XT HS HSPLL RC EC SECIDLE 1 01 Off Clocked Secondary Timer1 Oscillator RCIDLE 1 1x Off Clocked Internal Oscillator Block2 Note 1 IDLEN reflects its value when the SLEEP instruction is executed 2 Includes INTOSC and INTOSC postscaler as well as the INTRC source PIC18F2420252044204520 DS39631Epage 34 Advance Information 2008 Microchip Technology Inc 313 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source This formula assumes that the new clock source is stable Three bits indicate the current clock source and its status They are OSTS OSCCON3 IOFS OSCCON2 T1RUN T1CON6 In general only one of these bits will be set while in a given powermanaged mode When the OSTS bit is set the primary clock is providing the device clock When the IOFS bit is set the INTOSC output is providing a stable 8 MHz clock source to a divider that actually drives the device clock When the T1RUN bit is set the Timer1 oscillator is providing the clock If none of these bits are set then either the INTRC clock source is clocking the device or the INTOSC source is not yet stable If the internal oscillator block is configured as the primary clock source by the FOSC30 Configuration bits then both the OSTS and IOFS bits may be set when in PRIRUN or PRIIDLE modes This indicates that the primary clock INTOSC output is generating a stable 8 MHz output Entering another powermanaged RC mode at the same frequency would clear the OSTS bit 314 MULTIPLE SLEEP COMMANDS The powermanaged mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed If another SLEEP instruction is executed the device will enter the powermanaged mode specified by IDLEN at that time If IDLEN has changed the device will enter the new powermanaged mode specified by the new setting 32 Run Modes In the Run modes clocks to both the core and peripherals are active The difference between these modes is the clock source 321 PRIRUN MODE The PRIRUN mode is the normal fullpower execu tion mode of the microcontroller This is also the default mode upon a device Reset unless TwoSpeed Startup is enabled see Section 233 TwoSpeed Startup for details In this mode the OSTS bit is set The IOFS bit may be set if the internal oscillator block is the primary clock source see Section 271 Oscillator Control Register 322 SECRUN MODE The SECRUN mode is the compatible mode to the clock switching feature offered in other PIC18 devices In this mode the CPU and peripherals are clocked from the Timer1 oscillator This gives users the option of lower power consumption while still using a highaccuracy clock source SECRUN mode is entered by setting the SCS10 bits to 01 The device clock source is switched to the Timer1 oscillator see Figure 31 the primary oscilla tor is shut down the T1RUN bit T1CON6 is set and the OSTS bit is cleared On transitions from SECRUN mode to PRIRUN mode the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started When the primary clock becomes ready a clock switch back to the primary clock occurs see Figure 32 When the clock switch is complete the T1RUN bit is cleared the OSTS bit is set and the primary clock is providing the clock The IDLEN and SCS bits are not affected by the wakeup the Timer1 oscillator continues to run Note 1 Caution should be used when modifying a single IRCF bit If VDD is less than 3V it is possible to select a higher clock speed than is supported by the low VDD Improper device operation may result if the VDDFOSC specifications are violated 2 Executing a SLEEP instruction does not necessarily place the device into Sleep mode It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes depending on the setting of the IDLEN bit Note The Timer1 oscillator should already be running prior to entering SECRUN mode If the T1OSCEN bit is not set when the SCS10 bits are set to 01 entry to SECRUN mode will not occur If the Timer1 oscillator is enabled but not yet running device clocks will be delayed until the oscillator has started In such situa tions initial oscillator operation is far from stable and unpredictable operation may result 2008 Microchip Technology Inc Advance Information DS39631Epage 35 PIC18F2420252044204520 FIGURE 31 TRANSITION TIMING FOR ENTRY TO SECRUN MODE FIGURE 32 TRANSITION TIMING FROM SECRUN MODE TO PRIRUN MODE HSPLL 323 RCRUN MODE In RCRUN mode the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer In this mode the primary clock is shut down When using the INTRC source this mode provides the best power conservation of all the Run modes while still executing code It works well for user applications which are not highly timing sensitive or do not require highspeed clocks at all times If the primary clock source is the internal oscillator block either INTRC or INTOSC there are no distin guishable differences between PRIRUN and RCRUN modes during execution However a clock switch delay will occur during entry to and exit from RCRUN mode Therefore if the primary clock source is the internal oscillator block the use of RCRUN mode is not recommended This mode is entered by setting the SCS1 bit to 1 Although it is ignored it is recommended that the SCS0 bit also be cleared this is to maintain software compat ibility with future devices When the clock source is switched to the INTOSC multiplexer see Figure 33 the primary oscillator is shut down and the OSTS bit is cleared The IRCF bits may be modified at any time to immediately change the clock speed Q3 Q4 Q2 OSC1 Peripheral Program Q1 T1OSI Q1 Counter Clock CPU Clock PC 2 PC 1 2 3 n1 n Clock Transition1 Q4 Q3 Q2 Q1 Q3 Q2 PC 4 Note 1 Clock transition typically occurs within 24 TOSC Q1 Q3 Q4 OSC1 Peripheral Program PC T1OSI PLL Clock Q1 PC 4 Q2 Output Q3 Q4 Q1 CPU Clock PC 2 Clock Counter Q2 Q2 Q3 Note1 TOST 1024 TOSC TPLL 2 ms approx These intervals are not shown to scale 2 Clock transition typically occurs within 24 TOSC SCS10 bits Changed TPLL1 1 2 n1 n Clock OSTS bit Set Transition2 TOST1 Note Caution should be used when modifying a single IRCF bit If VDD is less than 3V it is possible to select a higher clock speed than is supported by the low VDD Improper device operation may result if the VDDFOSC specifications are violated PIC18F2420252044204520 DS39631Epage 36 Advance Information 2008 Microchip Technology Inc If the IRCF bits and the INTSRC bit are all clear the INTOSC output is not enabled and the IOFS bit will remain clear there will be no indication of the current clock source The INTRC source is providing the device clocks If the IRCF bits are changed from all clear thus enabling the INTOSC output or if INTSRC is set the IOFS bit becomes set after the INTOSC output becomes stable Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST If the IRCF bits were previously at a nonzero value or if INTSRC was set before setting SCS1 and the INTOSC source was already stable the IOFS bit will remain set On transitions from RCRUN mode to PRIRUN mode the device continues to be clocked from the INTOSC multiplexer while the primary clock is started When the primary clock becomes ready a clock switch to the pri mary clock occurs see Figure 34 When the clock switch is complete the IOFS bit is cleared the OSTS bit is set and the primary clock is providing the device clock The IDLEN and SCS bits are not affected by the switch The INTRC source will continue to run if either the WDT or the FailSafe Clock Monitor is enabled FIGURE 33 TRANSITION TIMING TO RCRUN MODE FIGURE 34 TRANSITION TIMING FROM RCRUN MODE TO PRIRUN MODE Q3 Q4 Q2 OSC1 Peripheral Program Q1 INTRC Q1 Counter Clock CPU Clock PC 2 PC 1 2 3 n1 n Clock Transition1 Q4 Q3 Q2 Q1 Q3 Q2 PC 4 Note 1 Clock transition typically occurs within 24 TOSC Q1 Q3 Q4 OSC1 Peripheral Program PC INTOSC PLL Clock Q1 PC 4 Q2 Output Q3 Q4 Q1 CPU Clock PC 2 Clock Counter Q2 Q2 Q3 Note1 TOST 1024 TOSC TPLL 2 ms approx These intervals are not shown to scale 2 Clock transition typically occurs within 24 TOSC SCS10 bits Changed TPLL1 1 2 n1 n Clock OSTS bit Set Transition2 Multiplexer TOST1 2008 Microchip Technology Inc Advance Information DS39631Epage 37 PIC18F2420252044204520 33 Sleep Mode The powermanaged Sleep mode in the PIC18F2420 252044204520 devices is identical to the legacy Sleep mode offered in all other PIC devices It is entered by clearing the IDLEN bit the default state on device Reset and executing the SLEEP instruction This shuts down the selected oscillator Figure 35 All clock source status bits are cleared Entering the Sleep mode from any other mode does not require a clock switch This is because no clocks are needed once the controller has entered Sleep If the WDT is selected the INTRC source will continue to operate If the Timer1 oscillator is enabled it will also continue to run When a wake event occurs in Sleep mode by interrupt Reset or WDT timeout the device will not be clocked until the clock source selected by the SCS10 bits becomes ready see Figure 36 or it will be clocked from the internal oscillator block if either the TwoSpeed Startup or the FailSafe Clock Monitor are enabled see Section 230 Special Features of the CPU In either case the OSTS bit is set when the primary clock is providing the device clocks The IDLEN and SCS bits are not affected by the wakeup 34 Idle Modes The Idle modes allow the controllers CPU to be selectively shut down while the peripherals continue to operate Selecting a particular Idle mode allows users to further manage power consumption If the IDLEN bit is set to 1 when a SLEEP instruction is executed the peripherals will be clocked from the clock source selected using the SCS10 bits however the CPU will not be clocked The clock source status bits are not affected Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode If the WDT is selected the INTRC source will continue to operate If the Timer1 oscillator is enabled it will also continue to run Since the CPU is not executing instructions the only exits from any of the Idle modes are by interrupt WDT timeout or a Reset When a wake event occurs CPU execution is delayed by an interval of TCSD parameter 38 Table 2610 while it becomes ready to execute code When the CPU begins executing code it resumes with the same clock source for the current Idle mode For example when waking from RCIDLE mode the internal oscillator block will clock the CPU and peripherals in other words RCRUN mode The IDLEN and SCS bits are not affected by the wakeup While in any Idle mode or the Sleep mode a WDT timeout will result in a WDT wakeup to the Run mode currently specified by the SCS1SCS0 bits FIGURE 35 TRANSITION TIMING FOR ENTRY TO SLEEP MODE FIGURE 36 TRANSITION TIMING FOR WAKE FROM SLEEP HSPLL Q3 Q4 Q2 OSC1 Peripheral Sleep Program Q1 Q1 Counter Clock CPU Clock PC 2 PC Q3 Q4 Q1 Q2 OSC1 Peripheral Program PC PLL Clock Q3 Q4 Output CPU Clock Q1 Q2 Q3 Q4 Q1 Q2 Clock Counter PC 6 PC 4 Q1 Q2 Q3 Q4 Wake Event Note1 TOST 1024 TOSC TPLL 2 ms approx These intervals are not shown to scale TOST1 TPLL1 OSTS bit Set PC 2 PIC18F2420252044204520 DS39631Epage 38 Advance Information 2008 Microchip Technology Inc 341 PRIIDLE MODE This mode is unique among the three lowpower Idle modes in that it does not disable the primary device clock For timingsensitive applications this allows for the fastest resumption of device operation with its more accurate primary clock source since the clock source does not have to warmup or transition from another oscillator PRIIDLE mode is entered from PRIRUN mode by setting the IDLEN bit and executing a SLEEP instruc tion If the device is in another Run mode set IDLEN first then clear the SCS bits and execute SLEEP Although the CPU is disabled the peripherals continue to be clocked from the primary clock source specified by the FOSC30 Configuration bits The OSTS bit remains set see Figure 37 When a wake event occurs the CPU is clocked from the primary clock source A delay of interval TCSD is required between the wake event and when code execution starts This is required to allow the CPU to become ready to execute instructions After the wake up the OSTS bit remains set The IDLEN and SCS bits are not affected by the wakeup see Figure 38 342 SECIDLE MODE In SECIDLE mode the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator This mode is entered from SECRUN by setting the IDLEN bit and executing a SLEEP instruc tion If the device is in another Run mode set the IDLEN bit first then set the SCS10 bits to 01 and execute SLEEP When the clock source is switched to the Timer1 oscillator the primary oscillator is shut down the OSTS bit is cleared and the T1RUN bit is set When a wake event occurs the peripherals continue to be clocked from the Timer1 oscillator After an interval of TCSD following the wake event the CPU begins exe cuting code being clocked by the Timer1 oscillator The IDLEN and SCS bits are not affected by the wakeup the Timer1 oscillator continues to run see Figure 38 FIGURE 37 TRANSITION TIMING FOR ENTRY TO IDLE MODE FIGURE 38 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Note The Timer1 oscillator should already be running prior to entering SECIDLE mode If the T1OSCEN bit is not set when the SLEEP instruction is executed the SLEEP instruction will be ignored and entry to SECIDLE mode will not occur If the Timer1 oscillator is enabled but not yet running peripheral clocks will be delayed until the oscillator has started In such situations initial oscillator operation is far from stable and unpredictable operation may result Q1 Peripheral Program PC PC 2 OSC1 Q3 Q4 Q1 CPU Clock Clock Counter Q2 OSC1 Peripheral Program PC CPU Clock Q1 Q3 Q4 Clock Counter Q2 Wake Event TCSD 2008 Microchip Technology Inc Advance Information DS39631Epage 39 PIC18F2420252044204520 343 RCIDLE MODE In RCIDLE mode the CPU is disabled but the periph erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer This mode allows for controllable power conservation during Idle periods From RCRUN this mode is entered by setting the IDLEN bit and executing a SLEEP instruction If the device is in another Run mode first set IDLEN then set the SCS1 bit and execute SLEEP Although its value is ignored it is recommended that SCS0 also be cleared this is to maintain software compatibility with future devices The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction When the clock source is switched to the INTOSC multiplexer the primary oscillator is shut down and the OSTS bit is cleared If the IRCF bits are set to any nonzero value or the INTSRC bit is set the INTOSC output is enabled The IOFS bit becomes set after the INTOSC output becomes stable after an interval of TIOBST parameter 39 Table 2610 Clocks to the peripherals continue while the INTOSC source stabilizes If the IRCF bits were previously at a nonzero value or INTSRC was set before the SLEEP instruction was exe cuted and the INTOSC source was already stable the IOFS bit will remain set If the IRCF bits and INTSRC are all clear the INTOSC output will not be enabled the IOFS bit will remain clear and there will be no indication of the current clock source When a wake event occurs the peripherals continue to be clocked from the INTOSC multiplexer After a delay of TCSD following the wake event the CPU begins executing code being clocked by the INTOSC multi plexer The IDLEN and SCS bits are not affected by the wakeup The INTRC source will continue to run if either the WDT or the FailSafe Clock Monitor is enabled 35 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt a Reset or a WDT timeout This section discusses the triggers that cause exits from powermanaged modes The clocking subsystem actions are discussed in each of the powermanaged modes see Section 32 Run Modes Section 33 Sleep Mode and Section 34 Idle Modes 351 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode To enable this functionality an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers The exit sequence is initiated when the corresponding interrupt flag bit is set On all exits from Idle or Sleep modes by interrupt code execution branches to the interrupt vector if the GIE GIEH bit INTCON7 is set Otherwise code execu tion continues or resumes without branching see Section 90 Interrupts A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes This delay is required for the CPU to prepare for execution Instruction execution resumes on the first clock cycle following this delay 352 EXIT BY WDT TIMEOUT A WDT timeout will cause different actions depending on which powermanaged mode the device is in when the timeout occurs If the device is not executing code all Idle modes and Sleep mode the timeout will result in an exit from the powermanaged mode see Section 32 Run Modes and Section 33 Sleep Mode If the device is executing code all Run modes the timeout will result in a WDT Reset see Section 232 Watchdog Timer WDT The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction the loss of a currently selected clock source if the FailSafe Clock Monitor is enabled and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source 353 EXIT BY RESET Normally the device is held in Reset by the Oscillator Startup Timer OST until the primary clock becomes ready At that time the OSTS bit is set and the device begins executing code If the internal oscillator block is the new clock source the IOFS bit is set instead The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wakeup and the type of oscillator if the new clock source is the primary clock Exit delays are summarized in Table 32 Code execution can begin before the primary clock becomes ready If either the TwoSpeed Startup see Section 233 TwoSpeed Startup or FailSafe Clock Monitor see Section 234 FailSafe Clock Monitor is enabled the device may begin execution as soon as the Reset source has cleared Execution is clocked by the INTOSC multiplexer driven by the inter nal oscillator block Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a powermanaged mode is entered before the primary clock becomes ready the primary clock is then shut down PIC18F2420252044204520 DS39631Epage 40 Advance Information 2008 Microchip Technology Inc 354 EXIT WITHOUT AN OSCILLATOR STARTUP DELAY Certain exits from powermanaged modes do not invoke the OST at all There are two cases PRIIDLE mode where the primary clock source is not stopped and the primary clock source is not any of the LP XT HS or HSPLL modes In these instances the primary clock source either does not require an oscillator startup delay since it is already running PRIIDLE or normally does not require an oscillator startup delay RC EC and INTIO Oscillator modes However a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution Instruction execution resumes on the first clock cycle following this delay TABLE 32 EXIT DELAY ON WAKEUP BY RESET FROM SLEEP MODE OR ANY IDLE MODE BY CLOCK SOURCES Clock Source Before Wakeup Clock Source After Wakeup Exit Delay Clock Ready Status Bit OSCCON Primary Device Clock PRIIDLE mode LP XT HS TCSD1 OSTS HSPLL EC RC INTOSC2 IOFS T1OSC or INTRC1 LP XT HS TOST3 OSTS HSPLL TOST trc 3 EC RC TCSD1 INTOSC2 TCSD1 IOFS INTOSC2 LP XT HS TOST3 OSTS HSPLL TOST trc 3 EC RC TCSD1 INTOSC2 TCSD1 IOFS None Sleep mode LP XT HS TOST3 OSTS HSPLL TOST trc 3 EC RC TCSD1 INTOSC2 TCSD1 IOFS Note 1 TCSD parameter 38 is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays see Section 34 Idle Modes On Reset INTOSC defaults to 1 MHz 2 Includes both the INTOSC 8 MHz source and postscaler derived frequencies 3 TOST is the Oscillator Startup Timer parameter 32 trc is the PLL lockout timer parameter F12 it is also designated as TPLL 2008 Microchip Technology Inc DS39631Epage 41 PIC18F2420252044204520 40 RESET The PIC18F2420252044204520 devices differentiate between various kinds of Reset a Poweron Reset POR b MCLR Reset during normal operation c MCLR Reset during powermanaged modes d Watchdog Timer WDT Reset during execution e Programmable Brownout Reset BOR f RESET Instruction g Stack Full Reset h Stack Underflow Reset This section discusses Resets generated by MCLR POR and BOR and covers the operation of the various startup timers Stack Reset events are covered in Section 5124 Stack Full and Underflow Resets WDT Resets are covered in Section 232 Watchdog Timer WDT A simplified block diagram of the OnChip Reset Circuit is shown in Figure 41 41 RCON Register Device Reset events are tracked through the RCON register Register 41 The lower five bits of the regis ter indicate that a specific Reset event has occurred In most cases these bits can only be cleared by the event and must be set by the application after the event The state of these flag bits taken together can be read to indicate the type of Reset that just occurred This is described in more detail in Section 46 Reset State of Registers The RCON register also has control bits for setting interrupt priority IPEN and software control of the BOR SBOREN Interrupt priority is discussed in Section 90 Interrupts BOR is covered in Section 44 Brownout Reset BOR FIGURE 41 SIMPLIFIED BLOCK DIAGRAM OF ONCHIP RESET CIRCUIT External Reset MCLR VDD OSC1 WDT Timeout VDD Rise Detect OSTPWRT INTRC1 POR Pulse OST 10Bit Ripple Counter PWRT 11Bit Ripple Counter Enable OST2 Enable PWRT Note 1 This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin 2 See Table 42 for timeout situations Brownout Reset BOREN RESET Instruction Stack Pointer Stack FullUnderflow Reset Sleep IDLE 1024 Cycles 655 ms 32 μs MCLRE S R Q ChipReset PIC18F2420252044204520 DS39631Epage 42 2008 Microchip Technology Inc REGISTER 41 RCON RESET CONTROL REGISTER RW0 RW11 U0 RW1 R1 R1 RW02 RW0 IPEN SBOREN RI TO PD POR BOR bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 IPEN Interrupt Priority Enable bit 1 Enable priority levels on interrupts 0 Disable priority levels on interrupts PIC16CXXX Compatibility mode bit 6 SBOREN BOR Software Enable bit1 If BOREN1BOREN0 01 1 BOR is enabled 0 BOR is disabled If BOREN1BOREN0 00 10 or 11 Bit is disabled and read as 0 bit 5 Unimplemented Read as 0 bit 4 RI RESET Instruction Flag bit 1 The RESET instruction was not executed set by firmware only 0 The RESET instruction was executed causing a device Reset must be set in software after a Brownout Reset occurs bit 3 TO Watchdog Timeout Flag bit 1 Set by powerup CLRWDT instruction or SLEEP instruction 0 A WDT timeout occurred bit 2 PD PowerDown Detection Flag bit 1 Set by powerup or by the CLRWDT instruction 0 Set by execution of the SLEEP instruction bit 1 POR Poweron Reset Status bit 1 A Poweron Reset has not occurred set by firmware only 0 A Poweron Reset occurred must be set in software after a Poweron Reset occurs bit 0 BOR Brownout Reset Status bit 1 A Brownout Reset has not occurred set by firmware only 0 A Brownout Reset occurred must be set in software after a Brownout Reset occurs Note 1 If SBOREN is enabled its Reset state is 1 otherwise it is 0 2 The actual Reset value of POR is determined by the type of device Reset See the notes following this register and Section 46 Reset State of Registers for additional information Note 1 It is recommended that the POR bit be set after a Poweron Reset has been detected so that subsequent Poweron Resets may be detected 2 Brownout Reset is said to have occurred when BOR is 0 and POR is 1 assuming that POR was set to 1 by software immediately after a Poweron Reset 2008 Microchip Technology Inc DS39631Epage 43 PIC18F2420252044204520 42 Master Clear MCLR The MCLR pin provides a method for triggering an external Reset of the device A Reset is generated by holding the pin low These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses The MCLR pin is not driven low by any internal Resets including the WDT In PIC18F2420252044204520 devices the MCLR input can be disabled with the MCLRE Configuration bit When MCLR is disabled the pin becomes a digital input See Section 105 PORTE TRISE and LATE Registers for more information 43 Poweron Reset POR A Poweron Reset pulse is generated onchip whenever VDD rises above a certain threshold This allows the device to start in the initialized state when VDD is adequate for operation To take advantage of the POR circuitry tie the MCLR pin through a resistor 1 kΩ to 10 kΩ to VDD This will eliminate external RC components usually needed to create a Poweron Reset delay A minimum rise rate for VDD is specified parameter D004 For a slow rise time see Figure 42 When the device starts normal operation ie exits the Reset condition device operating parameters volt age frequency temperature etc must be met to ensure operation If these conditions are not met the device must be held in Reset until the operating conditions are met POR events are captured by the POR bit RCON1 The state of the bit is set to 0 whenever a POR occurs it does not change for any other Reset event POR is not reset to 1 by any hardware event To capture multiple events the user manually resets the bit to 1 in software following any POR FIGURE 42 EXTERNAL POWERON RESET CIRCUIT FOR SLOW VDD POWERUP Note 1 External Poweron Reset circuit is required only if the VDD powerup slope is too slow The diode D helps discharge the capacitor quickly when VDD powers down 2 R 40 kΩ is recommended to make sure that the voltage drop across R does not violate the devices electrical specification 3 R1 1 kΩ will limit any current flowing into MCLR from external capacitor C in the event of MCLRVPP pin breakdown due to Electrostatic Discharge ESD or Electrical Overstress EOS C R1 R D VDD MCLR PIC18FXXXX VDD PIC18F2420252044204520 DS39631Epage 44 2008 Microchip Technology Inc 44 Brownout Reset BOR PIC18F2420252044204520 devices implement a BOR circuit that provides the user with a number of configuration and powersaving options The BOR is controlled by the BORV10 and BOREN10 Configuration bits There are a total of four BOR configurations which are summarized in Table 41 The BOR threshold is set by the BORV10 bits If BOR is enabled any values of BOREN10 except 00 any drop of VDD below VBOR parameter D005 for greater than TBOR parameter 35 will reset the device A Reset may or may not occur if VDD falls below VBOR for less than TBOR The chip will remain in Brownout Reset until VDD rises above VBOR If the Powerup Timer is enabled it will be invoked after VDD rises above VBOR it then will keep the chip in Reset for an additional time delay TPWRT parameter 33 If VDD drops below VBOR while the Powerup Timer is running the chip will go back into a Brownout Reset and the Powerup Timer will be initialized Once VDD rises above VBOR the Powerup Timer will execute the additional time delay BOR and the Powerup Timer PWRT are independently configured Enabling the Brownout Reset does not automatically enable the PWRT 441 SOFTWARE ENABLED BOR When BOREN10 01 the BOR can be enabled or disabled by the user in software This is done with the control bit SBOREN RCON6 Setting SBOREN enables the BOR to function as previously described Clearing SBOREN disables the BOR entirely The SBOREN bit operates only in this mode otherwise it is read as 0 Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration It also allows the user to tailor device power consumption in software by elimi nating the incremental current that the BOR consumes While the BOR current is typically very small it may have some impact in lowpower applications 442 DETECTING BOR When BOR is enabled the BOR bit always resets to 0 on any BOR or POR event This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone A more reliable method is to simultaneously check the state of both POR and BOR This assumes that the POR bit is reset to 1 in software immediately after any POR event If BOR is 0 while POR is 1 it can be reliably assumed that a BOR event has occurred 443 DISABLING BOR IN SLEEP MODE When BOREN10 10 the BOR remains under hardware control and operates as previously described Whenever the device enters Sleep mode however the BOR is automatically disabled When the device returns to any other operating mode BOR is automatically reenabled This mode allows for applications to recover from brownout situations while actively executing code when the device requires BOR protection the most At the same time it saves additional power in Sleep mode by eliminating the small incremental BOR current TABLE 41 BOR CONFIGURATIONS Note Even when BOR is under software control the Brownout Reset voltage level is still set by the BORV10 Configuration bits it cannot be changed in software BOR Configuration Status of SBOREN RCON6 BOR Operation BOREN1 BOREN0 0 0 Unavailable BOR disabled must be enabled by reprogramming the Configuration bits 0 1 Available BOR enabled in software operation controlled by SBOREN 1 0 Unavailable BOR enabled in hardware in Run and Idle modes disabled during Sleep mode 1 1 Unavailable BOR enabled in hardware must be disabled by reprogramming the Configuration bits 2008 Microchip Technology Inc DS39631Epage 45 PIC18F2420252044204520 45 Device Reset Timers PIC18F2420252044204520 devices incorporate three separate onchip timers that help regulate the Poweron Reset process Their main function is to ensure that the device clock is stable before code is executed These timers are Powerup Timer PWRT Oscillator Startup Timer OST PLL Lock Timeout 451 POWERUP TIMER PWRT The Powerup Timer PWRT of PIC18F24202520 44204520 devices is an 11bit counter which uses the INTRC source as the clock input This yields an approximate time interval of 2048 x 32 μs 656 ms While the PWRT is counting the device is held in Reset The powerup time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation See DC parameter 33 for details The PWRT is enabled by clearing the PWRTEN Configuration bit 452 OSCILLATOR STARTUP TIMER OST The Oscillator Startup Timer OST provides a 1024 oscillator cycle from OSC1 input delay after the PWRT delay is over parameter 33 This ensures that the crystal oscillator or resonator has started and stabilized The OST timeout is invoked only for XT LP HS and HSPLL modes and only on Poweron Reset or on exit from most powermanaged modes 453 PLL LOCK TIMEOUT With the PLL enabled in its PLL mode the timeout sequence following a Poweron Reset is slightly differ ent from other oscillator modes A separate timer is used to provide a fixed timeout that is sufficient for the PLL to lock to the main oscillator frequency This PLL lock timeout TPLL is typically 2 ms and follows the oscillator startup timeout 454 TIMEOUT SEQUENCE On powerup the timeout sequence is as follows 1 After the POR pulse has cleared PWRT timeout is invoked if enabled 2 Then the OST is activated The total timeout will vary based on oscillator configu ration and the status of the PWRT Figure 43 Figure 44 Figure 45 Figure 46 and Figure 47 all depict timeout sequences on powerup with the Powerup Timer enabled and the device operating in HS Oscillator mode Figure 43 through Figure 46 also apply to devices operating in XT or LP modes For devices in RC mode and with the PWRT disabled on the other hand there will be no timeout at all Since the timeouts occur from the POR pulse if MCLR is kept low long enough all timeouts will expire Bring ing MCLR high will begin execution immediately Figure 45 This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel TABLE 42 TIMEOUT IN VARIOUS SITUATIONS Oscillator Configuration Powerup2 and Brownout Exit from PowerManaged Mode PWRTEN 0 PWRTEN 1 HSPLL 66 ms1 1024 TOSC 2 ms2 1024 TOSC 2 ms2 1024 TOSC 2 ms2 HS XT LP 66 ms1 1024 TOSC 1024 TOSC 1024 TOSC EC ECIO 66 ms1 RC RCIO 66 ms1 INTIO1 INTIO2 66 ms1 Note 1 66 ms 655 ms is the nominal Powerup Timer PWRT delay 2 2 ms is the nominal time required for the PLL to lock PIC18F2420252044204520 DS39631Epage 46 2008 Microchip Technology Inc FIGURE 43 TIMEOUT SEQUENCE ON POWERUP MCLR TIED TO VDD VDD RISE TPWRT FIGURE 44 TIMEOUT SEQUENCE ON POWERUP MCLR NOT TIED TO VDD CASE 1 FIGURE 45 TIMEOUT SEQUENCE ON POWERUP MCLR NOT TIED TO VDD CASE 2 TPWRT TOST VDD MCLR INTERNAL POR PWRT TIMEOUT OST TIMEOUT INTERNAL RESET TPWRT TOST VDD MCLR INTERNAL POR PWRT TIMEOUT OST TIMEOUT INTERNAL RESET VDD MCLR INTERNAL POR PWRT TIMEOUT OST TIMEOUT INTERNAL RESET TPWRT TOST 2008 Microchip Technology Inc DS39631Epage 47 PIC18F2420252044204520 FIGURE 46 SLOW RISE TIME MCLR TIED TO VDD VDD RISE TPWRT FIGURE 47 TIMEOUT SEQUENCE ON POR WPLL ENABLED MCLR TIED TO VDD VDD MCLR INTERNAL POR PWRT TIMEOUT OST TIMEOUT INTERNAL RESET 0V 5V TPWRT TOST TPWRT TOST VDD MCLR INTERNAL POR PWRT TIMEOUT OST TIMEOUT INTERNAL RESET PLL TIMEOUT TPLL Note TOST 1024 clock cycles TPLL 2 ms max First three stages of the PWRT timer PIC18F2420252044204520 DS39631Epage 48 2008 Microchip Technology Inc 46 Reset State of Registers Most registers are unaffected by a Reset Their status is unknown on POR and unchanged by all other Resets The other registers are forced to a Reset state depending on the type of Reset that occurred Most registers are not affected by a WDT wakeup since this is viewed as the resumption of normal oper ation Status bits from the RCON register RI TO PD POR and BOR are set or cleared differently in different Reset situations as indicated in Table 43 These bits are used in software to determine the nature of the Reset Table 44 describes the Reset states for all of the Special Function Registers These are categorized by Poweron and Brownout Resets Master Clear and WDT Resets and WDT wakeups TABLE 43 STATUS BITS THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition Program Counter RCON Register STKPTR Register RI TO PD POR BOR STKFUL STKUNF Poweron Reset 0000h 1 1 1 0 0 0 0 RESET Instruction 0000h 0 u u u u u u Brownout Reset 0000h 1 1 1 u 0 u u MCLR Reset during PowerManaged Run Modes 0000h u 1 u u u u u MCLR Reset during PowerManaged Idle Modes and Sleep Mode 0000h u 1 0 u u u u WDT Timeout during Full Power or PowerManaged Run Mode 0000h u 0 u u u u u MCLR Reset during FullPower Execution 0000h u u u u u u u Stack Full Reset STVREN 1 0000h u u u u u 1 u Stack Underflow Reset STVREN 1 0000h u u u u u u 1 Stack Underflow Error not an actual Reset STVREN 0 0000h u u u u u u 1 WDT Timeout during PowerManaged Idle or Sleep Modes PC 2 u 0 0 u u u u Interrupt Exit from PowerManaged Modes PC 21 u u 0 u u u u Legend u unchanged Note 1 When the wakeup is due to an interrupt and the GIEH or GIEL bits are set the PC is loaded with the interrupt vector 008h or 0018h 2008 Microchip Technology Inc DS39631Epage 49 PIC18F2420252044204520 TABLE 44 INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Poweron Reset Brownout Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wakeup via WDT or Interrupt TOSU 2420 2520 4420 4520 0 0000 0 0000 0 uuuu3 TOSH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu3 TOSL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu3 STKPTR 2420 2520 4420 4520 000 0000 uu0 0000 uuu uuuu3 PCLATU 2420 2520 4420 4520 0 0000 0 0000 u uuuu PCLATH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PCL 2420 2520 4420 4520 0000 0000 0000 0000 PC 22 TBLPTRU 2420 2520 4420 4520 00 0000 00 0000 uu uuuu TBLPTRH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TABLAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PRODH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2420 2520 4420 4520 0000 000x 0000 000u uuuu uuuu1 INTCON2 2420 2520 4420 4520 1111 11 1111 11 uuuu uu1 INTCON3 2420 2520 4420 4520 110 000 110 000 uuu uuu1 INDF0 2420 2520 4420 4520 NA NA NA POSTINC0 2420 2520 4420 4520 NA NA NA POSTDEC0 2420 2520 4420 4520 NA NA NA PREINC0 2420 2520 4420 4520 NA NA NA PLUSW0 2420 2520 4420 4520 NA NA NA FSR0H 2420 2520 4420 4520 0000 0000 uuuu FSR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2420 2520 4420 4520 NA NA NA POSTINC1 2420 2520 4420 4520 NA NA NA POSTDEC1 2420 2520 4420 4520 NA NA NA PREINC1 2420 2520 4420 4520 NA NA NA PLUSW1 2420 2520 4420 4520 NA NA NA Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 One or more bits in the INTCONx or PIRx registers will be affected to cause wakeup 2 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 3 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 4 See Table 43 for Reset value for specific condition 5 Bits 6 and 7 of PORTA LATA and TRISA are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 6 The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit CONFIG3H1 When PBADEN 1 PCFG20 000 when PBADEN 0 PCFG20 111 PIC18F2420252044204520 DS39631Epage 50 2008 Microchip Technology Inc FSR1H 2420 2520 4420 4520 0000 0000 uuuu FSR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2420 2520 4420 4520 0000 0000 uuuu INDF2 2420 2520 4420 4520 NA NA NA POSTINC2 2420 2520 4420 4520 NA NA NA POSTDEC2 2420 2520 4420 4520 NA NA NA PREINC2 2420 2520 4420 4520 NA NA NA PLUSW2 2420 2520 4420 4520 NA NA NA FSR2H 2420 2520 4420 4520 0000 0000 uuuu FSR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2420 2520 4420 4520 x xxxx u uuuu u uuuu TMR0H 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TMR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu OSCCON 2420 2520 4420 4520 0100 q000 0100 q000 uuuu quuu HLVDCON 2420 2520 4420 4520 000 0101 000 0101 uuu uuuu WDTCON 2420 2520 4420 4520 0 0 u RCON4 2420 2520 4420 4520 0q1 11q0 0qq qquu uqu qquu TMR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2420 2520 4420 4520 0000 0000 u0uu uuuu uuuu uuuu TMR2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PR2 2420 2520 4420 4520 1111 1111 1111 1111 1111 1111 T2CON 2420 2520 4420 4520 000 0000 000 0000 uuu uuuu SSPBUF 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPCON1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPCON2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TABLE 44 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED Register Applicable Devices Poweron Reset Brownout Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wakeup via WDT or Interrupt Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 One or more bits in the INTCONx or PIRx registers will be affected to cause wakeup 2 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 3 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 4 See Table 43 for Reset value for specific condition 5 Bits 6 and 7 of PORTA LATA and TRISA are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 6 The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit CONFIG3H1 When PBADEN 1 PCFG20 000 when PBADEN 0 PCFG20 111 2008 Microchip Technology Inc DS39631Epage 51 PIC18F2420252044204520 ADRESH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2420 2520 4420 4520 00 0000 00 0000 uu uuuu ADCON1 2420 2520 4420 4520 00 0qqq6 00 0qqq6 uu uuuu ADCON2 2420 2520 4420 4520 000 0000 000 0000 uuu uuuu CCPR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 00 0000 00 0000 uu uuuu CCPR2H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2420 2520 4420 4520 00 0000 00 0000 uu uuuu BAUDCON 2420 2520 4420 4520 0100 000 0100 000 uuuu uuu PWM1CON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 0000 00 0000 00 uuuu uu CVRCON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu CMCON 2420 2520 4420 4520 0000 0111 0000 0111 uuuu uuuu TMR3H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2420 2520 4420 4520 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SPBRG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu RCREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TXREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TXSTA 2420 2520 4420 4520 0000 0010 0000 0010 uuuu uuuu RCSTA 2420 2520 4420 4520 0000 000x 0000 000x uuuu uuuu EEADR 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu EEDATA 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu EECON2 2420 2520 4420 4520 0000 0000 0000 0000 0000 0000 EECON1 2420 2520 4420 4520 xx0 x000 uu0 u000 uu0 u000 TABLE 44 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED Register Applicable Devices Poweron Reset Brownout Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wakeup via WDT or Interrupt Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 One or more bits in the INTCONx or PIRx registers will be affected to cause wakeup 2 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 3 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 4 See Table 43 for Reset value for specific condition 5 Bits 6 and 7 of PORTA LATA and TRISA are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 6 The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit CONFIG3H1 When PBADEN 1 PCFG20 000 when PBADEN 0 PCFG20 111 PIC18F2420252044204520 DS39631Epage 52 2008 Microchip Technology Inc IPR2 2420 2520 4420 4520 111 1111 111 1111 uuu uuuu PIR2 2420 2520 4420 4520 000 0000 000 0000 uuu uuuu1 PIE2 2420 2520 4420 4520 000 0000 000 0000 uuu uuuu IPR1 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu 2420 2520 4420 4520 111 1111 111 1111 uuu uuuu PIR1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu1 2420 2520 4420 4520 000 0000 000 0000 uuu uuuu1 PIE1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 000 0000 000 0000 uuu uuuu OSCTUNE 2420 2520 4420 4520 000 0000 000 0000 uuu uuuu TRISE 2420 2520 4420 4520 0000 111 0000 111 uuuu uuu TRISD 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISC 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISB 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISA5 2420 2520 4420 4520 1111 11115 1111 11115 uuuu uuuu5 LATE 2420 2520 4420 4520 xxx uuu uuu LATD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATA5 2420 2520 4420 4520 xxxx xxxx5 uuuu uuuu5 uuuu uuuu5 PORTE 2420 2520 4420 4520 xxxx uuuu uuuu PORTD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTA5 2420 2520 4420 4520 xx0x 00005 uu0u 00005 uuuu uuuu5 TABLE 44 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED Register Applicable Devices Poweron Reset Brownout Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wakeup via WDT or Interrupt Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 One or more bits in the INTCONx or PIRx registers will be affected to cause wakeup 2 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 3 When the wakeup is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 4 See Table 43 for Reset value for specific condition 5 Bits 6 and 7 of PORTA LATA and TRISA are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 6 The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit CONFIG3H1 When PBADEN 1 PCFG20 000 when PBADEN 0 PCFG20 111 2008 Microchip Technology Inc DS39631Epage 53 PIC18F2420252044204520 50 MEMORY ORGANIZATION There are three types of memory in PIC18 enhanced microcontroller devices Program Memory Data RAM Data EEPROM As Harvard architecture devices the data and program memories use separate busses this allows for concur rent access of the two memory spaces The data EEPROM for practical purposes can be regarded as a peripheral device since it is addressed and accessed through a set of control registers Additional detailed information on the operation of the Flash program memory is provided in Section 60 Flash Program Memory Data EEPROM is discussed separately in Section 70 Data EEPROM Memory 51 Program Memory Organization PIC18 microcontrollers implement a 21bit program counter which is capable of addressing a 2Mbyte program memory space Accessing a location between the upper boundary of the physically implemented memory and the 2Mbyte address will return all 0s a NOP instruction The PIC18F2420 and PIC18F4420 each have 16 Kbytes of Flash memory and can store up to 8192 singleword instructions The PIC18F2520 and PIC18F4520 each have 32 Kbytes of Flash memory and can store up to 16384 singleword instructions PIC18 devices have two interrupt vectors The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h The program memory map for PIC18F24202520 44204520 devices is shown in Figure 51 FIGURE 51 PROGRAM MEMORY MAP AND STACK FOR PIC18F2420252044204520 DEVICES PC200 Stack Level 1 Stack Level 31 Reset Vector LowPriority Interrupt Vector CALLRCALLRETURN RETFIERETLW 21 0000h 0018h OnChip Program Memory HighPriority Interrupt Vector 0008h User Memory Space 1FFFFFh 4000h 3FFFh Read 0 200000h 8000h 7FFFh OnChip Program Memory Read 0 PIC18F24204420 PIC18F25204520 PIC18F2420252044204520 DS39631Epage 54 2008 Microchip Technology Inc 511 PROGRAM COUNTER The Program Counter PC specifies the address of the instruction to fetch for execution The PC is 21 bits wide and is contained in three separate 8bit registers The low byte known as the PCL register is both readable and writable The high byte or PCH register contains the PC158 bits it is not directly readable or writable Updates to the PCH register are performed through the PCLATH register The upper byte is called PCU This register contains the PC2016 bits it is also not directly readable or writable Updates to the PCU register are performed through the PCLATU register The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL Similarly the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL This is useful for computed offsets to the PC see Section 5141 Computed GOTO The PC addresses bytes in the program memory To prevent the PC from becoming misaligned with word instructions the Least Significant bit of PCL is fixed to a value of 0 The PC increments by 2 to address sequential instructions in the program memory The CALL RCALL GOTO and program branch instructions write to the program counter directly For these instructions the contents of PCLATH and PCLATU are not transferred to the program counter 512 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur The PC is pushed onto the stack when a CALL or RCALL instruc tion is executed or an interrupt is Acknowledged The PC value is pulled off the stack on a RETURN RETLW or a RETFIE instruction PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions The stack operates as a 31word by 21bit RAM and a 5bit Stack Pointer STKPTR The stack space is not part of either program or data space The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Topof Stack TOS Special Function Registers Data can also be pushed to or popped from the stack using these registers A CALL type instruction causes a push onto the stack the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC already pointing to the instruction following the CALL A RETURN type instruction causes a pop from the stack the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented The Stack Pointer is initialized to 00000 after all Resets There is no RAM associated with the location corresponding to a Stack Pointer value of 00000 this is only a Reset value Status bits indicate if the stack is full or has overflowed or underflowed 5121 TopofStack Access Only the top of the return address stack TOS is readable and writable A set of three registers TOSUTOSHTOSL hold the contents of the stack loca tion pointed to by the STKPTR register Figure 52 This allows users to implement a software stack if necessary After a CALL RCALL or interrupt the software can read the pushed value by reading the TOSUTOSHTOSL registers These values can be placed on a userdefined software stack At return time the software can return these values to TOSUTOSHTOSL and do a return The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption FIGURE 52 RETURN ADDRESS STACK AND ASSOCIATED REGISTERS 00011 001A34h 11111 11110 11101 00010 00001 00000 00010 Return Address Stack 200 TopofStack 000D58h TOSL TOSH TOSU 34h 1Ah 00h STKPTR40 TopofStack Registers Stack Pointer 2008 Microchip Technology Inc DS39631Epage 55 PIC18F2420252044204520 5122 Return Stack Pointer STKPTR The STKPTR register Register 51 contains the Stack Pointer value the STKFUL Stack Full status bit and the STKUNF Stack Underflow status bits The value of the Stack Pointer can be 0 through 31 The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack On Reset the Stack Pointer value will be zero The user may read and write the Stack Pointer value This feature can be used by a RealTime Operating System RTOS for return stack maintenance After the PC is pushed onto the stack 31 times without popping any values off the stack the STKFUL bit is set The STKFUL bit is cleared by software or by a POR The action that takes place when the stack becomes full depends on the state of the STVREN Stack Over flow Reset Enable Configuration bit Refer to Section 231 Configuration Bits for a description of the device Configuration bits If STVREN is set default the 31st push will push the PC 2 value onto the stack set the STKFUL bit and reset the device The STKFUL bit will remain set and the Stack Pointer will be set to zero If STVREN is cleared the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31 Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31 When the stack has been popped enough times to unload the stack the next pop will return a value of zero to the PC and sets the STKUNF bit while the Stack Pointer remains at zero The STKUNF bit will remain set until cleared by software or until a POR occurs 5123 PUSH and POP Instructions Since the TopofStack is readable and writable the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature The PIC18 instruction set includes two instructions PUSH and POP that permit the TOS to be manipulated under software control TOSU TOSH and TOSL can be modified to place data or a return address on the stack The PUSH instruction places the current PC value onto the stack This increments the Stack Pointer and loads the current PC value onto the stack The POP instruction discards the current TOS by decre menting the Stack Pointer The previous value pushed onto the stack then becomes the TOS value Note Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector where the stack conditions can be verified and appropriate actions can be taken This is not the same as a Reset as the contents of the SFRs are not affected REGISTER 51 STKPTR STACK POINTER REGISTER RC0 RC0 U0 RW0 RW0 RW0 RW0 RW0 STKFUL1 STKUNF1 SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend C Clearable bit R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 STKFUL Stack Full Flag bit1 1 Stack became full or overflowed 0 Stack has not become full or overflowed bit 6 STKUNF Stack Underflow Flag bit1 1 Stack underflow occurred 0 Stack underflow did not occur bit 5 Unimplemented Read as 0 bit 40 SP40 Stack Pointer Location bits Note 1 Bit 7 and bit 6 are cleared by user software or by a POR PIC18F2420252044204520 DS39631Epage 56 2008 Microchip Technology Inc 5124 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L When STVREN is set a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset When STVREN is cleared a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset The STKFUL or STKUNF bits are cleared by the user software or a Poweron Reset 513 FAST REGISTER STACK A Fast Register Stack is provided for the STATUS WREG and BSR registers to provide a fast return option for interrupts The stack for each register is only one level deep and is neither readable nor writable It is loaded with the current value of the corresponding reg ister when the processor vectors for an interrupt All interrupt sources will push values into the stack regis ters The values in the registers are then loaded back into their associated registers if the RETFIE FAST instruction is used to return from the interrupt If both low and highpriority interrupts are enabled the stack registers cannot be used reliably to return from lowpriority interrupts If a highpriority interrupt occurs while servicing a lowpriority interrupt the stack regis ter values stored by the lowpriority interrupt will be overwritten In these cases users must save the key registers in software during a lowpriority interrupt If interrupt priority is not used all interrupts may use the Fast Register Stack for returns from interrupt If no interrupts are used the Fast Register Stack can be used to restore the STATUS WREG and BSR registers at the end of a subroutine call To use the Fast Register Stack for a subroutine call a CALL label FAST instruction must be executed to save the STATUS WREG and BSR registers to the Fast Register Stack A RETURN FAST instruction is then executed to restore these registers from the Fast Register Stack Example 51 shows a source code example that uses the Fast Register Stack during a subroutine call and return EXAMPLE 51 FAST REGISTER STACK CODE EXAMPLE 514 LOOKUP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or lookup tables in program memory For PIC18 devices lookup tables can be implemented in two ways Computed GOTO Table Reads 5141 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter An example is shown in Example 52 A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions The W register is loaded with an offset into the table before executing a call to that table The first instruction of the called routine is the ADDWF PCL instruction The next instruction executed will be one of the RETLW nn instructions that returns the value nn to the calling function The offset value in WREG specifies the number of bytes that the program counter should advance and should be multiples of 2 LSb 0 In this method only one data byte may be stored in each instruction location and room on the return address stack is required EXAMPLE 52 COMPUTED GOTO USING AN OFFSET VALUE 5142 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location Lookup table data may be stored two bytes per pro gram word by using table reads and writes The Table Pointer TBLPTR register specifies the byte address and the Table Latch TABLAT register contains the data that is read from or written to program memory Data is transferred to or from program memory one byte at a time Table read and table write operations are discussed further in Section 61 Table Reads and Table Writes CALL SUB1 FAST STATUS WREG BSR SAVED IN FAST REGISTER STACK SUB1 RETURN FAST RESTORE VALUES SAVED IN FAST REGISTER STACK MOVF OFFSET W CALL TABLE ORG nn00h TABLE ADDWF PCL RETLW nnh RETLW nnh RETLW nnh 2008 Microchip Technology Inc DS39631Epage 57 PIC18F2420252044204520 52 PIC18 Instruction Cycle 521 CLOCKING SCHEME The microcontroller clock input whether from an inter nal or external source is internally divided by four to generate four nonoverlapping quadrature clocks Q1 Q2 Q3 and Q4 Internally the program counter is incremented on every Q1 the instruction is fetched from the program memory and latched into the instruc tion register during Q4 The instruction is decoded and executed during the following Q1 through Q4 The clocks and instruction execution flow are shown in Figure 53 522 INSTRUCTION FLOWPIPELINING An Instruction Cycle consists of four Q cycles Q1 through Q4 The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle while the decode and execute take another instruction cycle However due to the pipe lining each instruction effectively executes in one cycle If an instruction causes the program counter to change eg GOTO then two cycles are required to complete the instruction Example 53 A fetch cycle begins with the Program Counter PC incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write FIGURE 53 CLOCKINSTRUCTION CYCLE EXAMPLE 53 INSTRUCTION PIPELINE FLOW Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 PC OSC2CLKO RC mode PC PC 2 PC 4 Fetch INST PC Execute INST PC 2 Fetch INST PC 2 Execute INST PC Fetch INST PC 4 Execute INST PC 2 Internal Phase Clock All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1 MOVLW 55h Fetch 1 Execute 1 2 MOVWF PORTB Fetch 2 Execute 2 3 BRA SUB1 Fetch 3 Execute 3 4 BSF PORTA BIT3 Forced NOP Fetch 4 Flush NOP 5 Instruction address SUB1 Fetch SUB1 Execute SUB1 PIC18F2420252044204520 DS39631Epage 58 2008 Microchip Technology Inc 523 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes Instruc tions are stored as two bytes or four bytes in program memory The Least Significant Byte of an instruction word is always stored in a program memory location with an even address LSb 0 To maintain alignment with instruction boundaries the PC increments in steps of 2 and the LSb will always read 0 see Section 511 Program Counter Figure 54 shows an example of how instruction words are stored in the program memory The CALL and GOTO instructions have the absolute pro gram memory address embedded into the instruction Since instructions are always stored on word boundar ies the data contained in the instruction is a word address The word address is written to PC201 which accesses the desired byte address in program memory Instruction 2 in Figure 54 shows how the instruction GOTO 0006h is encoded in the program memory Program branch instructions which encode a relative address offset operate in the same manner The offset value stored in a branch instruction represents the number of singleword instructions that the PC will be offset by Section 240 Instruction Set Summary provides further details of the instruction set FIGURE 54 INSTRUCTIONS IN PROGRAM MEMORY 524 TWOWORD INSTRUCTIONS The standard PIC18 instruction set has four twoword instructions CALL MOVFF GOTO and LSFR In all cases the second word of the instructions always has 1111 as its four Most Significant bits the other 12 bits are literal data usually a data memory address The use of 1111 in the 4 MSbs of an instruction spec ifies a special form of NOP If the instruction is executed in proper sequence immediately after the first word the data in the second word is accessed and used by the instruction sequence If the first word is skipped for some reason and the second word is executed by itself a NOP is executed instead This is necessary for cases when the twoword instruction is preceded by a condi tional instruction that changes the PC Example 54 shows how this works EXAMPLE 54 TWOWORD INSTRUCTIONS Word Address LSB 1 LSB 0 Program Memory Byte Locations 000000h 000002h 000004h 000006h Instruction 1 MOVLW 055h 0Fh 55h 000008h Instruction 2 GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3 MOVFF 123h 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h Note See Section 56 PIC18 Instruction Execution and the Extended Instruc tion Set for information on twoword instructions in the extended instruction set CASE 1 Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 is RAM location 0 1100 0001 0010 0011 MOVFF REG1 REG2 No skip this word 1111 0100 0101 0110 Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 continue code CASE 2 Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 is RAM location 0 1100 0001 0010 0011 MOVFF REG1 REG2 Yes execute this word 1111 0100 0101 0110 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 continue code 2008 Microchip Technology Inc DS39631Epage 59 PIC18F2420252044204520 53 Data Memory Organization The data memory in PIC18 devices is implemented as static RAM Each register in the data memory has a 12bit address allowing up to 4096 bytes of data memory The memory space is divided into as many as 16 banks that contain 256 bytes each PIC18F2420 252044204520 devices implement all 16 banks Figure 55 shows the data memory organization for the PIC18F2420252044204520 devices The data memory contains Special Function Registers SFRs and General Purpose Registers GPRs The SFRs are used for control and status of the controller and peripheral functions while GPRs are used for data storage and scratchpad operations in the users application Any read of an unimplemented location will read as 0s The instruction set and architecture allow operations across all banks The entire data memory may be accessed by Direct Indirect or Indexed Addressing modes Addressing modes are discussed later in this subsection To ensure that commonly used registers SFRs and select GPRs can be accessed in a single cycle PIC18 devices implement an Access Bank This is a 256byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR Section 532 Access Bank provides a detailed description of the Access RAM 531 BANK SELECT REGISTER BSR Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible Ideally this means that an entire address does not need to be provided for each read or write operation For PIC18 devices this is accom plished with a RAM banking scheme This divides the memory space into 16 contiguous banks of 256 bytes Depending on the instruction each location can be addressed directly by its full 12bit address or an 8bit loworder address and a 4bit Bank Pointer Most instructions in the PIC18 instruction set make use of the Bank Pointer known as the Bank Select Register BSR This SFR holds the 4 Most Significant bits of a locations address the instruction itself includes the 8 Least Significant bits Only the four lower bits of the BSR are implemented BSR30 The upper four bits are unused they will always read 0 and cannot be written to The BSR can be loaded directly by using the MOVLB instruction The value of the BSR indicates the bank in data memory the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the banks lower boundary The relationship between the BSRs value and the bank division in data memory is shown in Figure 57 Since up to 16 registers may share the same loworder address the user must always be careful to ensure that the proper bank is selected before performing a data read or write For example writing what should be program data to an 8bit address of F9h while the BSR is 0Fh will end up resetting the program counter While any bank can be selected only those banks that are actually implemented can be read or written to Writes to unimplemented banks are ignored while reads from unimplemented banks will return 0s Even so the STATUS register will still be affected as if the operation was successful The data memory map in Figure 55 indicates which banks are implemented In the core PIC18 instruction set only the MOVFF instruction fully specifies the 12bit address of the source and target registers This instruction ignores the BSR completely when it executes All other instructions include only the loworder address as an operand and must use either the BSR or the Access Bank to locate their target registers Note The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled See Section 55 Data Memory and the Extended Instruction Set for more information PIC18F2420252044204520 DS39631Epage 60 2008 Microchip Technology Inc FIGURE 55 DATA MEMORY MAP FOR PIC18F24204420 DEVICES Bank 0 Bank 1 Bank 14 Bank 15 Data Memory Map BSR30 0000 0001 1111 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Access Bank When a 0 The BSR is ignored and the Access Bank is used The first 128 bytes are general purpose RAM from Bank 0 The second 128 bytes are Special Function Registers from Bank 15 When a 1 The BSR specifies the Bank used by the instruction F7Fh F00h EFFh 1FFh 100h 0FFh 000h Access RAM FFh 00h FFh 00h FFh 00h GPR GPR SFR Access RAM High Access RAM Low Bank 2 0110 0010 SFRs 2FFh 200h 3FFh 300h 4FFh 400h 5FFh 500h 6FFh 600h 7FFh 700h 8FFh 800h 9FFh 900h AFFh A00h BFFh B00h CFFh C00h DFFh D00h E00h Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h GPR FFh 00h 0011 0100 0101 0111 1000 1001 1010 1011 1100 1101 1110 Unused Read 00h Unused 2008 Microchip Technology Inc DS39631Epage 61 PIC18F2420252044204520 FIGURE 56 DATA MEMORY MAP FOR PIC18F25204520 DEVICES Bank 0 Bank 1 Bank 14 Bank 15 Data Memory Map BSR30 0000 0001 1111 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Access Bank When a 0 The BSR is ignored and the Access Bank is used The first 128 bytes are general purpose RAM from Bank 0 The second 128 bytes are Special Function Registers from Bank 15 When a 1 The BSR specifies the Bank used by the instruction F7Fh F00h EFFh 1FFh 100h 0FFh 000h Access RAM FFh 00h FFh 00h FFh 00h GPR GPR SFR Access RAM High Access RAM Low Bank 2 0110 0010 SFRs 2FFh 200h 3FFh 300h 4FFh 400h 5FFh 500h 6FFh 600h 7FFh 700h 8FFh 800h 9FFh 900h AFFh A00h BFFh B00h CFFh C00h DFFh D00h E00h Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h GPR FFh 00h 0011 0100 0101 0111 1000 1001 1010 1011 1100 1101 1110 Unused Read 00h Unused GPR GPR GPR PIC18F2420252044204520 DS39631Epage 62 2008 Microchip Technology Inc FIGURE 57 USE OF THE BANK SELECT REGISTER DIRECT ADDRESSING 532 ACCESS BANK While the use of the BSR with an embedded 8bit address allows users to address the entire range of data memory it also means that the user must always ensure that the correct bank is selected Otherwise data may be read from or written to the wrong location This can be disastrous if a GPR is the intended target of an operation but an SFR is written to instead Verifying andor changing the BSR for each read or write to data memory can become very inefficient To streamline access for the most commonly used data memory locations the data memory is configured with an Access Bank which allows users to access a mapped block of memory without specifying a BSR The Access Bank consists of the first 128 bytes of memory 00h7Fh in Bank 0 and the last 128 bytes of memory 80hFFh in Block 15 The lower half is known as the Access RAM and is composed of GPRs This upper half is also where the devices SFRs are mapped These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8bit address Figure 55 The Access Bank is used by core PIC18 instructions that include the Access RAM bit the a parameter in the instruction When a is equal to 1 the instruction uses the BSR and the 8bit address included in the opcode for the data memory address When a is 0 however the instruction is forced to use the Access Bank address map the current value of the BSR is ignored entirely Using this forced addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first For 8bit addresses of 80h and above this means that users can evaluate and operate on SFRs more efficiently The Access RAM below 80h is a good place for data values that the user might need to access rapidly such as immediate computational results or common program variables Access RAM also allows for faster and more code efficient context saving and switching of variables The mapping of the Access Bank is slightly different when the extended instruction set is enabled XINST Configuration bit 1 This is discussed in more detail in Section 553 Mapping the Access Bank in Indexed Literal Offset Mode 533 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area This is data RAM which is available for use by all instructions GPRs start at the bottom of Bank 0 address 000h and grow upwards towards the bottom of the SFR area GPRs are not initialized by a Poweron Reset and are unchanged on all other Resets Note 1 The Access RAM bit of the instruction can be used to force an override of the selected bank BSR30 to the registers of the Access Bank 2 The MOVFF instruction embeds the entire 12bit address in the instruction Data Memory Bank Select2 7 0 From Opcode2 0 0 0 0 000h 100h 200h 300h F00h E00h FFFh Bank 0 Bank 1 Bank 2 Bank 14 Bank 15 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh Bank 3 through Bank 13 0 0 1 1 1 1 1 1 1 1 1 1 7 0 BSR1 2008 Microchip Technology Inc DS39631Epage 63 PIC18F2420252044204520 534 SPECIAL FUNCTION REGISTERS The Special Function Registers SFRs are registers used by the CPU and peripheral modules for controlling the desired operation of the device These registers are implemented as static RAM SFRs start at the top of data memory FFFh and extend downward to occupy the top half of Bank 15 F80h to FFFh A list of these registers is given in Table 51 and Table 52 The SFRs can be classified into two sets those asso ciated with the core device functionality ALU Resets and interrupts and those related to the peripheral func tions The Reset and Interrupt registers are described in their respective chapters while the ALUs STATUS register is described later in this section Registers related to the operation of a peripheral feature are described in the chapter for that peripheral The SFRs are typically distributed among the peripherals whose functions they control Unused SFR locations are unimplemented and read as 0s TABLE 51 SPECIAL FUNCTION REGISTER MAP FOR PIC18F2420252044204520 DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF21 FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC21 FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC21 FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC21 FBCh CCPR2H F9Ch 2 FFBh PCLATU FDBh PLUSW21 FBBh CCPR2L F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah 2 FF9h PCL FD9h FSR2L FB9h 2 F99h 2 FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h 2 FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON3 F97h 2 FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS3 F96h TRISE3 FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD3 FF4h PRODH FD4h 2 FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h 2 FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h 2 FEFh INDF01 FCFh TMR1H FAFh SPBRG F8Fh 2 FEEh POSTINC01 FCEh TMR1L FAEh RCREG F8Eh 2 FEDh POSTDEC01 FCDh T1CON FADh TXREG F8Dh LATE3 FECh PREINC01 FCCh TMR2 FACh TXSTA F8Ch LATD3 FEBh PLUSW01 FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh 2 F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h 2 FE7h INDF11 FC7h SSPSTAT FA7h EECON21 F87h 2 FE6h POSTINC11 FC6h SSPCON1 FA6h EECON1 F86h 2 FE5h POSTDEC11 FC5h SSPCON2 FA5h 2 F85h 2 FE4h PREINC11 FC4h ADRESH FA4h 2 F84h PORTE3 FE3h PLUSW11 FC3h ADRESL FA3h 2 F83h PORTD3 FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1 This is not a physical register 2 Unimplemented registers are read as 0 3 This register is not available on 28pin devices PIC18F2420252044204520 DS39631Epage 64 2008 Microchip Technology Inc TABLE 52 PIC18F2420252044204520 REGISTER FILE SUMMARY File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR BOR Details on page TOSU TopofStack Upper Byte TOS2016 0 0000 49 54 TOSH TopofStack High Byte TOS158 0000 0000 49 54 TOSL TopofStack Low Byte TOS70 0000 0000 49 54 STKPTR STKFUL STKUNF SP4 SP3 SP2 SP1 SP0 000 0000 49 55 PCLATU Holding Register for PC2016 0 0000 49 54 PCLATH Holding Register for PC158 0000 0000 49 54 PCL PC Low Byte PC70 0000 0000 49 54 TBLPTRU bit 21 Program Memory Table Pointer Upper Byte TBLPTR2016 00 0000 49 76 TBLPTRH Program Memory Table Pointer High Byte TBLPTR158 0000 0000 49 76 TBLPTRL Program Memory Table Pointer Low Byte TBLPTR70 0000 0000 49 76 TABLAT Program Memory Table Latch 0000 0000 49 76 PRODH Product Register High Byte xxxx xxxx 49 89 PRODL Product Register Low Byte xxxx xxxx 49 89 INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49 93 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP RBIP 1111 11 49 94 INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 110 000 49 95 INDF0 Uses contents of FSR0 to address data memory value of FSR0 not changed not a physical register NA 49 69 POSTINC0 Uses contents of FSR0 to address data memory value of FSR0 postincremented not a physical register NA 49 69 POSTDEC0 Uses contents of FSR0 to address data memory value of FSR0 postdecremented not a physical register NA 49 69 PREINC0 Uses contents of FSR0 to address data memory value of FSR0 preincremented not a physical register NA 49 69 PLUSW0 Uses contents of FSR0 to address data memory value of FSR0 preincremented not a physical register value of FSR0 offset by W NA 49 69 FSR0H Indirect Data Memory Address Pointer 0 High Byte 0000 49 69 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49 69 WREG Working Register xxxx xxxx 49 INDF1 Uses contents of FSR1 to address data memory value of FSR1 not changed not a physical register NA 49 69 POSTINC1 Uses contents of FSR1 to address data memory value of FSR1 postincremented not a physical register NA 49 69 POSTDEC1 Uses contents of FSR1 to address data memory value of FSR1 postdecremented not a physical register NA 49 69 PREINC1 Uses contents of FSR1 to address data memory value of FSR1 preincremented not a physical register NA 49 69 PLUSW1 Uses contents of FSR1 to address data memory value of FSR1 preincremented not a physical register value of FSR1 offset by W NA 49 69 FSR1H Indirect Data Memory Address Pointer 1 High Byte 0000 50 69 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 50 69 BSR Bank Select Register 0000 50 59 INDF2 Uses contents of FSR2 to address data memory value of FSR2 not changed not a physical register NA 50 69 POSTINC2 Uses contents of FSR2 to address data memory value of FSR2 postincremented not a physical register NA 50 69 POSTDEC2 Uses contents of FSR2 to address data memory value of FSR2 postdecremented not a physical register NA 50 69 PREINC2 Uses contents of FSR2 to address data memory value of FSR2 preincremented not a physical register NA 50 69 PLUSW2 Uses contents of FSR2 to address data memory value of FSR2 preincremented not a physical register value of FSR2 offset by W NA 50 69 FSR2H Indirect Data Memory Address Pointer 2 High Byte 0000 50 69 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50 69 STATUS N OV Z DC C x xxxx 50 67 Legend x unknown u unchanged unimplemented q value depends on condition Shaded cells are unimplemented read as 0 Note 1 The SBOREN bit is only available when the BOREN10 Configuration bits 01 otherwise it is disabled and reads as 0 See Section 44 Brownout Reset BOR 2 These registers andor bits are not implemented on 28pin devices and are read as 0 Reset values are shown for 4044pin devices individual unimplemented bits should be interpreted as 3 The PLLEN bit is only available in specific oscillator configurations otherwise it is disabled and reads as 0 See Section 264 PLL in INTOSC Modes 4 The RE3 bit is only available when Master Clear Reset is disabled MCLRE Configuration bit 0 otherwise RE3 reads as 0 This bit is readonly 5 RA6RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes When disabled these bits read as 0 2008 Microchip Technology Inc DS39631Epage 65 PIC18F2420252044204520 TMR0H Timer0 Register High Byte 0000 0000 50 125 TMR0L Timer0 Register Low Byte xxxx xxxx 50 125 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50 123 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 30 50 HLVDCON VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 000 0101 50 245 WDTCON SWDTEN 0 50 259 RCON IPEN SBOREN1 RI TO PD POR BOR 0q1 11q0 42 48 102 TMR1H Timer1 Register High Byte xxxx xxxx 50 132 TMR1L Timer1 Register Low Bytes xxxx xxxx 50 132 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50 127 TMR2 Timer2 Register 0000 0000 50 134 PR2 Timer2 Period Register 1111 1111 50 134 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 000 0000 50 133 SSPBUF MSSP Receive BufferTransmit Register xxxx xxxx 50 169 170 SSPADD MSSP Address Register in I2C Slave Mode MSSP Baud Rate Reload Register in I2C Master Mode 0000 0000 50 170 SSPSTAT SMP CKE DA P S RW UA BF 0000 0000 50 162 171 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50 163 172 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50 173 ADRESH AD Result Register High Byte xxxx xxxx 51 232 ADRESL AD Result Register Low Byte xxxx xxxx 51 232 ADCON0 CHS3 CHS2 CHS1 CHS0 GODONE ADON 00 0000 51 223 ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 00 0qqq 51 224 ADCON2 ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 000 0000 51 225 CCPR1H CaptureComparePWM Register 1 High Byte xxxx xxxx 51 140 CCPR1L CaptureComparePWM Register 1 Low Byte xxxx xxxx 51 140 CCP1CON P1M12 P1M02 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 51 139 147 CCPR2H CaptureComparePWM Register 2 High Byte xxxx xxxx 51 140 CCPR2L CaptureComparePWM Register 2 Low Byte xxxx xxxx 51 140 CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 00 0000 51 139 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 0100 000 51 204 PWM1CON PRSEN PDC62 PDC52 PDC42 PDC32 PDC22 PDC12 PDC02 0000 0000 51 156 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD12 PSSBD02 0000 0000 51 157 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51 239 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 51 233 TMR3H Timer3 Register High Byte xxxx xxxx 51 137 TMR3L Timer3 Register Low Byte xxxx xxxx 51 137 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51 135 TABLE 52 PIC18F2420252044204520 REGISTER FILE SUMMARY CONTINUED File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR BOR Details on page Legend x unknown u unchanged unimplemented q value depends on condition Shaded cells are unimplemented read as 0 Note 1 The SBOREN bit is only available when the BOREN10 Configuration bits 01 otherwise it is disabled and reads as 0 See Section 44 Brownout Reset BOR 2 These registers andor bits are not implemented on 28pin devices and are read as 0 Reset values are shown for 4044pin devices individual unimplemented bits should be interpreted as 3 The PLLEN bit is only available in specific oscillator configurations otherwise it is disabled and reads as 0 See Section 264 PLL in INTOSC Modes 4 The RE3 bit is only available when Master Clear Reset is disabled MCLRE Configuration bit 0 otherwise RE3 reads as 0 This bit is readonly 5 RA6RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes When disabled these bits read as 0 PIC18F2420252044204520 DS39631Epage 66 2008 Microchip Technology Inc SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 51 206 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 51 206 RCREG EUSART Receive Register 0000 0000 51 213 TXREG EUSART Transmit Register 0000 0000 51 211 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51 202 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51 203 EEADR EEPROM Address Register 0000 0000 51 74 83 EEDATA EEPROM Data Register 0000 0000 51 74 83 EECON2 EEPROM Control Register 2 not a physical register 0000 0000 51 74 83 EECON1 EEPGD CFGS FREE WRERR WREN WR RD xx0 x000 51 75 84 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 111 1111 52 101 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 000 0000 52 97 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 000 0000 52 99 IPR1 PSPIP2 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52 100 PIR1 PSPIF2 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52 96 PIE1 PSPIE2 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52 98 OSCTUNE INTSRC PLLEN3 TUN4 TUN3 TUN2 TUN1 TUN0 0q0 0000 27 52 TRISE2 IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 0000 111 52 118 TRISD2 PORTD Data Direction Register 1111 1111 52 114 TRISC PORTC Data Direction Register 1111 1111 52 111 TRISB PORTB Data Direction Register 1111 1111 52 108 TRISA TRISA75 TRISA65 PORTA Data Direction Register 1111 1111 52 105 LATE2 PORTE Data Latch Register Read and Write to Data Latch xxx 52 117 LATD2 PORTD Data Latch Register Read and Write to Data Latch xxxx xxxx 52 114 LATC PORTC Data Latch Register Read and Write to Data Latch xxxx xxxx 52 111 LATB PORTB Data Latch Register Read and Write to Data Latch xxxx xxxx 52 108 LATA LATA75 LATA65 PORTA Data Latch Register Read and Write to Data Latch xxxx xxxx 52 105 PORTE RE34 RE22 RE12 RE02 xxxx 52 117 PORTD2 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52 114 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52 111 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52 108 PORTA RA75 RA65 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 52 105 TABLE 52 PIC18F2420252044204520 REGISTER FILE SUMMARY CONTINUED File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR BOR Details on page Legend x unknown u unchanged unimplemented q value depends on condition Shaded cells are unimplemented read as 0 Note 1 The SBOREN bit is only available when the BOREN10 Configuration bits 01 otherwise it is disabled and reads as 0 See Section 44 Brownout Reset BOR 2 These registers andor bits are not implemented on 28pin devices and are read as 0 Reset values are shown for 4044pin devices individual unimplemented bits should be interpreted as 3 The PLLEN bit is only available in specific oscillator configurations otherwise it is disabled and reads as 0 See Section 264 PLL in INTOSC Modes 4 The RE3 bit is only available when Master Clear Reset is disabled MCLRE Configuration bit 0 otherwise RE3 reads as 0 This bit is readonly 5 RA6RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes When disabled these bits read as 0 2008 Microchip Technology Inc DS39631Epage 67 PIC18F2420252044204520 535 STATUS REGISTER The STATUS register shown in Register 52 contains the arithmetic status of the ALU As with any other SFR it can be the operand for any instruction If the STATUS register is the destination for an instruc tion that affects the Z DC C OV or N bits the results of the instruction are not written instead the STATUS register is updated according to the instruction per formed Therefore the result of an instruction with the STATUS register as its destination may be different than intended As an example CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged 000u u1uu It is recommended that only BCF BSF SWAPF MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z C DC OV or N bits in the STATUS register For other instructions that do not affect Status bits see the instruction set summaries in Table 242 and Table 243 Note The C and DC bits operate as the borrow and digit borrow bits respectively in subtraction REGISTER 52 STATUS REGISTER U0 U0 U0 RWx RWx RWx RWx RWx N OV Z DC1 C2 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 75 Unimplemented Read as 0 bit 4 N Negative bit This bit is used for signed arithmetic 2s complement It indicates whether the result was negative ALU MSB 1 1 Result was negative 0 Result was positive bit 3 OV Overflow bit This bit is used for signed arithmetic 2s complement It indicates an overflow of the 7bit magnitude which causes the sign bit bit 7 to change state 1 Overflow occurred for signed arithmetic in this arithmetic operation 0 No overflow occurred bit 2 Z Zero bit 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 DC Digit Carryborrow bit1 For ADDWF ADDLW SUBLW and SUBWF instructions 1 A carryout from the 4th loworder bit of the result occurred 0 No carryout from the 4th loworder bit of the result bit 0 C Carryborrow bit2 For ADDWF ADDLW SUBLW and SUBWF instructions 1 A carryout from the Most Significant bit of the result occurred 0 No carryout from the Most Significant bit of the result occurred Note 1 For borrow the polarity is reversed A subtraction is executed by adding the 2s complement of the second operand For rotate RRF RLF instructions this bit is loaded with either bit 4 or bit 3 of the source register 2 For borrow the polarity is reversed A subtraction is executed by adding the 2s complement of the second operand For rotate RRF RLF instructions this bit is loaded with either the high or loworder bit of the source register PIC18F2420252044204520 DS39631Epage 68 2008 Microchip Technology Inc 54 Data Addressing Modes While the program memory can be addressed in only one way through the program counter information in the data memory space can be addressed in several ways For most instructions the addressing mode is fixed Other instructions may use up to three modes depending on which operands are used and whether or not the extended instruction set is enabled The addressing modes are Inherent Literal Direct Indirect An additional addressing mode Indexed Literal Offset is available when the extended instruction set is enabled XINST Configuration bit 1 Its operation is discussed in greater detail in Section 551 Indexed Addressing with Literal Offset 541 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all they either perform an operation that globally affects the device or they operate implicitly on one register This addressing mode is known as Inherent Addressing Examples include SLEEP RESET and DAW Other instructions work in a similar way but require an additional explicit argument in the opcode This is known as Literal Addressing mode because they require some literal value as an argument Examples include ADDLW and MOVLW which respectively add or move a literal value to the W register Other examples include CALL and GOTO which include a 20bit program memory address 542 DIRECT ADDRESSING Direct Addressing specifies all or part of the source andor destination address of the operation within the opcode itself The options are specified by the arguments accompanying the instruction In the core PIC18 instruction set bitoriented and byte oriented instructions use some version of Direct Addressing by default All of these instructions include some 8bit literal address as their Least Significant Byte This address specifies either a register address in one of the banks of data RAM Section 533 General Purpose Register File or a location in the Access Bank Section 532 Access Bank as the data source for the instruction The Access RAM bit a determines how the address is interpreted When a is 1 the contents of the BSR Section 531 Bank Select Register BSR are used with the address to determine the complete 12bit address of the register When a is 0 the address is interpreted as being a register in the Access Bank Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode A few instructions such as MOVFF include the entire 12bit address either source or destination in their opcodes In these cases the BSR is ignored entirely The destination of the operations results is determined by the destination bit d When d is 1 the results are stored back in the source register overwriting its origi nal contents When d is 0 the results are stored in the W register Instructions without the d argument have a destination that is implicit in the instruction their destination is either the target register being operated on or the W register 543 INDIRECT ADDRESSING Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction This is done by using File Select Registers FSRs as pointers to the locations to be read or written to Since the FSRs are themselves located in RAM as Special Function Registers they can also be directly manipulated under program control This makes FSRs very useful in implementing data structures such as tables and arrays in data memory The registers for Indirect Addressing are also implemented with Indirect File Operands INDFs that permit automatic manipulation of the pointer value with autoincrementing autodecrementing or offsetting with another value This allows for efficient code using loops such as the example of clearing an entire RAM bank in Example 55 EXAMPLE 55 HOW TO CLEAR RAM BANK 1 USING INDIRECT ADDRESSING Note The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled See Section 55 Data Memory and the Extended Instruction Set for more information LFSR FSR0 100h NEXT CLRF POSTINC0 Clear INDF register then inc pointer BTFSS FSR0H 1 All done with Bank1 BRA NEXT NO clear next CONTINUE YES continue 2008 Microchip Technology Inc DS39631Epage 69 PIC18F2420252044204520 5431 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of reg isters FSR0 FSR1 and FSR2 Each represents a pair of 8bit registers FSRnH and FSRnL The four upper bits of the FSRnH register are not used so each FSR pair holds a 12bit value This represents a value that can address the entire range of the data memory in a linear fashion The FSR register pairs then serve as pointers to data memory locations Indirect Addressing is accomplished with a set of Indirect File Operands INDF0 through INDF2 These can be thought of as virtual registers they are mapped in the SFR space but are not physically imple mented Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair A read from INDF1 for example reads the data at the address indicated by FSR1HFSR1L Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instructions target The INDF operand is just a convenient way of using the pointer Because Indirect Addressing uses a full 12bit address data RAM banking is not necessary Thus the current contents of the BSR and the Access RAM bit have no effect on determining the target address 5432 FSR Registers and POSTINC POSTDEC PREINC and PLUSW In addition to the INDF operand each FSR register pair also has four additional indirect operands Like INDF these are virtual registers that cannot be indirectly read or written to Accessing these registers actually accesses the associated FSR register pair but also performs a specific action on it stored value They are POSTDEC accesses the FSR value then automatically decrements it by 1 afterwards POSTINC accesses the FSR value then automatically increments it by 1 afterwards PREINC increments the FSR value by 1 then uses it in the operation PLUSW adds the signed value of the W register range of 127 to 128 to that of the FSR and uses the new value in the operation In this context accessing an INDF register uses the value in the FSR registers without changing them Sim ilarly accessing a PLUSW register gives the FSR value offset by that in the W register neither value is actually changed in the operation Accessing the other virtual registers changes the value of the FSR registers Operations on the FSRs with POSTDEC POSTINC and PREINC affect the entire register pair that is roll overs of the FSRnL register from FFh to 00h carry over to the FSRnH register On the other hand results of these operations do not change the value of any flags in the STATUS register eg Z N OV etc FIGURE 58 INDIRECT ADDRESSING FSR1HFSR1L 0 7 Data Memory 000h 100h 200h 300h F00h E00h FFFh Bank 0 Bank 1 Bank 2 Bank 14 Bank 15 Bank 3 through Bank 13 ADDWF INDF1 1 0 7 Using an instruction with one of the Indirect Addressing registers as the operand uses the 12bit address stored in the FSR pair associated with that register to determine the data memory location to be used in that operation In this case the FSR1 pair contains ECCh This means the contents of location ECCh will be added to that of the W register and stored back in ECCh x x x x 1 1 1 0 1 1 0 0 1 1 0 0 PIC18F2420252044204520 DS39631Epage 70 2008 Microchip Technology Inc The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space By manipulating the value in the W register users can reach addresses that are fixed offsets from pointer addresses In some applications this can be used to implement some powerful program control structure such as software stacks inside of data memory 5433 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases For example using an FSR to point to one of the virtual registers will not result in successful operations As a specific case assume that FSR0HFSR0L contains FE7h the address of INDF1 Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h Attempts to write to INDF1 using INDF0 as the operand will result in a NOP On the other hand using the virtual registers to write to an FSR pair may not occur as planned In these cases the value will be written to the FSR pair but without any incrementing or decrementing Thus writing to INDF2 or POSTDEC2 will write the same value to the FSR2HFSR2L Since the FSRs are physical registers mapped in the SFR space they can be manipulated through all direct operations Users should proceed cautiously when working on these registers particularly if their code uses indirect addressing Similarly operations by Indirect Addressing are gener ally permitted on all other SFRs Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device 55 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set XINST Configuration bit 1 significantly changes certain aspects of data memory and its addressing Specifi cally the use of the Access Bank for many of the core PIC18 instructions is different this is due to the introduction of a new addressing mode for the data memory space What does not change is just as important The size of the data memory space is unchanged as well as its linear addressing The SFR map remains the same Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode inherent and literal instructions do not change at all Indirect Addressing with FSR0 and FSR1 also remains unchanged 551 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM Under the proper conditions instructions that use the Access Bank that is most bitoriented and byteoriented instructions can invoke a form of Indexed Addressing using an offset specified in the instruction This special address ing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode When using the extended instruction set this addressing mode requires the following The use of the Access Bank is forced a 0 and The file address argument is less than or equal to 5Fh Under these conditions the file address of the instruc tion is not interpreted as the lower byte of an address used with the BSR in direct addressing or as an 8bit address in the Access Bank Instead the value is interpreted as an offset value to an Address Pointer specified by FSR2 The offset and the contents of FSR2 are added to obtain the target address of the operation 552 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode This includes all byteoriented and bitoriented instructions or almost onehalf of the standard PIC18 instruction set Instructions that only use Inherent or Literal Addressing modes are unaffected Additionally byteoriented and bitoriented instructions are not affected if they do not use the Access Bank Access RAM bit is 1 or include a file address of 60h or above Instructions meeting these criteria will continue to execute as before A comparison of the dif ferent possible addressing modes when the extended instruction set is enabled in shown in Figure 59 Those who desire to use byteoriented or bitoriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode This is described in more detail in Section 2421 Extended Instruction Syntax 2008 Microchip Technology Inc DS39631Epage 71 PIC18F2420252044204520 FIGURE 59 COMPARING ADDRESSING OPTIONS FOR BITORIENTED AND BYTEORIENTED INSTRUCTIONS EXTENDED INSTRUCTION SET ENABLED EXAMPLE INSTRUCTION ADDWF f d a Opcode 0010 01da ffff ffff When a 0 and f 60h The instruction executes in Direct Forced mode f is inter preted as a location in the Access RAM between 060h and 0FFh This is the same as locations 060h to 07Fh Bank 0 and F80h to FFFh Bank 15 of data memory Locations below 60h are not available in this addressing mode When a 0 and f 5Fh The instruction executes in Indexed Literal Offset mode f is interpreted as an offset to the address value in FSR2 The two are added together to obtain the address of the target register for the instruction The address can be anywhere in the data memory space Note that in this mode the correct syntax is now ADDWF k d where k is the same as f When a 1 all values of f The instruction executes in Direct mode also known as Direct Long mode f is inter preted as a location in one of the 16 banks of the data memory space The bank is designated by the Bank Select Register BSR The address can be in any implemented bank in the data memory space 000h 060h 100h F00h F80h FFFh Valid range 00h 60h 80h FFh Data Memory Access RAM Bank 0 Bank 1 through Bank 14 Bank 15 SFRs 000h 080h 100h F00h F80h FFFh Data Memory Bank 0 Bank 1 through Bank 14 Bank 15 SFRs FSR2H FSR2L ffffffff 001001da ffffffff 001001da 000h 080h 100h F00h F80h FFFh Data Memory Bank 0 Bank 1 through Bank 14 Bank 15 SFRs for f BSR 00000000 080h PIC18F2420252044204520 DS39631Epage 72 2008 Microchip Technology Inc 553 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM 00h to 5Fh are mapped Rather than containing just the contents of the bottom half of Bank 0 this mode maps the contents from Bank 0 and a userdefined window that can be located anywhere in the data memory space The value of FSR2 establishes the lower boundary of the addresses mapped into the window while the upper boundary is defined by FSR2 plus 95 5Fh Addresses in the Access RAM above 5Fh are mapped as previously described see Section 532 Access Bank An example of Access Bank remapping in this addressing mode is shown in Figure 510 Remapping of the Access Bank applies only to opera tions using the Indexed Literal Offset mode Operations that use the BSR Access RAM bit is 1 will continue to use Direct Addressing as before 56 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set These instructions are executed as described in Section 242 Extended Instruction Set FIGURE 510 REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Data Memory 000h 100h 200h F80h F00h FFFh Bank 1 Bank 15 Bank 2 through Bank 14 SFRs 05Fh ADDWF f d a FSR2HFSR2L 120h Locations in the region from the FSR2 Pointer 120h to the pointer plus 05Fh 17Fh are mapped to the bottom of the Access RAM 000h05Fh Locations in Bank 0 from 060h to 07Fh are mapped as usual to the middle half of the Access Bank Special Function Registers at F80h through FFFh are mapped to 80h through FFh as usual Bank 0 addresses below 5Fh can still be addressed by using the BSR Access Bank 00h 80h FFh 7Fh Bank 0 SFRs Bank 1 Window Bank 0 Bank 0 Window Example Situation 07Fh 120h 17Fh 5Fh Bank 1 2008 Microchip Technology Inc DS39631Epage 73 PIC18F2420252044204520 60 FLASH PROGRAM MEMORY The Flash program memory is readable writable and erasable during normal operation over the entire VDD range A read from program memory is executed on one byte at a time A write to program memory is executed on blocks of 32 bytes at a time Program memory is erased in blocks of 64 bytes at a time A bulk erase operation may not be issued from user code Writing or erasing program memory will cease instruction fetches until the operation is complete The program memory cannot be accessed during the write or erase therefore code cannot execute An internal programming timer terminates program memory writes and erases A value written to program memory does not need to be a valid instruction Executing a program memory location that forms an invalid instruction results in a NOP 61 Table Reads and Table Writes In order to read and write program memory there are two operations that allow the processor to move bytes between the program memory space and the data RAM Table Read TBLRD Table Write TBLWT The program memory space is 16 bits wide while the data RAM space is 8 bits wide Table reads and table writes move data between these two memory spaces through an 8bit register TABLAT Table read operations retrieve data from program memory and places it into the data RAM space Figure 61 shows the operation of a table read with program memory and data RAM Table write operations store data from the data memory space into holding registers in program memory The procedure to write the contents of the holding registers into program memory is detailed in Section 65 Writing to Flash Program Memory Figure 62 shows the operation of a table write with program memory and data RAM Table operations work with byte entities A table block containing data rather than program instructions is not required to be word aligned Therefore a table block can start and end at any byte address If a table write is being used to write executable code into program memory program instructions will need to be word aligned FIGURE 61 TABLE READ OPERATION Table Pointer1 Table Latch 8bit Program Memory TBLPTRH TBLPTRL TABLAT TBLPTRU Instruction TBLRD Note 1 The Table Pointer register points to a byte in program memory Program Memory TBLPTR PIC18F2420252044204520 DS39631Epage 74 2008 Microchip Technology Inc FIGURE 62 TABLE WRITE OPERATION 62 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions These include the EECON1 register EECON2 register TABLAT register TBLPTR registers 621 EECON1 AND EECON2 REGISTERS The EECON1 register Register 61 is the control register for memory accesses The EECON2 register is not a physical register it is used exclusively in the memory write and erase sequences Reading EECON2 will read all 0s The EEPGD control bit determines if the access will be a program or data EEPROM memory access When clear any subsequent operations will operate on the data EEPROM memory When set any subsequent operations will operate on the program memory The CFGS control bit determines if the access will be to the ConfigurationCalibration registers or to program memorydata EEPROM memory When set subsequent operations will operate on Configuration registers regardless of EEPGD see Section 230 Special Features of the CPU When clear memory selection access is determined by EEPGD The FREE bit when set will allow a program memory erase operation When FREE is set the erase operation is initiated on the next WR command When FREE is clear only writes are enabled The WREN bit when set will allow a write operation On powerup the WREN bit is clear The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete The WR control bit initiates write operations The bit cannot be cleared only set in software it is cleared in hardware at the completion of the write operation Table Pointer1 Table Latch 8bit TBLPTRH TBLPTRL TABLAT Program Memory TBLPTR TBLPTRU Instruction TBLWT Note1 The Table Pointer actually points to one of 32 holding registers the address of which is determined by TBLPTRL40 The process for physically writing data to the program memory array is discussed in Section 65 Writing to Flash Program Memory Holding Registers Program Memory Note During normal operation the WRERR is read as 1 This can indicate that a write operation was prematurely terminated by a Reset or a write operation was attempted improperly Note The EEIF interrupt flag bit PIR24 is set when the write is complete It must be cleared in software 2008 Microchip Technology Inc DS39631Epage 75 PIC18F2420252044204520 REGISTER 61 EECON1 EEPROM CONTROL REGISTER 1 RWx RWx U0 RW0 RWx RW0 RS0 RS0 EEPGD CFGS FREE WRERR1 WREN WR RD bit 7 bit 0 Legend S Settable bit cannot be cleared in software R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 EEPGD Flash Program or Data EEPROM Memory Select bit 1 Access Flash program memory 0 Access data EEPROM memory bit 6 CFGS Flash ProgramData EEPROM or Configuration Select bit 1 Access Configuration registers 0 Access Flash program or data EEPROM memory bit 5 Unimplemented Read as 0 bit 4 FREE Flash Row Erase Enable bit 1 Erase the program memory row addressed by TBLPTR on the next WR command cleared by completion of erase operation 0 Perform write only bit 3 WRERR Flash ProgramData EEPROM Error Flag bit1 1 A write operation is prematurely terminated any Reset during selftimed programming in normal operation or an improper write attempt 0 The write operation completed bit 2 WREN Flash ProgramData EEPROM Write Enable bit 1 Allows write cycles to Flash programdata EEPROM 0 Inhibits write cycles to Flash programdata EEPROM bit 1 WR Write Control bit 1 Initiates a data EEPROM erasewrite cycle or a program memory erase cycle or write cycle The operation is selftimed and the bit is cleared by hardware once write is complete The WR bit can only be set not cleared in software 0 Write cycle to the EEPROM is complete bit 0 RD Read Control bit 1 Initiates an EEPROM read Read takes one cycle RD is cleared in hardware The RD bit can only be set not cleared in software RD bit cannot be set when EEPGD 1 or CFGS 1 0 Does not initiate an EEPROM read Note 1 When a WRERR occurs the EEPGD and CFGS bits are not cleared This allows tracing of the error condition PIC18F2420252044204520 DS39631Epage 76 2008 Microchip Technology Inc 622 TABLAT TABLE LATCH REGISTER The Table Latch TABLAT is an 8bit register mapped into the SFR space The Table Latch register is used to hold 8bit data during data transfers between program memory and data RAM 623 TBLPTR TABLE POINTER REGISTER The Table Pointer TBLPTR register addresses a byte within the program memory The TBLPTR is comprised of three SFR registers Table Pointer Upper Byte Table Pointer High Byte and Table Pointer Low Byte TBLPTRUTBLPTRHTBLPTRL These three regis ters join to form a 22bit wide pointer The loworder 21 bits allow the device to address up to 2 Mbytes of program memory space The 22nd bit allows access to the device ID the user ID and the Configuration bits The Table Pointer register TBLPTR is used by the TBLRD and TBLWT instructions These instructions can update the TBLPTR in one of four ways based on the table operation These operations are shown in Table 61 These operations on the TBLPTR only affect the loworder 21 bits 624 TABLE POINTER BOUNDARIES TBLPTR is used in reads writes and erases of the Flash program memory When a TBLRD is executed all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT When a TBLWT is executed the five LSbs of the Table Pointer register TBLPTR40 determine which of the 32 program memory holding registers is written to When the timed write to program memory begins via the WR bit the 16 MSbs of the TBLPTR TBLPTR216 determine which program memory block of 32 bytes is written to For more detail see Section 65 Writing to Flash Program Memory When an erase of program memory is executed the 16 MSbs of the Table Pointer register TBLPTR216 point to the 64byte block that will be erased The Least Significant bits TBLPTR50 are ignored Figure 63 describes the relevant boundaries of TBLPTR based on Flash program memory operations TABLE 61 TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS FIGURE 63 TABLE POINTER BOUNDARIES BASED ON OPERATION Example Operation on Table Pointer TBLRD TBLWT TBLPTR is not modified TBLRD TBLWT TBLPTR is incremented after the readwrite TBLRD TBLWT TBLPTR is decremented after the readwrite TBLRD TBLWT TBLPTR is incremented before the readwrite 21 16 15 8 7 0 TABLE ERASE TABLE READ TBLPTR210 TBLPTRL TBLPTRH TBLPTRU TBLPTR216 TABLE WRITE TBLPTR215 2008 Microchip Technology Inc DS39631Epage 77 PIC18F2420252044204520 63 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM Table reads from program memory are performed one byte at a time TBLPTR points to a byte address in program space Executing TBLRD places the byte pointed to into TABLAT In addition TBLPTR can be modified automatically for the next table read operation The internal program memory is typically organized by words The Least Significant bit of the address selects between the high and low bytes of the word Figure 64 shows the interface between the internal program memory and the TABLAT FIGURE 64 READS FROM FLASH PROGRAM MEMORY EXAMPLE 61 READING A FLASH PROGRAM MEMORY WORD Even Byte Address Program Memory Odd Byte Address TBLRD TABLAT TBLPTR xxxxx1 FETCH Instruction Register IR Read Register TBLPTR xxxxx0 MOVLW CODEADDRUPPER Load TBLPTR with the base MOVWF TBLPTRU address of the word MOVLW CODEADDRHIGH MOVWF TBLPTRH MOVLW CODEADDRLOW MOVWF TBLPTRL READWORD TBLRD read into TABLAT and increment MOVF TABLAT W get data MOVWF WORDEVEN TBLRD read into TABLAT and increment MOVFW TABLAT W get data MOVF WORDODD PIC18F2420252044204520 DS39631Epage 78 2008 Microchip Technology Inc 64 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes Only through the use of an external programmer or through ICSP control can larger blocks of program memory be bulk erased Word erase in the Flash array is not supported When initiating an erase sequence from the micro controller itself a block of 64 bytes of program memory is erased The Most Significant 16 bits of the TBLPTR216 point to the block being erased TBLPTR50 are ignored The EECON1 register commands the erase operation The EEPGD bit must be set to point to the Flash pro gram memory The WREN bit must be set to enable write operations The FREE bit is set to select an erase operation For protection the write initiate sequence for EECON2 must be used A long write is necessary for erasing the internal Flash Instruction execution is halted while in a long write cycle The long write will be terminated by the internal programming timer 641 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is 1 Load Table Pointer register with address of row being erased 2 Set the EECON1 register for the erase operation set EEPGD bit to point to program memory clear the CFGS bit to access program memory set WREN bit to enable writes set FREE bit to enable the erase 3 Disable interrupts 4 Write 55h to EECON2 5 Write 0AAh to EECON2 6 Set the WR bit This will begin the row erase cycle 7 The CPU will stall for duration of the erase about 2 ms using internal timer 8 Reenable interrupts EXAMPLE 62 ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODEADDRUPPER load TBLPTR with the base MOVWF TBLPTRU address of the memory block MOVLW CODEADDRHIGH MOVWF TBLPTRH MOVLW CODEADDRLOW MOVWF TBLPTRL ERASEROW BSF EECON1 EEPGD point to Flash program memory BCF EECON1 CFGS access Flash program memory BSF EECON1 WREN enable write to memory BSF EECON1 FREE enable Row Erase operation BCF INTCON GIE disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 write 55h MOVLW 0AAh MOVWF EECON2 write 0AAh BSF EECON1 WR start erase CPU stall BSF INTCON GIE reenable interrupts 2008 Microchip Technology Inc DS39631Epage 79 PIC18F2420252044204520 65 Writing to Flash Program Memory The minimum programming block is 16 words or 32 bytes Word or byte programming is not supported Table writes are used internally to load the holding registers needed to program the Flash memory There are 32 holding registers used by the table writes for programming Since the Table Latch TABLAT is only a single byte the TBLWT instruction may need to be executed 32 times for each programming operation All of the table write operations will essentially be short writes because only the holding registers are written At the end of updating the 32 holding registers the EECON1 register must be written to in order to start the programming operation with a long write The long write is necessary for programming the inter nal Flash Instruction execution is halted while in a long write cycle The long write will be terminated by the internal programming timer The EEPROM onchip timer controls the write time The writeerase voltages are generated by an onchip charge pump rated to operate over the voltage range of the device FIGURE 65 TABLE WRITES TO FLASH PROGRAM MEMORY 651 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be 1 Read 64 bytes into RAM 2 Update data values in RAM as necessary 3 Load Table Pointer register with address being erased 4 Execute the row erase procedure 5 Load Table Pointer register with address of first byte being written 6 Write the 32 bytes into the holding registers with autoincrement 7 Set the EECON1 register for the write operation set EEPGD bit to point to program memory clear the CFGS bit to access program memory set WREN to enable byte writes 8 Disable interrupts 9 Write 55h to EECON2 10 Write 0AAh to EECON2 11 Set the WR bit This will begin the write cycle 12 The CPU will stall for duration of the write about 2 ms using internal timer 13 Reenable interrupts 14 Verify the memory table read This procedure will require about 6 ms to update one row of 64 bytes of memory An example of the required code is given in Example 63 Note The default value of the holding registers on device Resets and after write operations is FFh A write of FFh to a holding register does not modify that byte This means indi vidual bytes of program memory may be modified provided that the change does not attempt to change any bit from a 0 to a 1 When modifying individual bytes it is not necessary to load all 32 holding registers before executing a write operation TABLAT TBLPTR xxxx3F TBLPTR xxxxx1 TBLPTR xxxxx0 Write Register TBLPTR xxxxx2 Program Memory Holding Register Holding Register Holding Register Holding Register 8 8 8 8 Note Before setting the WR bit the Table Pointer address needs to be within the intended address range of the 32 bytes in the holding register PIC18F2420252044204520 DS39631Epage 80 2008 Microchip Technology Inc EXAMPLE 63 WRITING TO FLASH PROGRAM MEMORY MOVLW D64 number of bytes in erase block MOVWF COUNTER MOVLW BUFFERADDRHIGH point to buffer MOVWF FSR0H MOVLW BUFFERADDRLOW MOVWF FSR0L MOVLW CODEADDRUPPER Load TBLPTR with the base MOVWF TBLPTRU address of the memory block MOVLW CODEADDRHIGH MOVWF TBLPTRH MOVLW CODEADDRLOW MOVWF TBLPTRL READBLOCK TBLRD read into TABLAT and inc MOVF TABLAT W get data MOVWF POSTINC0 store data DECFSZ COUNTER done BRA READBLOCK repeat MODIFYWORD MOVLW DATAADDRHIGH point to buffer MOVWF FSR0H MOVLW DATAADDRLOW MOVWF FSR0L MOVLW NEWDATALOW update buffer word MOVWF POSTINC0 MOVLW NEWDATAHIGH MOVWF INDF0 ERASEBLOCK MOVLW CODEADDRUPPER load TBLPTR with the base MOVWF TBLPTRU address of the memory block MOVLW CODEADDRHIGH MOVWF TBLPTRH MOVLW CODEADDRLOW MOVWF TBLPTRL BSF EECON1 EEPGD point to Flash program memory BCF EECON1 CFGS access Flash program memory BSF EECON1 WREN enable write to memory BSF EECON1 FREE enable Row Erase operation BCF INTCON GIE disable interrupts MOVLW 55h Required MOVWF EECON2 write 55h Sequence MOVLW 0AAh MOVWF EECON2 write 0AAh BSF EECON1 WR start erase CPU stall BSF INTCON GIE reenable interrupts TBLRD dummy read decrement MOVLW BUFFERADDRHIGH point to buffer MOVWF FSR0H MOVLW BUFFERADDRLOW MOVWF FSR0L WRITEBUFFERBACK MOVLW D32 number of bytes in holding register MOVWF COUNTER WRITEBYTETOHREGS MOVFF POSTINC0 WREG get low byte of buffer data MOVWF TABLAT present data to table latch TBLWT write data perform a short write to internal TBLWT holding register DECFSZ COUNTER loop until buffers are full BRA WRITEWORDTOHREGS 2008 Microchip Technology Inc DS39631Epage 81 PIC18F2420252044204520 EXAMPLE 63 WRITING TO FLASH PROGRAM MEMORY CONTINUED 652 WRITE VERIFY Depending on the application good programming practice may dictate that the value written to the memory should be verified against the original value This should be used in applications where excessive writes can stress bits near the specification limit 653 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event such as loss of power or an unexpected Reset the memory location just programmed should be verified and repro grammed if needed If the write operation is interrupted by a MCLR Reset or a WDT Timeout Reset during normal operation the user can check the WRERR bit and rewrite the locations as needed 654 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory the write initiate sequence must also be followed See Section 230 Special Features of the CPU for more detail 66 Flash Program Operation During Code Protection See Section 235 Program Verification and Code Protection for details on code protection of Flash program memory TABLE 62 REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY PROGRAMMEMORY BSF EECON1 EEPGD point to Flash program memory BCF EECON1 CFGS access Flash program memory BSF EECON1 WREN enable write to memory BCF INTCON GIE disable interrupts MOVLW 55h Required MOVWF EECON2 write 55h Sequence MOVLW 0AAh MOVWF EECON2 write 0AAh BSF EECON1 WR start program CPU stall BSF INTCON GIE reenable interrupts BCF EECON1 WREN disable write to memory Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TBLPTRU bit 21 Program Memory Table Pointer Upper Byte TBLPTR2016 49 TBLPTRH Program Memory Table Pointer High Byte TBLPTR158 49 TBLPTRL Program Memory Table Pointer Low Byte TBLPTR70 49 TABLAT Program Memory Table Latch 49 INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 EECON2 EEPROM Control Register 2 not a physical register 51 EECON1 EEPGD CFGS FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 Legend unimplemented read as 0 Shaded cells are not used during FlashEEPROM access PIC18F2420252044204520 DS39631Epage 82 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 83 PIC18F2420252044204520 70 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array separate from the data RAM and program memory that is used for longterm storage of program data It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers SFRs The EEPROM is readable and writable during normal operation over the entire VDD range Five SFRs are used to read and write to the data EEPROM as well as the program memory They are EECON1 EECON2 EEDATA EEADR The data EEPROM allows byte read and write When interfacing to the data memory block EEDATA holds the 8bit data for readwrite and the EEADR register holds the address of the EEPROM location being accessed The EEPROM data memory is rated for high erasewrite cycle endurance A byte write automatically erases the location and writes the new data erasebeforewrite The write time is controlled by an onchip timer it will vary with voltage and temperature as well as from chip to chip Please refer to parameter D122 Table 261 in Section 260 Electrical Characteristics for exact limits 71 EEADR Register The EEADR register is used to address the data EEPROM for read and write operations The 8bit range of the register can address a memory range of 256 bytes 00h to FFh 72 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers EECON1 and EECON2 These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM The EECON1 register Register 71 is the control register for data and program memory access Control bit EEPGD determines if the access will be to program or data EEPROM memory When clear operations will access the data EEPROM memory When set program memory is accessed Control bit CFGS determines if the access will be to the Configuration registers or to program memorydata EEPROM memory When set subsequent operations access Configuration registers When CFGS is clear the EEPGD bit selects either program Flash or data EEPROM memory The WREN bit when set will allow a write operation On powerup the WREN bit is clear The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete The WR control bit initiates write operations The bit can be set but not cleared in software It is only cleared in hardware at the completion of the write operation Control bits RD and WR start read and erasewrite operations respectively These bits are set by firmware and cleared by hardware at the completion of the operation The RD bit cannot be set when accessing program memory EEPGD 1 Program memory is read using table read instructions See Section 61 Table Reads and Table Writes regarding table reads The EECON2 register is not a physical register It is used exclusively in the memory write and erase sequences Reading EECON2 will read all 0s Note During normal operation the WRERR may read as 1 This can indicate that a write operation was prematurely termi nated by a Reset or a write operation was attempted improperly Note The EEIF interrupt flag bit PIR24 is set when the write is complete It must be cleared in software PIC18F2420252044204520 DS39631Epage 84 2008 Microchip Technology Inc REGISTER 71 EECON1 EEPROM CONTROL REGISTER 1 RWx RWx U0 RW0 RWx RW0 RS0 RS0 EEPGD CFGS FREE WRERR1 WREN WR RD bit 7 bit 0 Legend S Settable bit cannot be cleared in software R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 EEPGD Flash Program or Data EEPROM Memory Select bit 1 Access Flash program memory 0 Access data EEPROM memory bit 6 CFGS Flash ProgramData EEPROM or Configuration Select bit 1 Access Configuration registers 0 Access Flash program or data EEPROM memory bit 5 Unimplemented Read as 0 bit 4 FREE Flash Row Erase Enable bit 1 Erase the program memory row addressed by TBLPTR on the next WR command cleared by completion of erase operation 0 Perform write only bit 3 WRERR Flash ProgramData EEPROM Error Flag bit1 1 A write operation is prematurely terminated any Reset during selftimed programming in normal operation or an improper write attempt 0 The write operation completed bit 2 WREN Flash ProgramData EEPROM Write Enable bit 1 Allows write cycles to Flash programdata EEPROM 0 Inhibits write cycles to Flash programdata EEPROM bit 1 WR Write Control bit 1 Initiates a data EEPROM erasewrite cycle or a program memory erase cycle or write cycle The operation is selftimed and the bit is cleared by hardware once write is complete The WR bit can only be set not cleared in software 0 Write cycle to the EEPROM is complete bit 0 RD Read Control bit 1 Initiates an EEPROM read Read takes one cycle RD is cleared in hardware The RD bit can only be set not cleared in software RD bit cannot be set when EEPGD 1 or CFGS 1 0 Does not initiate an EEPROM read Note 1 When a WRERR occurs the EEPGD and CFGS bits are not cleared This allows tracing of the error condition 2008 Microchip Technology Inc DS39631Epage 85 PIC18F2420252044204520 73 Reading the Data EEPROM Memory To read a data memory location the user must write the address to the EEADR register clear the EEPGD con trol bit EECON17 and then set control bit RD EECON10 The data is available on the very next instruction cycle therefore the EEDATA register can be read by the next instruction EEDATA will hold this value until another read operation or until it is written to by the user during a write operation The basic process is shown in Example 71 74 Writing to the Data EEPROM Memory To write an EEPROM data location the address must first be written to the EEADR register and the data written to the EEDATA register The sequence in Example 72 must be followed to initiate the write cycle The write will not begin if this sequence is not exactly followed write 55h to EECON2 write 0AAh to EECON2 then set WR bit for each byte It is strongly recommended that interrupts be disabled during this code segment Additionally the WREN bit in EECON1 must be set to enable writes This mechanism prevents accidental writes to data EEPROM due to unexpected code exe cution ie runaway programs The WREN bit should be kept clear at all times except when updating the EEPROM The WREN bit is not cleared by hardware After a write sequence has been initiated EECON1 EEADR and EEDATA cannot be modified The WR bit will be inhibited from being set unless the WREN bit is set Both WR and WREN cannot be set with the same instruction At the completion of the write cycle the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit EEIF is set The user may either enable this interrupt or poll this bit EEIF must be cleared by software 75 Write Verify Depending on the application good programming practice may dictate that the value written to the memory should be verified against the original value This should be used in applications where excessive writes can stress bits near the specification limit EXAMPLE 71 DATA EEPROM READ EXAMPLE 72 DATA EEPROM WRITE MOVLW DATAEEADDR MOVWF EEADR Data Memory Address to read BCF EECON1 EEPGD Point to DATA memory BCF EECON1 CFGS Access EEPROM BSF EECON1 RD EEPROM Read MOVF EEDATA W W EEDATA MOVLW DATAEEADDR MOVWF EEADR Data Memory Address to write MOVLW DATAEEDATA MOVWF EEDATA Data Memory Value to write BCF EECON1 EEPGD Point to DATA memory BCF EECON1 CFGS Access EEPROM BSF EECON1 WREN Enable writes BCF INTCON GIE Disable Interrupts MOVLW 55h Required MOVWF EECON2 Write 55h Sequence MOVLW 0AAh MOVWF EECON2 Write 0AAh BSF EECON1 WR Set WR bit to begin write BSF INTCON GIE Enable Interrupts User code execution BCF EECON1 WREN Disable writes on write complete EEIF set PIC18F2420252044204520 DS39631Epage 86 2008 Microchip Technology Inc 76 Operation During CodeProtect Data EEPROM memory has its own codeprotect bits in Configuration Words External read and write operations are disabled if code protection is enabled The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the codeprotect Configuration bit Refer to Section 230 Special Features of the CPU for additional information 77 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory To protect against spuri ous EEPROM writes various mechanisms have been implemented On powerup the WREN bit is cleared In addition writes to the EEPROM are blocked during the Powerup Timer period TPWRT parameter 33 The write initiate sequence and the WREN bit together help prevent an accidental write during brownout power glitch or software malfunction 78 Using the Data EEPROM The data EEPROM is a highendurance byte addressable array that has been optimized for the storage of frequently changing information eg program variables or other data that are updated often Frequently changing values will typically be updated more often than specification D124 If this is not the case an array refresh must be performed For this reason variables that change infrequently such as constants IDs calibration etc should be stored in Flash program memory A simple data EEPROM refresh routine is shown in Example 73 EXAMPLE 73 DATA EEPROM REFRESH ROUTINE Note If data EEPROM is only used to store constants andor data that changes rarely an array refresh is likely not required See specification D124 CLRF EEADR Start at address 0 BCF EECON1 CFGS Set for memory BCF EECON1 EEPGD Set for Data EEPROM BCF INTCON GIE Disable interrupts BSF EECON1 WREN Enable writes Loop Loop to refresh array BSF EECON1 RD Read current address MOVLW 55h MOVWF EECON2 Write 55h MOVLW 0AAh MOVWF EECON2 Write 0AAh BSF EECON1 WR Set WR bit to begin write BTFSC EECON1 WR Wait for write to complete BRA 2 INCFSZ EEADR F Increment address BRA LOOP Not zero do it again BCF EECON1 WREN Disable writes BSF INTCON GIE Enable interrupts 2008 Microchip Technology Inc DS39631Epage 87 PIC18F2420252044204520 TABLE 71 REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 EEADR EEPROM Address Register 51 EEDATA EEPROM Data Register 51 EECON2 EEPROM Control Register 2 not a physical register 51 EECON1 EEPGD CFGS FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 Legend unimplemented read as 0 Shaded cells are not used during FlashEEPROM access PIC18F2420252044204520 DS39631Epage 88 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 89 PIC18F2420252044204520 80 8 x 8 HARDWARE MULTIPLIER 81 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU The multiplier performs an unsigned operation and yields a 16bit result that is stored in the product register pair PRODHPRODL The multipliers operation does not affect any flags in the STATUS register Making multiplication a hardware operation allows it to be completed in a single instruction cycle This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applica tions previously reserved for digital signal processors A comparison of various hardware and software multiply operations along with the savings in memory and execution time is shown in Table 81 82 Operation Example 81 shows the instruction sequence for an 8 x 8 unsigned multiplication Only one instruction is required when one of the arguments is already loaded in the WREG register Example 82 shows the sequence to do an 8 x 8 signed multiplication To account for the sign bits of the argu ments each arguments Most Significant bit MSb is tested and the appropriate subtractions are done EXAMPLE 81 8 x 8 UNSIGNED MULTIPLY ROUTINE EXAMPLE 82 8 x 8 SIGNED MULTIPLY ROUTINE TABLE 81 PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS MOVF ARG1 W MULWF ARG2 ARG1 ARG2 PRODHPRODL MOVF ARG1 W MULWF ARG2 ARG1 ARG2 PRODHPRODL BTFSC ARG2 SB Test Sign Bit SUBWF PRODH F PRODH PRODH ARG1 MOVF ARG2 W BTFSC ARG1 SB Test Sign Bit SUBWF PRODH F PRODH PRODH ARG2 Routine Multiply Method Program Memory Words Cycles Max Time 40 MHz 10 MHz 4 MHz 8 x 8 unsigned Without hardware multiply 13 69 69 μs 276 μs 69 μs Hardware multiply 1 1 100 ns 400 ns 1 μs 8 x 8 signed Without hardware multiply 33 91 91 μs 364 μs 91 μs Hardware multiply 6 6 600 ns 24 μs 6 μs 16 x 16 unsigned Without hardware multiply 21 242 242 μs 968 μs 242 μs Hardware multiply 28 28 28 μs 112 μs 28 μs 16 x 16 signed Without hardware multiply 52 254 254 μs 1026 μs 254 μs Hardware multiply 35 40 40 μs 160 μs 40 μs PIC18F2420252044204520 DS39631Epage 90 2008 Microchip Technology Inc Example 83 shows the sequence to do a 16 x 16 unsigned multiplication Equation 81 shows the algorithm that is used The 32bit result is stored in four registers RES30 EQUATION 81 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM EXAMPLE 83 16 x 16 UNSIGNED MULTIPLY ROUTINE Example 84 shows the sequence to do a 16 x 16 signed multiply Equation 82 shows the algorithm used The 32bit result is stored in four registers RES30 To account for the sign bits of the argu ments the MSb for each argument pair is tested and the appropriate subtractions are done EQUATION 82 16 x 16 SIGNED MULTIPLICATION ALGORITHM EXAMPLE 84 16 x 16 SIGNED MULTIPLY ROUTINE RES30 ARG1HARG1L ARG2HARG2L ARG1H ARG2H 216 ARG1H ARG2L 28 ARG1L ARG2H 28 ARG1L ARG2L MOVF ARG1L W MULWF ARG2L ARG1L ARG2L PRODHPRODL MOVFF PRODH RES1 MOVFF PRODL RES0 MOVF ARG1H W MULWF ARG2H ARG1H ARG2H PRODHPRODL MOVFF PRODH RES3 MOVFF PRODL RES2 MOVF ARG1L W MULWF ARG2H ARG1L ARG2H PRODHPRODL MOVF PRODL W ADDWF RES1 F Add cross MOVF PRODH W products ADDWFC RES2 F CLRF WREG ADDWFC RES3 F MOVF ARG1H W MULWF ARG2L ARG1H ARG2L PRODHPRODL MOVF PRODL W ADDWF RES1 F Add cross MOVF PRODH W products ADDWFC RES2 F CLRF WREG ADDWFC RES3 F RES30 ARG1HARG1L ARG2HARG2L ARG1H ARG2H 216 ARG1H ARG2L 28 ARG1L ARG2H 28 ARG1L ARG2L 1 ARG2H7 ARG1HARG1L 216 1 ARG1H7 ARG2HARG2L 216 MOVF ARG1L W MULWF ARG2L ARG1L ARG2L PRODHPRODL MOVFF PRODH RES1 MOVFF PRODL RES0 MOVF ARG1H W MULWF ARG2H ARG1H ARG2H PRODHPRODL MOVFF PRODH RES3 MOVFF PRODL RES2 MOVF ARG1L W MULWF ARG2H ARG1L ARG2H PRODHPRODL MOVF PRODL W ADDWF RES1 F Add cross MOVF PRODH W products ADDWFC RES2 F CLRF WREG ADDWFC RES3 F MOVF ARG1H W MULWF ARG2L ARG1H ARG2L PRODHPRODL MOVF PRODL W ADDWF RES1 F Add cross MOVF PRODH W products ADDWFC RES2 F CLRF WREG ADDWFC RES3 F BTFSS ARG2H 7 ARG2HARG2L neg BRA SIGNARG1 no check ARG1 MOVF ARG1L W SUBWF RES2 MOVF ARG1H W SUBWFB RES3 SIGNARG1 BTFSS ARG1H 7 ARG1HARG1L neg BRA CONTCODE no done MOVF ARG2L W SUBWF RES2 MOVF ARG2H W SUBWFB RES3 CONTCODE 2008 Microchip Technology Inc DS39631Epage 91 PIC18F2420252044204520 90 INTERRUPTS The PIC18F2420252044204520 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a highpriority level or a lowpriority level The highpriority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h Highpriority interrupt events will interrupt any lowpriority interrupts that may be in progress There are ten registers which are used to control interrupt operation These registers are RCON INTCON INTCON2 INTCON3 PIR1 PIR2 PIE1 PIE2 IPR1 IPR2 It is recommended that the Microchip header files sup plied with MPLAB IDE be used for the symbolic bit names in these registers This allows the assembler compiler to automatically take care of the placement of these bits within the specified register In general interrupt sources have three bits to control their operation They are Flag bit to indicate that an interrupt event occurred Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit RCON7 When interrupt priority is enabled there are two bits which enable interrupts globally Setting the GIEH bit INTCON7 enables all interrupts that have the priority bit set high priority Setting the GIEL bit INTCON6 enables all interrupts that have the priority bit cleared low priority When the interrupt flag enable bit and appropriate global interrupt enable bit are set the interrupt will vec tor immediately to address 0008h or 0018h depending on the priority bit setting Individual interrupts can be disabled through their corresponding enable bits When the IPEN bit is cleared default state the interrupt priority feature is disabled and interrupts are compatible with PIC midrange devices In Compati bility mode the interrupt priority bits for each source have no effect INTCON6 is the PEIE bit which enablesdisables all peripheral interrupt sources INTCON7 is the GIE bit which enablesdisables all interrupt sources All interrupts branch to address 0008h in Compatibility mode When an interrupt is responded to the global interrupt enable bit is cleared to disable further interrupts If the IPEN bit is cleared this is the GIE bit If interrupt priority levels are used this will be either the GIEH or GIEL bit Highpriority interrupt sources can interrupt a low priority interrupt Lowpriority interrupts are not processed while highpriority interrupts are in progress The return address is pushed onto the stack and the PC is loaded with the interrupt vector address 0008h or 0018h Once in the Interrupt Service Routine the sources of the interrupt can be determined by polling the interrupt flag bits The interrupt flag bits must be cleared in software before reenabling interrupts to avoid recursive interrupts The return from interrupt instruction RETFIE exits the interrupt routine and sets the GIE bit GIEH or GIEL if priority levels are used which reenables interrupts For external interrupt events such as the INTx pins or the PORTB input change interrupt the interrupt latency will be three to four instruction cycles The exact latency is the same for one or twocycle instructions Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit Note Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled Doing so may cause erratic microcontroller behavior PIC18F2420252044204520 DS39631Epage 92 2008 Microchip Technology Inc FIGURE 91 PIC18 INTERRUPT LOGIC TMR0IE GIEGIEH PEIEGIEL Wakeup if in Interrupt to CPU Vector to Location 0008h INT2IF INT2IE INT2IP INT1IF INT1IE INT1IP TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP IPEN TMR0IF TMR0IP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP RBIF RBIE RBIP INT0IF INT0IE PEIEGIE Interrupt to CPU Vector to Location IPEN IPEN 0018h SSPIF SSPIE SSPIP SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts ADIF ADIE ADIP HighPriority Interrupt Generation LowPriority Interrupt Generation RCIF RCIE RCIP Additional Peripheral Interrupts Idle or Sleep modes GIEGIEH 2008 Microchip Technology Inc DS39631Epage 93 PIC18F2420252044204520 91 INTCON Registers The INTCON registers are readable and writable registers which contain various enable priority and flag bits Note Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling REGISTER 91 INTCON INTERRUPT CONTROL REGISTER RW0 RW0 RW0 RW0 RW0 RW0 RW0 RWx GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF1 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 GIEGIEH Global Interrupt Enable bit When IPEN 0 1 Enables all unmasked interrupts 0 Disables all interrupts When IPEN 1 1 Enables all highpriority interrupts 0 Disables all interrupts bit 6 PEIEGIEL Peripheral Interrupt Enable bit When IPEN 0 1 Enables all unmasked peripheral interrupts 0 Disables all peripheral interrupts When IPEN 1 1 Enables all lowpriority peripheral interrupts 0 Disables all lowpriority peripheral interrupts bit 5 TMR0IE TMR0 Overflow Interrupt Enable bit 1 Enables the TMR0 overflow interrupt 0 Disables the TMR0 overflow interrupt bit 4 INT0IE INT0 External Interrupt Enable bit 1 Enables the INT0 external interrupt 0 Disables the INT0 external interrupt bit 3 RBIE RB Port Change Interrupt Enable bit 1 Enables the RB port change interrupt 0 Disables the RB port change interrupt bit 2 TMR0IF TMR0 Overflow Interrupt Flag bit 1 TMR0 register has overflowed must be cleared in software 0 TMR0 register did not overflow bit 1 INT0IF INT0 External Interrupt Flag bit 1 The INT0 external interrupt occurred must be cleared in software 0 The INT0 external interrupt did not occur bit 0 RBIF RB Port Change Interrupt Flag bit1 1 At least one of the RB74 pins changed state must be cleared in software 0 None of the RB74 pins have changed state Note 1 A mismatch condition will continue to set this bit Reading PORTB will end the mismatch condition and allow the bit to be cleared PIC18F2420252044204520 DS39631Epage 94 2008 Microchip Technology Inc REGISTER 92 INTCON2 INTERRUPT CONTROL REGISTER 2 RW1 RW1 RW1 RW1 U0 RW1 U0 RW1 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP RBIP bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 RBPU PORTB Pullup Enable bit 1 All PORTB pullups are disabled 0 PORTB pullups are enabled by individual port latch values bit 6 INTEDG0 External Interrupt 0 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge bit 5 INTEDG1 External Interrupt 1 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge bit 4 INTEDG2 External Interrupt 2 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge bit 3 Unimplemented Read as 0 bit 2 TMR0IP TMR0 Overflow Interrupt Priority bit 1 High priority 0 Low priority bit 1 Unimplemented Read as 0 bit 0 RBIP RB Port Change Interrupt Priority bit 1 High priority 0 Low priority Note Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling 2008 Microchip Technology Inc DS39631Epage 95 PIC18F2420252044204520 REGISTER 93 INTCON3 INTERRUPT CONTROL REGISTER 3 RW1 RW1 U0 RW0 RW0 U0 RW0 RW0 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 INT2IP INT2 External Interrupt Priority bit 1 High priority 0 Low priority bit 6 INT1IP INT1 External Interrupt Priority bit 1 High priority 0 Low priority bit 5 Unimplemented Read as 0 bit 4 INT2IE INT2 External Interrupt Enable bit 1 Enables the INT2 external interrupt 0 Disables the INT2 external interrupt bit 3 INT1IE INT1 External Interrupt Enable bit 1 Enables the INT1 external interrupt 0 Disables the INT1 external interrupt bit 2 Unimplemented Read as 0 bit 1 INT2IF INT2 External Interrupt Flag bit 1 The INT2 external interrupt occurred must be cleared in software 0 The INT2 external interrupt did not occur bit 0 INT1IF INT1 External Interrupt Flag bit 1 The INT1 external interrupt occurred must be cleared in software 0 The INT1 external interrupt did not occur Note Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling PIC18F2420252044204520 DS39631Epage 96 2008 Microchip Technology Inc 92 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts Due to the number of peripheral interrupt sources there are two Peripheral Interrupt Request Flag registers PIR1 and PIR2 Note 1 Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit GIE INTCON7 2 User software should ensure the appropri ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt REGISTER 94 PIR1 PERIPHERAL INTERRUPT REQUEST FLAG REGISTER 1 RW0 RW0 R0 R0 RW0 RW0 RW0 RW0 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 PSPIF Parallel Slave Port ReadWrite Interrupt Flag bit1 1 A read or a write operation has taken place must be cleared in software 0 No read or write has occurred bit 6 ADIF AD Converter Interrupt Flag bit 1 An AD conversion completed must be cleared in software 0 The AD conversion is not complete bit 5 RCIF EUSART Receive Interrupt Flag bit 1 The EUSART receive buffer RCREG is full cleared when RCREG is read 0 The EUSART receive buffer is empty bit 4 TXIF EUSART Transmit Interrupt Flag bit 1 The EUSART transmit buffer TXREG is empty cleared when TXREG is written 0 The EUSART transmit buffer is full bit 3 SSPIF Master Synchronous Serial Port Interrupt Flag bit 1 The transmissionreception is complete must be cleared in software 0 Waiting to transmitreceive bit 2 CCP1IF CCP1 Interrupt Flag bit Capture mode 1 A TMR1 register capture occurred must be cleared in software 0 No TMR1 register capture occurred Compare mode 1 A TMR1 register compare match occurred must be cleared in software 0 No TMR1 register compare match occurred PWM mode Unused in this mode bit 1 TMR2IF TMR2 to PR2 Match Interrupt Flag bit 1 TMR2 to PR2 match occurred must be cleared in software 0 No TMR2 to PR2 match occurred bit 0 TMR1IF TMR1 Overflow Interrupt Flag bit 1 TMR1 register overflowed must be cleared in software 0 TMR1 register did not overflow Note 1 This bit is unimplemented on 28pin devices and will read as 0 2008 Microchip Technology Inc DS39631Epage 97 PIC18F2420252044204520 REGISTER 95 PIR2 PERIPHERAL INTERRUPT REQUEST FLAG REGISTER 2 RW0 RW0 U0 RW0 RW0 RW0 RW0 RW0 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 OSCFIF Oscillator Fail Interrupt Flag bit 1 Device oscillator failed clock input has changed to INTOSC must be cleared in software 0 Device clock operating bit 6 CMIF Comparator Interrupt Flag bit 1 Comparator input has changed must be cleared in software 0 Comparator input has not changed bit 5 Unimplemented Read as 0 bit 4 EEIF Data EEPROMFlash Write Operation Interrupt Flag bit 1 The write operation is complete must be cleared in software 0 The write operation is not complete or has not been started bit 3 BCLIF Bus Collision Interrupt Flag bit 1 A bus collision occurred must be cleared in software 0 No bus collision occurred bit 2 HLVDIF HighLowVoltage Detect Interrupt Flag bit 1 A highlowvoltage condition occurred direction determined by VDIRMAG bit HLVDCON7 0 A highlowvoltage condition has not occurred bit 1 TMR3IF TMR3 Overflow Interrupt Flag bit 1 TMR3 register overflowed must be cleared in software 0 TMR3 register did not overflow bit 0 CCP2IF CCP2 Interrupt Flag bit Capture mode 1 A TMR1 register capture occurred must be cleared in software 0 No TMR1 register capture occurred Compare mode 1 A TMR1 register compare match occurred must be cleared in software 0 No TMR1 register compare match occurred PWM mode Unused in this mode PIC18F2420252044204520 DS39631Epage 98 2008 Microchip Technology Inc 93 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts Due to the number of periph eral interrupt sources there are two Peripheral Interrupt Enable registers PIE1 and PIE2 When IPEN 0 the PEIE bit must be set to enable any of these peripheral interrupts REGISTER 96 PIE1 PERIPHERAL INTERRUPT ENABLE REGISTER 1 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 PSPIE Parallel Slave Port ReadWrite Interrupt Enable bit1 1 Enables the PSP readwrite interrupt 0 Disables the PSP readwrite interrupt bit 6 ADIE AD Converter Interrupt Enable bit 1 Enables the AD interrupt 0 Disables the AD interrupt bit 5 RCIE EUSART Receive Interrupt Enable bit 1 Enables the EUSART receive interrupt 0 Disables the EUSART receive interrupt bit 4 TXIE EUSART Transmit Interrupt Enable bit 1 Enables the EUSART transmit interrupt 0 Disables the EUSART transmit interrupt bit 3 SSPIE Master Synchronous Serial Port Interrupt Enable bit 1 Enables the MSSP interrupt 0 Disables the MSSP interrupt bit 2 CCP1IE CCP1 Interrupt Enable bit 1 Enables the CCP1 interrupt 0 Disables the CCP1 interrupt bit 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit 1 Enables the TMR2 to PR2 match interrupt 0 Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE TMR1 Overflow Interrupt Enable bit 1 Enables the TMR1 overflow interrupt 0 Disables the TMR1 overflow interrupt Note 1 This bit is unimplemented on 28pin devices and will read as 0 2008 Microchip Technology Inc DS39631Epage 99 PIC18F2420252044204520 REGISTER 97 PIE2 PERIPHERAL INTERRUPT ENABLE REGISTER 2 RW0 RW0 U0 RW0 RW0 RW0 RW0 RW0 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 OSCFIE Oscillator Fail Interrupt Enable bit 1 Enabled 0 Disabled bit 6 CMIE Comparator Interrupt Enable bit 1 Enabled 0 Disabled bit 5 Unimplemented Read as 0 bit 4 EEIE Data EEPROMFlash Write Operation Interrupt Enable bit 1 Enabled 0 Disabled bit 3 BCLIE Bus Collision Interrupt Enable bit 1 Enabled 0 Disabled bit 2 HLVDIE HighLowVoltage Detect Interrupt Enable bit 1 Enabled 0 Disabled bit 1 TMR3IE TMR3 Overflow Interrupt Enable bit 1 Enabled 0 Disabled bit 0 CCP2IE CCP2 Interrupt Enable bit 1 Enabled 0 Disabled PIC18F2420252044204520 DS39631Epage 100 2008 Microchip Technology Inc 94 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts Due to the number of periph eral interrupt sources there are two Peripheral Interrupt Priority registers IPR1 and IPR2 Using the priority bits requires that the Interrupt Priority Enable IPEN bit be set REGISTER 98 IPR1 PERIPHERAL INTERRUPT PRIORITY REGISTER 1 RW1 RW1 RW1 RW1 RW1 RW1 RW1 RW1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 PSPIP Parallel Slave Port ReadWrite Interrupt Priority bit1 1 High priority 0 Low priority bit 6 ADIP AD Converter Interrupt Priority bit 1 High priority 0 Low priority bit 5 RCIP EUSART Receive Interrupt Priority bit 1 High priority 0 Low priority bit 4 TXIP EUSART Transmit Interrupt Priority bit 1 High priority 0 Low priority bit 3 SSPIP Master Synchronous Serial Port Interrupt Priority bit 1 High priority 0 Low priority bit 2 CCP1IP CCP1 Interrupt Priority bit 1 High priority 0 Low priority bit 1 TMR2IP TMR2 to PR2 Match Interrupt Priority bit 1 High priority 0 Low priority bit 0 TMR1IP TMR1 Overflow Interrupt Priority bit 1 High priority 0 Low priority Note 1 This bit is unimplemented on 28pin devices and will read as 0 2008 Microchip Technology Inc DS39631Epage 101 PIC18F2420252044204520 REGISTER 99 IPR2 PERIPHERAL INTERRUPT PRIORITY REGISTER 2 RW1 RW1 U0 RW1 RW1 RW1 RW1 RW1 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 OSCFIP Oscillator Fail Interrupt Priority bit 1 High priority 0 Low priority bit 6 CMIP Comparator Interrupt Priority bit 1 High priority 0 Low priority bit 5 Unimplemented Read as 0 bit 4 EEIP Data EEPROMFlash Write Operation Interrupt Priority bit 1 High priority 0 Low priority bit 3 BCLIP Bus Collision Interrupt Priority bit 1 High priority 0 Low priority bit 2 HLVDIP HighLowVoltage Detect Interrupt Priority bit 1 High priority 0 Low priority bit 1 TMR3IP TMR3 Overflow Interrupt Priority bit 1 High priority 0 Low priority bit 0 CCP2IP CCP2 Interrupt Priority bit 1 High priority 0 Low priority PIC18F2420252044204520 DS39631Epage 102 2008 Microchip Technology Inc 95 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wakeup from Idle or Sleep modes RCON also contains the IPEN bit which enables interrupt priorities The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 41 RCON Register REGISTER 910 RCON RESET CONTROL REGISTER RW0 RW11 U0 RW1 R1 R1 RW01 RW0 IPEN SBOREN RI TO PD POR BOR bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 IPEN Interrupt Priority Enable bit 1 Enable priority levels on interrupts 0 Disable priority levels on interrupts PIC16CXXX Compatibility mode bit 6 SBOREN Software BOR Enable bit1 For details of bit operation see Register 41 bit 5 Unimplemented Read as 0 bit 4 RI RESET Instruction Flag bit For details of bit operation see Register 41 bit 3 TO Watchdog Timer Timeout Flag bit For details of bit operation see Register 41 bit 2 PD PowerDown Detection Flag bit For details of bit operation see Register 41 bit 1 POR Poweron Reset Status bit1 For details of bit operation see Register 41 bit 0 BOR Brownout Reset Status bit For details of bit operation see Register 41 Note 1 Actual Reset values are determined by device configuration and the nature of the device Reset See Register 41 for additional information 2008 Microchip Technology Inc DS39631Epage 103 PIC18F2420252044204520 96 INTx Pin Interrupts External interrupts on the RB0INT0 RB1INT1 and RB2INT2 pins are edgetriggered If the corresponding INTEDGx bit in the INTCON2 register is set 1 the interrupt is triggered by a rising edge if the bit is clear the trigger is on the falling edge When a valid edge appears on the RBxINTx pin the corresponding flag bit INTxIF is set This interrupt can be disabled by clearing the corresponding enable bit INTxIE Flag bit INTxIF must be cleared in software in the Interrupt Service Routine before reenabling the interrupt All external interrupts INT0 INT1 and INT2 can wake up the processor from Idle or Sleep modes if bit INTxIE was set prior to going into those modes If the Global Interrupt Enable bit GIE is set the processor will branch to the interrupt vector following wakeup Interrupt priority for INT1 and INT2 is determined by the value contained in the Interrupt Priority bits INT1IP INTCON36 and INT2IP INTCON37 There is no priority bit associated with INT0 It is always a highpriority interrupt source 97 TMR0 Interrupt In 8bit mode which is the default an overflow in the TMR0 register FFh 00h will set flag bit TMR0IF In 16bit mode an overflow in the TMR0HTMR0L regis ter pair FFFFh 0000h will set TMR0IF The interrupt can be enableddisabled by settingclearing enable bit TMR0IE INTCON5 Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP INTCON22 See Section 110 Timer0 Module for further details on the Timer0 module 98 PORTB InterruptonChange An input change on PORTB74 sets flag bit RBIF INTCON0 The interrupt can be enableddisabled by settingclearing enable bit RBIE INTCON3 Interrupt priority for PORTB interruptonchange is determined by the value contained in the interrupt priority bit RBIP INTCON20 99 Context Saving During Interrupts During interrupts the return PC address is saved on the stack Additionally the WREG STATUS and BSR registers are saved on the Fast Return Stack If a fast return from interrupt is not used see Section 53 Data Memory Organization the user may need to save the WREG STATUS and BSR registers on entry to the Interrupt Service Routine Depending on the users application other registers may also need to be saved Example 91 saves and restores the WREG STATUS and BSR registers during an Interrupt Service Routine EXAMPLE 91 SAVING STATUS WREG AND BSR REGISTERS IN RAM MOVWF WTEMP WTEMP is in virtual bank MOVFF STATUS STATUSTEMP STATUSTEMP located anywhere MOVFF BSR BSRTEMP BSRTMEP located anywhere USER ISR CODE MOVFF BSRTEMP BSR Restore BSR MOVF WTEMP W Restore WREG MOVFF STATUSTEMP STATUS Restore STATUS PIC18F2420252044204520 DS39631Epage 104 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 105 PIC18F2420252044204520 100 IO PORTS Depending on the device selected and features enabled there are up to five ports available Some pins of the IO ports are multiplexed with an alternate function from the peripheral features on the device In general when a peripheral is enabled that pin may not be used as a general purpose IO pin Each port has three registers for its operation These registers are TRIS register Data Direction register PORT register reads the levels on the pins of the device LAT register Data Latch register The Data Latch LAT register is useful for readmodify write operations on the value that the IO pins are driving A simplified model of a generic IO port without the interfaces to other peripherals is shown in Figure 101 FIGURE 101 GENERIC IO PORT OPERATION 101 PORTA TRISA and LATA Registers PORTA is an 8bit wide bidirectional port The corre sponding Data Direction register is TRISA Setting a TRISA bit 1 will make the corresponding PORTA pin an input ie put the corresponding output driver in a highimpedance mode Clearing a TRISA bit 0 will make the corresponding PORTA pin an output ie put the contents of the output latch on the selected pin Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch The Data Latch LATA register is also memory mapped Readmodifywrite operations on the LATA register read and write the latched output value for PORTA The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RA4T0CKIC1OUT pin Pins RA6 and RA7 are multiplexed with the main oscillator pins they are enabled as oscillator or IO pins by the selection of the main oscillator in the Configuration register see Section 231 Configuration Bits for details When they are not used as port pins RA6 and RA7 and their associated TRIS and LAT bits are read as 0 The other PORTA pins are multiplexed with analog inputs the analog VREF and VREF inputs and the com parator voltage reference output The operation of pins RA30 and RA5 as AD Converter inputs is selected by clearing or setting the control bits in the ADCON1 register AD Control Register 1 Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register To use RA30 as digital inputs it is also necessary to turn off the comparators The RA4T0CKIC1OUT pin is a Schmitt Trigger input All other PORTA pins have TTL input levels and full CMOS output drivers The TRISA register controls the direction of the PORTA pins even when they are being used as analog inputs The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs EXAMPLE 101 INITIALIZING PORTA Data Bus WR LAT WR TRIS RD Port Data Latch TRIS Latch RD TRIS Input Buffer IO pin1 Q D CK Q D CK EN Q D EN RD LAT or Port Note 1 IO pins have diode protection to VDD and VSS Note On a Poweron Reset RA5 and RA30 are configured as analog inputs and read as 0 RA4 is configured as a digital input CLRF PORTA Initialize PORTA by clearing output data latches CLRF LATA Alternate method to clear output data latches MOVLW 07h Configure AD MOVWF ADCON1 for digital inputs MOVWF 07h Configure comparators MOVWF CMCON for digital input MOVLW 0CFh Value used to initialize data direction MOVWF TRISA Set RA30 as inputs RA54 as outputs PIC18F2420252044204520 DS39631Epage 106 2008 Microchip Technology Inc TABLE 101 PORTA IO SUMMARY Pin Function TRIS Setting IO IO Type Description RA0AN0 RA0 0 O DIG LATA0 data output not affected by analog input 1 I TTL PORTA0 data input disabled when analog input enabled AN0 1 I ANA AD input channel 0 and comparator C1 input Default input configuration on POR does not affect digital output RA1AN1 RA1 0 O DIG LATA1 data output not affected by analog input 1 I TTL PORTA1 data input disabled when analog input enabled AN1 1 I ANA AD input channel 1 and comparator C2 input Default input configuration on POR does not affect digital output RA2AN2 VREFCVREF RA2 0 O DIG LATA2 data output not affected by analog input Disabled when CVREF output enabled 1 I TTL PORTA2 data input Disabled when analog functions enabled disabled when CVREF output enabled AN2 1 I ANA AD input channel 2 and comparator C2 input Default input configuration on POR not affected by analog output VREF 1 I ANA AD and comparator voltage reference low input CVREF x O ANA Comparator voltage reference output Enabling this feature disables digital IO RA3AN3VREF RA3 0 O DIG LATA3 data output not affected by analog input 1 I TTL PORTA3 data input disabled when analog input enabled AN3 1 I ANA AD input channel 3 and comparator C1 input Default input configuration on POR VREF 1 I ANA AD and comparator voltage reference high input RA4T0CKIC1OUT RA4 0 O DIG LATA4 data output 1 I ST PORTA4 data input default configuration on POR T0CKI 1 I ST Timer0 clock input C1OUT 0 O DIG Comparator 1 output takes priority over port data RA5AN4SS HLVDINC2OUT RA5 0 O DIG LATA5 data output not affected by analog input 1 I TTL PORTA5 data input disabled when analog input enabled AN4 1 I ANA AD input channel 4 Default configuration on POR SS 1 I TTL Slave select input for MSSP module HLVDIN 1 I ANA HighLowVoltage Detect external trip point input C2OUT 0 O DIG Comparator 2 output takes priority over port data OSC2CLKORA6 RA6 0 O DIG LATA6 data output Enabled in RCIO INTIO2 and ECIO modes only 1 I TTL PORTA6 data input Enabled in RCIO INTIO2 and ECIO modes only OSC2 x O ANA Main oscillator feedback output connection XT HS and LP modes CLKO x O DIG System cycle clock output FOSC4 in RC INTIO1 and EC Oscillator modes OSC1CLKIRA7 RA7 0 O DIG LATA7 data output Disabled in external oscillator modes 1 I TTL PORTA7 data input Disabled in external oscillator modes OSC1 x I ANA Main oscillator input connection CLKI x I ANA Main clock input connection Legend DIG Digital level output TTL TTL input buffer ST Schmitt Trigger input buffer ANA Analog level inputoutput x Dont care TRIS bit does not affect port direction or is overridden for this option 2008 Microchip Technology Inc DS39631Epage 107 PIC18F2420252044204520 TABLE 102 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTA RA71 RA61 RA5 RA4 RA3 RA2 RA1 RA0 52 LATA LATA71 LATA61 PORTA Data Latch Register Read and Write to Data Latch 52 TRISA TRISA71 TRISA61 PORTA Data Direction Register 52 ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 Legend unimplemented read as 0 Shaded cells are not used by PORTA Note 1 RA76 and their associated latch and data direction bits are enabled as IO pins based on oscillator configuration otherwise they are read as 0 PIC18F2420252044204520 DS39631Epage 108 2008 Microchip Technology Inc 102 PORTB TRISB and LATB Registers PORTB is an 8bit wide bidirectional port The corre sponding Data Direction register is TRISB Setting a TRISB bit 1 will make the corresponding PORTB pin an input ie put the corresponding output driver in a highimpedance mode Clearing a TRISB bit 0 will make the corresponding PORTB pin an output ie put the contents of the output latch on the selected pin The Data Latch register LATB is also memory mapped Readmodifywrite operations on the LATB register read and write the latched output value for PORTB EXAMPLE 102 INITIALIZING PORTB Each of the PORTB pins has a weak internal pullup A single control bit can turn on all the pullups This is performed by clearing bit RBPU INTCON27 The weak pullup is automatically turned off when the port pin is configured as an output The pullups are disabled on a Poweron Reset Four of the PORTB pins RB74 have an interrupt onchange feature Only pins configured as inputs can cause this interrupt to occur ie any RB74 pin configured as an output is excluded from the interrupt onchange comparison The input pins of RB74 are compared with the old value latched on the last read of PORTB The mismatch outputs of RB74 are ORed together to generate the RB Port Change Interrupt with Flag bit RBIF INTCON0 This interrupt can wake the device from the Sleep mode or any of the Idle modes The user in the Interrupt Service Routine can clear the interrupt in the following manner a Any read or write of PORTB except with the MOVFF ANY PORTB instruction b Clear flag bit RBIF A mismatch condition will continue to set flag bit RBIF Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared The interruptonchange feature is recommended for wakeup on key depression operation and operations where PORTB is only used for the interruptonchange feature Polling of PORTB is not recommended while using the interruptonchange feature RB3 can be configured by the Configuration bit CCP2MX as the alternate peripheral pin for the CCP2 module CCP2MX 0 Note On a Poweron Reset RB40 are configured as analog inputs by default and read as 0 RB75 are configured as digital inputs By programming the Configuration bit PBADEN RB40 will alternatively be configured as digital inputs on POR CLRF PORTB Initialize PORTB by clearing output data latches CLRF LATB Alternate method to clear output data latches MOVLW 0Fh Set RB40 as MOVWF ADCON1 digital IO pins required if config bit PBADEN is set MOVLW 0CFh Value used to initialize data direction MOVWF TRISB Set RB30 as inputs RB54 as outputs RB76 as inputs 2008 Microchip Technology Inc DS39631Epage 109 PIC18F2420252044204520 TABLE 103 PORTB IO SUMMARY Pin Function TRIS Setting IO IO Type Description RB0INT0FLT0 AN12 RB0 0 O DIG LATB0 data output not affected by analog input 1 I TTL PORTB0 data input weak pullup when RBPU bit is cleared Disabled when analog input enabled1 INT0 1 I ST External interrupt 0 input FLT0 1 I ST Enhanced PWM Fault input ECCP1 module enabled in software AN12 1 I ANA AD input channel 121 RB1INT1AN10 RB1 0 O DIG LATB1 data output not affected by analog input 1 I TTL PORTB1 data input weak pullup when RBPU bit is cleared Disabled when analog input enabled1 INT1 1 I ST External Interrupt 1 input AN10 1 I ANA AD input channel 101 RB2INT2AN8 RB2 0 O DIG LATB2 data output not affected by analog input 1 I TTL PORTB2 data input weak pullup when RBPU bit is cleared Disabled when analog input enabled1 INT2 1 I ST External interrupt 2 input AN8 1 I ANA AD input channel 81 RB3AN9CCP2 RB3 0 O DIG LATB3 data output not affected by analog input 1 I TTL PORTB3 data input weak pullup when RBPU bit is cleared Disabled when analog input enabled1 AN9 1 I ANA AD input channel 91 CCP22 0 O DIG CCP2 compare and PWM output 1 I ST CCP2 capture input RB4KBI0AN11 RB4 0 O DIG LATB4 data output not affected by analog input 1 I TTL PORTB4 data input weak pullup when RBPU bit is cleared Disabled when analog input enabled1 KBI0 1 I TTL Interruptonpin change AN11 1 I ANA AD input channel 111 RB5KBI1PGM RB5 0 O DIG LATB5 data output 1 I TTL PORTB5 data input weak pullup when RBPU bit is cleared KBI1 1 I TTL Interruptonpin change PGM x I ST SingleSupply InCircuit Serial Programming mode entry ICSP Enabled by LVP Configuration bit all other pin functions disabled RB6KBI2PGC RB6 0 O DIG LATB6 data output 1 I TTL PORTB6 data input weak pullup when RBPU bit is cleared KBI2 1 I TTL Interruptonpin change PGC x I ST Serial execution ICSP clock input for ICSP and ICD operation3 RB7KBI3PGD RB7 0 O DIG LATB7 data output 1 I TTL PORTB7 data input weak pullup when RBPU bit is cleared KBI3 1 I TTL Interruptonpin change PGD x O DIG Serial execution data output for ICSP and ICD operation3 x I ST Serial execution data input for ICSP and ICD operation3 Legend DIG Digital level output TTL TTL input buffer ST Schmitt Trigger input buffer ANA Analog level inputoutput x Dont care TRIS bit does not affect port direction or is overridden for this option Note 1 Configuration on POR is determined by the PBADEN Configuration bit Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared 2 Alternate assignment for CCP2 when the CCP2MX Configuration bit is 0 Default assignment is RC1 3 All other pin functions are disabled when ICSP or ICD are enabled PIC18F2420252044204520 DS39631Epage 110 2008 Microchip Technology Inc TABLE 104 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 LATB PORTB Data Latch Register Read and Write to Data Latch 52 TRISB PORTB Data Direction Register 52 INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP RBIP 49 INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 49 ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 Legend unimplemented read as 0 Shaded cells are not used by PORTB 2008 Microchip Technology Inc DS39631Epage 111 PIC18F2420252044204520 103 PORTC TRISC and LATC Registers PORTC is an 8bit wide bidirectional port The corre sponding Data Direction register is TRISC Setting a TRISC bit 1 will make the corresponding PORTC pin an input ie put the corresponding output driver in a highimpedance mode Clearing a TRISC bit 0 will make the corresponding PORTC pin an output ie put the contents of the output latch on the selected pin The Data Latch register LATC is also memory mapped Readmodifywrite operations on the LATC register read and write the latched output value for PORTC PORTC is multiplexed with several peripheral functions Table 105 The pins have Schmitt Trigger input buf fers RC1 is normally configured by Configuration bit CCP2MX as the default peripheral pin of the CCP2 module defaulterased state CCP2MX 1 When enabling peripheral functions care should be taken in defining TRIS bits for each PORTC pin Some peripherals override the TRIS bit to make a pin an output while other peripherals override the TRIS bit to make a pin an input The user should refer to the corresponding peripheral section for additional information The contents of the TRISC register are affected by peripheral overrides Reading TRISC always returns the current contents even though a peripheral device may be overriding one or more of the pins EXAMPLE 103 INITIALIZING PORTC Note On a Poweron Reset these pins are configured as digital inputs CLRF PORTC Initialize PORTC by clearing output data latches CLRF LATC Alternate method to clear output data latches MOVLW 0CFh Value used to initialize data direction MOVWF TRISC Set RC30 as inputs RC54 as outputs RC76 as inputs PIC18F2420252044204520 DS39631Epage 112 2008 Microchip Technology Inc TABLE 105 PORTC IO SUMMARY Pin Function TRIS Setting IO IO Type Description RC0T1OSO T13CKI RC0 0 O DIG LATC0 data output 1 I ST PORTC0 data input T1OSO x O ANA Timer1 oscillator output enabled when Timer1 oscillator enabled Disables digital IO T13CKI 1 I ST Timer1Timer3 counter input RC1T1OSICCP2 RC1 0 O DIG LATC1 data output 1 I ST PORTC1 data input T1OSI x I ANA Timer1 oscillator input enabled when Timer1 oscillator enabled Disables digital IO CCP21 0 O DIG CCP2 compare and PWM output takes priority over port data 1 I ST CCP2 capture input RC2CCP1P1A RC2 0 O DIG LATC2 data output 1 I ST PORTC2 data input CCP1 0 O DIG ECCP1 compare or PWM output takes priority over port data 1 I ST ECCP1 capture input P1A2 0 O DIG ECCP1 Enhanced PWM output channel A May be configured for tristate during Enhanced PWM shutdown events Takes priority over port data RC3SCKSCL RC3 0 O DIG LATC3 data output 1 I ST PORTC3 data input SCK 0 O DIG SPI clock output MSSP module takes priority over port data 1 I ST SPI clock input MSSP module SCL 0 O DIG I2C clock output MSSP module takes priority over port data 1 I I2CSMB I2C clock input MSSP module input type depends on module setting RC4SDISDA RC4 0 O DIG LATC4 data output 1 I ST PORTC4 data input SDI 1 I ST SPI data input MSSP module SDA 1 O DIG I2C data output MSSP module takes priority over port data 1 I I2CSMB I2C data input MSSP module input type depends on module setting RC5SDO RC5 0 O DIG LATC5 data output 1 I ST PORTC5 data input SDO 0 O DIG SPI data output MSSP module takes priority over port data RC6TXCK RC6 0 O DIG LATC6 data output 1 I ST PORTC6 data input TX 1 O DIG Asynchronous serial transmit data output EUSART module takes priority over port data User must configure as output CK 1 O DIG Synchronous serial clock output EUSART module takes priority over port data 1 I ST Synchronous serial clock input EUSART module RC7RXDT RC7 0 O DIG LATC7 data output 1 I ST PORTC7 data input RX 1 I ST Asynchronous serial receive data input EUSART module DT 1 O DIG Synchronous serial data output EUSART module takes priority over port data 1 I ST Synchronous serial data input EUSART module User must configure as an input Legend DIG Digital level output TTL TTL input buffer ST Schmitt Trigger input buffer ANA Analog level inputoutput I2CSMB I2CSMBus input buffer x Dont care TRIS bit does not affect port direction or is overridden for this option Note 1 Default assignment for CCP2 when the CCP2MX Configuration bit is set Alternate assignment is RB3 2 Enhanced PWM output is available only on PIC18F4520 devices 2008 Microchip Technology Inc DS39631Epage 113 PIC18F2420252044204520 TABLE 106 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 52 LATC PORTC Data Latch Register Read and Write to Data Latch 52 TRISC PORTC Data Direction Register 52 PIC18F2420252044204520 DS39631Epage 114 2008 Microchip Technology Inc 104 PORTD TRISD and LATD Registers PORTD is an 8bit wide bidirectional port The corre sponding Data Direction register is TRISD Setting a TRISD bit 1 will make the corresponding PORTD pin an input ie put the corresponding output driver in a highimpedance mode Clearing a TRISD bit 0 will make the corresponding PORTD pin an output ie put the contents of the output latch on the selected pin The Data Latch register LATD is also memory mapped Readmodifywrite operations on the LATD register read and write the latched output value for PORTD All pins on PORTD are implemented with Schmitt Trig ger input buffers Each pin is individually configurable as an input or output Three of the PORTD pins are multiplexed with outputs P1B P1C and P1D of the Enhanced CCP module The operation of these additional PWM output pins is covered in greater detail in Section 160 Enhanced CaptureComparePWM ECCP Module PORTD can also be configured as an 8bit wide micro processor port Parallel Slave Port by setting control bit PSPMODE TRISE4 In this mode the input buffers are TTL See Section 106 Parallel Slave Port for additional information on the Parallel Slave Port PSP EXAMPLE 104 INITIALIZING PORTD Note PORTD is only available on 4044pin devices Note On a Poweron Reset these pins are configured as digital inputs Note When the enhanced PWM mode is used with either dual or quad outputs the PSP functions of PORTD are automatically disabled CLRF PORTD Initialize PORTD by clearing output data latches CLRF LATD Alternate method to clear output data latches MOVLW 0CFh Value used to initialize data direction MOVWF TRISD Set RD30 as inputs RD54 as outputs RD76 as inputs 2008 Microchip Technology Inc DS39631Epage 115 PIC18F2420252044204520 TABLE 107 PORTD IO SUMMARY Pin Function TRIS Setting IO IO Type Description RD0PSP0 RD0 0 O DIG LATD0 data output 1 I ST PORTD0 data input PSP0 x O DIG PSP read data output LATD0 takes priority over port data x I TTL PSP write data input RD1PSP1 RD1 0 O DIG LATD1 data output 1 I ST PORTD1 data input PSP1 x O DIG PSP read data output LATD1 takes priority over port data x I TTL PSP write data input RD2PSP2 RD2 0 O DIG LATD2 data output 1 I ST PORTD2 data input PSP2 x O DIG PSP read data output LATD2 takes priority over port data x I TTL PSP write data input RD3PSP3 RD3 0 O DIG LATD3 data output 1 I ST PORTD3 data input PSP3 x O DIG PSP read data output LATD3 takes priority over port data x I TTL PSP write data input RD4PSP4 RD4 0 O DIG LATD4 data output 1 I ST PORTD4 data input PSP4 x O DIG PSP read data output LATD4 takes priority over port data x I TTL PSP write data input RD5PSP5P1B RD5 0 O DIG LATD5 data output 1 I ST PORTD5 data input PSP5 x O DIG PSP read data output LATD5 takes priority over port data x I TTL PSP write data input P1B 0 O DIG ECCP1 Enhanced PWM output channel B takes priority over port and PSP data May be configured for tristate during Enhanced PWM shutdown events RD6PSP6P1C RD6 0 O DIG LATD6 data output 1 I ST PORTD6 data input PSP6 x O DIG PSP read data output LATD6 takes priority over port data x I TTL PSP write data input P1C 0 O DIG ECCP1 Enhanced PWM output channel C takes priority over port and PSP data May be configured for tristate during Enhanced PWM shutdown events RD7PSP7P1D RD7 0 O DIG LATD7 data output 1 I ST PORTD7 data input PSP7 x O DIG PSP read data output LATD7 takes priority over port data x I TTL PSP write data input P1D 0 O DIG ECCP1 Enhanced PWM output channel D takes priority over port and PSP data May be configured for tristate during Enhanced PWM shutdown events Legend DIG Digital level output TTL TTL input buffer ST Schmitt Trigger input buffer x Dont care TRIS bit does not affect port direction or is overridden for this option PIC18F2420252044204520 DS39631Epage 116 2008 Microchip Technology Inc TABLE 108 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52 LATD PORTD Data Latch Register Read and Write to Data Latch 52 TRISD PORTD Data Direction Register 52 TRISE1 IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 52 CCP1CON P1M11 P1M01 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 Legend unimplemented read as 0 Shaded cells are not used by PORTD Note 1 These registers andor bits are unimplemented on 28oin devices 2008 Microchip Technology Inc DS39631Epage 117 PIC18F2420252044204520 105 PORTE TRISE and LATE Registers Depending on the particular PIC18F242025204420 4520 device selected PORTE is implemented in two different ways For 4044pin devices PORTE is a 4bit wide port Three pins RE0RDAN5 RE1WRAN6 and RE2CS AN7 are individually configurable as inputs or outputs These pins have Schmitt Trigger input buffers When selected as an analog input these pins will read as 0s The corresponding Data Direction register is TRISE Setting a TRISE bit 1 will make the corresponding PORTE pin an input ie put the corresponding output driver in a highimpedance mode Clearing a TRISE bit 0 will make the corresponding PORTE pin an output ie put the contents of the output latch on the selected pin TRISE controls the direction of the RE pins even when they are being used as analog inputs The user must make sure to keep the pins configured as inputs when using them as analog inputs The upper four bits of the TRISE register also control the operation of the Parallel Slave Port Their operation is explained in Register 101 The Data Latch register LATE is also memory mapped Readmodifywrite operations on the LATE register read and write the latched output value for PORTE The fourth pin of PORTE MCLRVPPRE3 is an input only pin Its operation is controlled by the MCLRE Con figuration bit When selected as a port pin MCLRE 0 it functions as a digital input only pin as such it does not have TRIS or LAT bits associated with its operation Otherwise it functions as the devices Master Clear input In either configuration RE3 also functions as the programming voltage input during programming EXAMPLE 105 INITIALIZING PORTE 1051 PORTE IN 28PIN DEVICES For 28pin devices PORTE is only available when Master Clear functionality is disabled MCLRE 0 In these cases PORTE is a single bit input only port com prised of RE3 only The pin operates as previously described Note On a Poweron Reset RE20 are configured as analog inputs Note On a Poweron Reset RE3 is enabled as a digital input only if Master Clear functionality is disabled CLRF PORTE Initialize PORTE by clearing output data latches CLRF LATE Alternate method to clear output data latches MOVLW 0Ah Configure AD MOVWF ADCON1 for digital inputs MOVLW 03h Value used to initialize data direction MOVWF TRISE Set RE0 as inputs RE1 as outputs RE2 as inputs PIC18F2420252044204520 DS39631Epage 118 2008 Microchip Technology Inc REGISTER 101 TRISE REGISTER 4044PIN DEVICES ONLY R0 R0 RW0 RW0 U0 RW1 RW1 RW1 IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 IBF Input Buffer Full Status bit 1 A word has been received and waiting to be read by the CPU 0 No word has been received bit 6 OBF Output Buffer Full Status bit 1 The output buffer still holds a previously written word 0 The output buffer has been read bit 5 IBOV Input Buffer Overflow Detect bit in Microprocessor mode 1 A write occurred when a previously input word has not been read must be cleared in software 0 No overflow occurred bit 4 PSPMODE Parallel Slave Port Mode Select bit 1 Parallel Slave Port mode 0 General purpose IO mode bit 3 Unimplemented Read as 0 bit 2 TRISE2 RE2 Direction Control bit 1 Input 0 Output bit 1 TRISE1 RE1 Direction Control bit 1 Input 0 Output bit 0 TRISE0 RE0 Direction Control bit 1 Input 0 Output 2008 Microchip Technology Inc DS39631Epage 119 PIC18F2420252044204520 TABLE 109 PORTE IO SUMMARY TABLE 1010 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Pin Function TRIS Setting IO IO Type Description RE0RDAN5 RE0 0 O DIG LATE0 data output not affected by analog input 1 I ST PORTE0 data input disabled when analog input enabled RD 1 I TTL PSP read enable input PSP enabled AN5 1 I ANA AD input channel 5 default input configuration on POR RE1WRAN6 RE1 0 O DIG LATE1 data output not affected by analog input 1 I ST PORTE1 data input disabled when analog input enabled WR 1 I TTL PSP write enable input PSP enabled AN6 1 I ANA AD input channel 6 default input configuration on POR RE2CSAN7 RE2 0 O DIG LATE2 data output not affected by analog input 1 I ST PORTE2 data input disabled when analog input enabled CS 1 I TTL PSP write enable input PSP enabled AN7 1 I ANA AD input channel 7 default input configuration on POR MCLRVPPRE31 MCLR I ST External Master Clear input enabled when MCLRE Configuration bit is set VPP I ANA Highvoltage detection used for ICSP mode entry detection Always available regardless of pin mode RE3 2 I ST PORTE3 data input enabled when MCLRE Configuration bit is clear Legend DIG Digital level output TTL TTL input buffer ST Schmitt Trigger input buffer ANA Analog level inputoutput x Dont care TRIS bit does not affect port direction or is overridden for this option Note 1 RE3 is available on both 28pin and 4044pin devices All other PORTE pins are only implemented on 4044pin devices 2 RE3 does not have a corresponding TRIS bit to control data direction Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTE RE312 RE2 RE1 RE0 52 LATE2 LATE Data Latch Register 52 TRISE IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 52 ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 Legend unimplemented read as 0 Shaded cells are not used by PORTE Note 1 Implemented only when Master Clear functionality is disabled MCLRE Configuration bit 0 2 RE3 is the only PORTE bit implemented on both 28pin and 4044pin devices All other bits are implemented only when PORTE is implemented ie 4044pin devices PIC18F2420252044204520 DS39631Epage 120 2008 Microchip Technology Inc 106 Parallel Slave Port In addition to its function as a general IO port PORTD can also operate as an 8bit wide Parallel Slave Port PSP or microprocessor port PSP operation is con trolled by the 4 upper bits of the TRISE register Register 101 Setting control bit PSPMODE TRISE4 enables PSP operation as long as the Enhanced CCP module is not operating in dual output or quad output PWM mode In Slave mode the port is asynchronously readable and writable by the external world The PSP can directly interface to an 8bit micro processor data bus The external microprocessor can read or write the PORTD latch as an 8bit latch Setting the control bit PSPMODE enables the PORTE IO pins to become control inputs for the microprocessor port When set port pin RE0 is the RD input RE1 is the WR input and RE2 is the CS Chip Select input For this functionality the corresponding data direction bits of the TRISE register TRISE20 must be config ured as inputs set The AD port configuration bits PFCG30 ADCON130 must also be set to a value in the range of 1010 through 1111 A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high The PSPIF and IBF flag bits are both set when the write ends A read from the PSP occurs when both the CS and RD lines are first detected low The data in PORTD is read out and the OBF bit is clear If the user writes new data to PORTD to set OBF the data is immediately read out however the OBF bit is not set When either the CS or RD lines are detected high the PORTD pins return to the input state and the PSPIF bit is set User applications should wait for PSPIF to be set before servicing the PSP when this happens the IBF and OBF bits can be polled and the appropriate action taken The timing for the control signals in Write and Read modes is shown in Figure 103 and Figure 104 respectively FIGURE 102 PORTD AND PORTE BLOCK DIAGRAM PARALLEL SLAVE PORT Note The Parallel Slave Port is only available on 4044pin devices Data Bus WR LATD RDx pin Q D CK EN Q D EN RD PORTD One bit of PORTD Set Interrupt Flag PSPIF PIR17 Read Chip Select Write RD CS WR TTL TTL TTL TTL or WR PORTD RD LATD Data Latch Note IO pins have diode protection to VDD and VSS PORTE Pins 2008 Microchip Technology Inc DS39631Epage 121 PIC18F2420252044204520 FIGURE 103 PARALLEL SLAVE PORT WRITE WAVEFORMS FIGURE 104 PARALLEL SLAVE PORT READ WAVEFORMS TABLE 1011 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52 LATD PORTD Data Latch Register Read and Write to Data Latch 52 TRISD PORTD Data Direction Register 52 PORTE RE3 RE2 RE1 RE0 52 LATE LATE Data Latch Register 52 TRISE IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 52 INTCON GIEGIEH PEIEGIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 Legend unimplemented read as 0 Shaded cells are not used by the Parallel Slave Port Q1 Q2 Q3 Q4 CS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 WR RD IBF OBF PSPIF PORTD70 Q1 Q2 Q3 Q4 CS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 WR IBF PSPIF RD OBF PORTD70 PIC18F2420252044204520 DS39631Epage 122 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 123 PIC18F2420252044204520 110 TIMER0 MODULE The Timer0 module incorporates the following features Software selectable operation as a timer or counter in both 8bit or 16bit modes Readable and writable registers Dedicated 8bit software programmable prescaler Selectable clock source internal or external Edge select for external clock Interruptonoverflow The T0CON register Register 111 controls all aspects of the modules operation including the prescale selection It is both readable and writable A simplified block diagram of the Timer0 module in 8bit mode is shown in Figure 111 Figure 112 shows a simplified block diagram of the Timer0 module in 16bit mode REGISTER 111 T0CON TIMER0 CONTROL REGISTER RW1 RW1 RW1 RW1 RW1 RW1 RW1 RW1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 TMR0ON Timer0 OnOff Control bit 1 Enables Timer0 0 Stops Timer0 bit 6 T08BIT Timer0 8Bit16Bit Control bit 1 Timer0 is configured as an 8bit timercounter 0 Timer0 is configured as a 16bit timercounter bit 5 T0CS Timer0 Clock Source Select bit 1 Transition on T0CKI pin 0 Internal instruction cycle clock CLKO bit 4 T0SE Timer0 Source Edge Select bit 1 Increment on hightolow transition on T0CKI pin 0 Increment on lowtohigh transition on T0CKI pin bit 3 PSA Timer0 Prescaler Assignment bit 1 TImer0 prescaler is not assigned Timer0 clock input bypasses prescaler 0 Timer0 prescaler is assigned Timer0 clock input comes from prescaler output bit 20 T0PS20 Timer0 Prescaler Select bits 111 1256 Prescale value 110 1128 Prescale value 101 164 Prescale value 100 132 Prescale value 011 116 Prescale value 010 18 Prescale value 001 14 Prescale value 000 12 Prescale value PIC18F2420252044204520 DS39631Epage 124 2008 Microchip Technology Inc 111 Timer0 Operation Timer0 can operate as either a timer or a counter the mode is selected with the T0CS bit T0CON5 In Timer mode T0CS 0 the module increments on every clock by default unless a different prescaler value is selected see Section 113 Prescaler If the TMR0 register is written to the increment is inhibited for the following two instruction cycles The user can work around this by writing an adjusted value to the TMR0 register The Counter mode is selected by setting the T0CS bit 1 In this mode Timer0 increments either on every rising or falling edge of pin RA4T0CKI The increment ing edge is determined by the Timer0 Source Edge Select bit T0SE T0CON4 clearing this bit selects the rising edge Restrictions on the external clock input are discussed below An external clock source can be used to drive Timer0 however it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock TOSC There is a delay between synchronization and the onset of incrementing the timercounter 112 Timer0 Reads and Writes in 16Bit Mode TMR0H is not the actual high byte of Timer0 in 16bit mode it is actually a buffered version of the real high byte of Timer0 which is not directly readable nor writ able refer to Figure 112 TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte Similarly a write to the high byte of Timer0 must also take place through the TMR0H Buffer register The high byte is updated with the contents of TMR0H when a write occurs to TMR0L This allows all 16 bits of Timer0 to be updated at once FIGURE 111 TIMER0 BLOCK DIAGRAM 8BIT MODE FIGURE 112 TIMER0 BLOCK DIAGRAM 16BIT MODE Note Upon Reset Timer0 is enabled in 8bit mode with clock input from T0CKI max prescale T0CKI pin T0SE 0 1 0 1 T0CS FOSC4 Programmable Prescaler Sync with Internal Clocks TMR0L 2 TCY Delay Internal Data Bus PSA T0PS20 Set TMR0IF on Overflow 3 8 8 Note Upon Reset Timer0 is enabled in 8bit mode with clock input from T0CKI max prescale T0CKI pin T0SE 0 1 0 1 T0CS FOSC4 Programmable Prescaler Sync with Internal Clocks TMR0L 2 TCY Delay Internal Data Bus 8 PSA T0PS20 Set TMR0IF on Overflow 3 TMR0 TMR0H High Byte 8 8 8 Read TMR0L Write TMR0L 8 2008 Microchip Technology Inc DS39631Epage 125 PIC18F2420252044204520 113 Prescaler An 8bit counter is available as a prescaler for the Timer0 module The prescaler is not directly readable or writable its value is set by the PSA and T0PS20 bits T0CON30 which determine the prescaler assignment and prescale ratio Clearing the PSA bit assigns the prescaler to the Timer0 module When it is assigned prescale values from 12 through 1256 in powerof2 increments are selectable When assigned to the Timer0 module all instructions writing to the TMR0 register eg CLRF TMR0 MOVWF TMR0 BSF TMR0 etc clear the prescaler count 1131 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed onthefly during program execution 114 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8bit mode or from FFFFh to 0000h in 16bit mode This overflow sets the TMR0IF flag bit The interrupt can be masked by clearing the TMR0IE bit INTCON5 Before re enabling the interrupt the TMR0IF bit must be cleared in software by the Interrupt Service Routine Since Timer0 is shut down in Sleep mode the TMR0 interrupt cannot awaken the processor from Sleep TABLE 111 REGISTERS ASSOCIATED WITH TIMER0 Note Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0L Timer0 Register Low Byte 50 TMR0H Timer0 Register High Byte 50 INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 50 TRISA RA71 RA61 RA5 RA4 RA3 RA2 RA1 RA0 52 Legend Shaded cells are not used by Timer0 Note 1 PORTA76 and their direction bits are individually configured as port pins based on various primary oscillator modes When disabled these bits read as 0 PIC18F2420252044204520 DS39631Epage 126 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 127 PIC18F2420252044204520 120 TIMER1 MODULE The Timer1 timercounter module incorporates these features Software selectable operation as a 16bit timer or counter Readable and writable 8bit registers TMR1H and TMR1L Selectable clock source internal or external with device clock or Timer1 oscillator internal options Interruptonoverflow Reset on CCP Special Event Trigger Device clock status flag T1RUN A simplified block diagram of the Timer1 module is shown in Figure 121 A block diagram of the modules operation in ReadWrite mode is shown in Figure 122 The module incorporates its own lowpower oscillator to provide an additional clocking option The Timer1 oscillator can also be used as a lowpower clock source for the microcontroller in powermanaged operation Timer1 can also be used to provide RealTime Clock RTC functionality to applications with only a minimal addition of external components and code overhead Timer1 is controlled through the T1CON Control register Register 121 It also contains the Timer1 Oscillator Enable bit T1OSCEN Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON T1CON0 REGISTER 121 T1CON TIMER1 CONTROL REGISTER RW0 R0 RW0 RW0 RW0 RW0 RW0 RW0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 RD16 16Bit ReadWrite Mode Enable bit 1 Enables register readwrite of TImer1 in one 16bit operation 0 Enables register readwrite of Timer1 in two 8bit operations bit 6 T1RUN Timer1 System Clock Status bit 1 Device clock is derived from Timer1 oscillator 0 Device clock is derived from another source bit 54 T1CKPS10 Timer1 Input Clock Prescale Select bits 11 18 Prescale value 10 14 Prescale value 01 12 Prescale value 00 11 Prescale value bit 3 T1OSCEN Timer1 Oscillator Enable bit 1 Timer1 oscillator is enabled 0 Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2 T1SYNC Timer1 External Clock Input Synchronization Select bit When TMR1CS 1 1 Do not synchronize external clock input 0 Synchronize external clock input When TMR1CS 0 This bit is ignored Timer1 uses the internal clock when TMR1CS 0 bit 1 TMR1CS Timer1 Clock Source Select bit 1 External clock from pin RC0T1OSOT13CKI on the rising edge 0 Internal clock FOSC4 bit 0 TMR1ON Timer1 On bit 1 Enables Timer1 0 Stops Timer1 PIC18F2420252044204520 DS39631Epage 128 2008 Microchip Technology Inc 121 Timer1 Operation Timer1 can operate in one of these modes Timer Synchronous Counter Asynchronous Counter The operating mode is determined by the clock select bit TMR1CS T1CON1 When TMR1CS is cleared 0 Timer1 increments on every internal instruction cycle FOSC4 When the bit is set Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled When Timer1 is enabled the RC1T1OSI and RC0 T1OSOT13CKI pins become inputs This means the values of TRISC10 are ignored and the pins are read as 0 FIGURE 121 TIMER1 BLOCK DIAGRAM FIGURE 122 TIMER1 BLOCK DIAGRAM 16BIT READWRITE MODE T1SYNC TMR1CS T1CKPS10 Sleep Input T1OSCEN1 FOSC4 Internal Clock OnOff Prescaler 1 2 4 8 Synchronize Detect 1 0 2 T1OSOT13CKI T1OSI 1 0 TMR1ON TMR1L Set TMR1IF on Overflow TMR1 High Byte Clear TMR1 CCP Special Event Trigger Timer1 Oscillator Note 1 When enable bit T1OSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain OnOff Timer1 Timer1 Clock Input T1SYNC TMR1CS T1CKPS10 Sleep Input T1OSCEN1 FOSC4 Internal Clock Prescaler 1 2 4 8 Synchronize Detect 1 0 2 T1OSOT13CKI T1OSI Note 1 When enable bit T1OSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain 1 0 TMR1L Internal Data Bus 8 Set TMR1IF on Overflow TMR1 TMR1H High Byte 8 8 8 Read TMR1L Write TMR1L 8 TMR1ON Clear TMR1 CCP Special Event Trigger Timer1 Oscillator OnOff Timer1 Timer1 Clock Input 2008 Microchip Technology Inc DS39631Epage 129 PIC18F2420252044204520 122 Timer1 16Bit ReadWrite Mode Timer1 can be configured for 16bit reads and writes see Figure 122 When the RD16 control bit T1CON7 is set the address for TMR1H is mapped to a buffer register for the high byte of Timer1 A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte followed by a read of the low byte has become invalid due to a rollover between reads A write to the high byte of Timer1 must also take place through the TMR1H Buffer register The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once The high byte of Timer1 is not directly readable or writable in this mode All reads and writes must take place through the Timer1 High Byte Buffer register Writes to TMR1H do not clear the Timer1 prescaler The prescaler is only cleared on writes to TMR1L 123 Timer1 Oscillator An onchip crystal oscillator circuit is incorporated between pins T1OSI input and T1OSO amplifier out put It is enabled by setting the Timer1 Oscillator Enable bit T1OSCEN T1CON3 The oscillator is a low power circuit rated for 32 kHz crystals It will continue to run during all powermanaged modes The circuit for a typical LP oscillator is shown in Figure 123 Table 121 shows the capacitor selection for the Timer1 oscillator The user must provide a software time delay to ensure proper startup of the Timer1 oscillator FIGURE 123 EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR TABLE 121 CAPACITOR SELECTION FOR THE TIMER OSCILLATOR 1231 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in powermanaged modes By setting the clock select bits SCS10 OSCCON10 to 01 the device switches to SECRUN mode both the CPU and peripherals are clocked from the Timer1 oscillator If the IDLEN bit OSCCON7 is cleared and a SLEEP instruction is executed the device enters SECIDLE mode Additional details are available in Section 30 PowerManaged Modes Whenever the Timer1 oscillator is providing the clock source the Timer1 system clock status flag T1RUN T1CON6 is set This can be used to determine the controllers current clocking mode It can also indicate the clock source being currently used by the FailSafe Clock Monitor If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source 1232 LOWPOWER TIMER1 OPTION The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration When the LPT1OSC Configuration bit is set the Timer1 oscillator operates in a lowpower mode When LPT1OSC is not set Timer1 operates at a higher power level Power consumption for a particular mode is relatively constant regardless of the devices operating mode The default Timer1 configuration is the higher power mode As the lowpower Timer1 mode tends to be more sensitive to interference high noise environments may cause some oscillator instability The lowpower option is therefore best suited for low noise applications where power conservation is an important design consideration Note See the Notes with Table 121 for additional information about capacitor selection C1 C2 XTAL PIC18FXXXX T1OSI T1OSO 32768 kHz 27 pF 27 pF Osc Type Freq C1 C2 LP 32 kHz 27 pF1 27 pF1 Note 1 Microchip suggests these values as a starting point in validating the oscillator circuit 2 Higher capacitance increases the stability of the oscillator but also increases the startup time 3 Since each resonatorcrystal has its own characteristics the user should consult the resonatorcrystal manufacturer for appropriate values of external components 4 Capacitor values are for design guidance only PIC18F2420252044204520 DS39631Epage 130 2008 Microchip Technology Inc 1233 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation Due to the lowpower nature of the oscillator it may also be sensitive to rapidly changing signals in close proximity The oscillator circuit shown in Figure 123 should be located as close as possible to the microcontroller There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD If a highspeed circuit must be located near the oscilla tor such as the CCP1 pin in Output Compare or PWM mode or the primary oscillator using the OSC2 pin a grounded guard ring around the oscillator circuit as shown in Figure 124 may be helpful when used on a singlesided PCB or in addition to a ground plane FIGURE 124 OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING 124 Timer1 Interrupt The TMR1 register pair TMR1HTMR1L increments from 0000h to FFFFh and rolls over to 0000h The Timer1 interrupt if enabled is generated on overflow which is latched in interrupt flag bit TMR1IF PIR10 This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit TMR1IE PIE10 125 Resetting Timer1 Using the CCP Special Event Trigger If either of the CCP modules is configured to use Timer1 and generate a Special Event Trigger in Com pare mode CCP1M30 or CCP2M30 1011 this signal will reset Timer1 The trigger from CCP2 will also start an AD conversion if the AD module is enabled see Section 1534 Special Event Trigger for more information The module must be configured as either a timer or a synchronous counter to take advantage of this feature When used this way the CCPRxHCCPRxL register pair effectively becomes a Period register for Timer1 If Timer1 is running in Asynchronous Counter mode this Reset operation may not work In the event that a write to Timer1 coincides with a Special Event Trigger the write operation will take precedence 126 Using Timer1 as a RealTime Clock Adding an external LP oscillator to Timer1 such as the one described in Section 123 Timer1 Oscillator gives users the option to include RTC functionality to their applications This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time When operating in Sleep mode and using a battery or supercapacitor as a power source it can completely eliminate the need for a separate RTC device and battery backup The application code routine RTCisr shown in Example 121 demonstrates a simple method to increment a counter at onesecond intervals using an Interrupt Service Routine Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one additional counters for minutes and hours are incremented as the previous counter overflow Since the register pair is 16 bits wide counting up to overflow the register directly from a 32768 kHz clock would take 2 seconds To force the overflow at the required onesecond intervals it is necessary to pre load it The simplest method is to set the MSb of TMR1H with a BSF instruction Note that the TMR1L register is never preloaded or altered doing so may introduce cumulative error over many cycles For this method to be accurate Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled PIE10 1 as shown in the routine RTCinit The Timer1 oscillator must also be enabled and running at all times VDD OSC1 VSS OSC2 RC0 RC1 RC2 Note Not drawn to scale Note The Special Event Triggers from the CCP2 module will not set the TMR1IF interrupt flag bit PIR10 2008 Microchip Technology Inc DS39631Epage 131 PIC18F2420252044204520 127 Considerations in Asynchronous Counter Mode Following a Timer1 interrupt and an update to the TMR1 registers the Timer1 module uses a falling edge on its clock source to trigger the next register update on the rising edge If the update is completed after the clock input has fallen the next rising edge will not be counted If the application can reliably update TMR1 before the timer input goes low no additional action is needed Otherwise an adjusted update can be performed following a later Timer1 increment This can be done by monitoring TMR1L within the interrupt routine until it increments and then updating the TMR1HTMR1L register pair while the clock is low or onehalf of the period of the clock source Assuming that Timer1 is being used as a RealTime Clock the clock source is a 32768 kHz crystal oscillator in this case one half period of the clock is 1525 μs The RealTime Clock application code in Example 121 shows a typical ISR for Timer1 as well as the optional code required if the update cannot be done reliably within the required interval EXAMPLE 121 IMPLEMENTING A REALTIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h Preload TMR1 register pair MOVWF TMR1H for 1 second overflow CLRF TMR1L MOVLW b00001111 Configure for external clock MOVWF T1CON Asynchronous operation external oscillator CLRF secs Initialize timekeeping registers CLRF mins MOVLW 12 MOVWF hours BSF PIE1 TMR1IE Enable Timer1 interrupt RETURN RTCisr Start ISR here Insert the next 4 lines of code when TMR1 can not be reliably updated before clock pulse goes low BTFSC TMR1L0 wait for TMR1L0 to become clear BRA 2 may already be clear BTFSS TMR1L0 wait for TMR1L0 to become set BRA 2 TMR1 has just incremented If TMR1 update can be completed before clock pulse goes low BSF TMR1H 7 Preload for 1 sec overflow BCF PIR1 TMR1IF Clear interrupt flag INCF secs F Increment seconds MOVLW 59 60 seconds elapsed CPFSGT secs RETURN No done CLRF secs Clear seconds INCF mins F Increment minutes MOVLW 59 60 minutes elapsed CPFSGT mins RETURN No done CLRF mins clear minutes INCF hours F Increment hours MOVLW 23 24 hours elapsed CPFSGT hours RETURN No done CLRF hours Reset hours RETURN Done PIC18F2420252044204520 DS39631Epage 132 2008 Microchip Technology Inc TABLE 122 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMERCOUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TMR1L Timer1 Register Low Byte 50 TMR1H Timer1 Register High Byte 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 Legend Shaded cells are not used by the Timer1 module Note 1 These bits are unimplemented on 28pin devices always maintain these bits clear 2008 Microchip Technology Inc DS39631Epage 133 PIC18F2420252044204520 130 TIMER2 MODULE The Timer2 module timer incorporates the following features 8Bit Timer and Period registers TMR2 and PR2 respectively Readable and writable both registers Software programmable prescaler 11 14 and 116 Software programmable postscaler 11 through 116 Interrupt on TMR2 to PR2 match Optional use as the shift clock for the MSSP module The module is controlled through the T2CON register Register 131 which enables or disables the timer and configures the prescaler and postscaler Timer2 can be shut off by clearing control bit TMR2ON T2CON2 to minimize power consumption A simplified block diagram of the module is shown in Figure 131 131 Timer2 Operation In normal operation TMR2 is incremented from 00h on each clock FOSC4 A 4bit counterprescaler on the clock input gives direct input divideby4 and divideby 16 prescale options these are selected by the prescaler control bits T2CKPS10 T2CON10 The value of TMR2 is compared to that of the Period register PR2 on each clock cycle When the two values match the com parator generates a match signal as the timer output This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counterpostscaler see Section 132 Timer2 Interrupt The TMR2 and PR2 registers are both directly readable and writable The TMR2 register is cleared on any device Reset while the PR2 register initializes at FFh Both the prescaler and postscaler counters are cleared on the following events a write to the TMR2 register a write to the T2CON register any device Reset Poweron Reset MCLR Reset Watchdog Timer Reset or Brownout Reset TMR2 is not cleared when T2CON is written REGISTER 131 T2CON TIMER2 CONTROL REGISTER U0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 Unimplemented Read as 0 bit 63 T2OUTPS30 Timer2 Output Postscale Select bits 0000 11 Postscale 0001 12 Postscale 1111 116 Postscale bit 2 TMR2ON Timer2 On bit 1 Timer2 is on 0 Timer2 is off bit 10 T2CKPS10 Timer2 Clock Prescale Select bits 00 Prescaler is 1 01 Prescaler is 4 1x Prescaler is 16 PIC18F2420252044204520 DS39631Epage 134 2008 Microchip Technology Inc 132 Timer2 Interrupt Timer2 also can generate an optional device interrupt The Timer2 output signal TMR2 to PR2 match pro vides the input for the 4bit output counterpostscaler This counter generates the TMR2 match interrupt flag which is latched in TMR2IF PIR11 The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit TMR2IE PIE11 A range of 16 postscale options from 11 through 116 inclusive can be selected with the postscaler control bits T2OUTPS30 T2CON63 133 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules where it is used as a time base for operations in PWM mode Timer2 can optionally be used as the shift clock source for the MSSP module operating in SPI mode Addi tional information is provided in Section 170 Master Synchronous Serial Port MSSP Module FIGURE 131 TIMER2 BLOCK DIAGRAM TABLE 131 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMERCOUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TMR2 Timer2 Register 50 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 PR2 Timer2 Period Register 50 Legend unimplemented read as 0 Shaded cells are not used by the Timer2 module Note 1 These bits are unimplemented on 28pin devices always maintain these bits clear Comparator TMR2 Output TMR2 Postscaler Prescaler PR2 2 FOSC4 11 to 116 11 14 116 4 T2OUTPS30 T2CKPS10 Set TMR2IF Internal Data Bus 8 Reset TMR2PR2 8 8 to PWM or MSSP Match 2008 Microchip Technology Inc DS39631Epage 135 PIC18F2420252044204520 140 TIMER3 MODULE The Timer3 module timercounter incorporates these features Software selectable operation as a 16bit timer or counter Readable and writable 8bit registers TMR3H and TMR3L Selectable clock source internal or external with device clock or Timer1 oscillator internal options Interruptonoverflow Module Reset on CCP Special Event Trigger A simplified block diagram of the Timer3 module is shown in Figure 141 A block diagram of the modules operation in ReadWrite mode is shown in Figure 142 The Timer3 module is controlled through the T3CON register Register 141 It also selects the clock source options for the CCP modules see Section 1511 CCP Modules and Timer Resources for more information REGISTER 141 T3CON TIMER3 CONTROL REGISTER RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 RD16 16Bit ReadWrite Mode Enable bit 1 Enables register readwrite of Timer3 in one 16bit operation 0 Enables register readwrite of Timer3 in two 8bit operations bit 63 T3CCP21 Timer3 and Timer1 to CCPx Enable bits 1x Timer3 is the capturecompare clock source for the CCP modules 01 Timer3 is the capturecompare clock source for CCP2 Timer1 is the capturecompare clock source for CCP1 00 Timer1 is the capturecompare clock source for the CCP modules bit 54 T3CKPS10 Timer3 Input Clock Prescale Select bits 11 18 Prescale value 10 14 Prescale value 01 12 Prescale value 00 11 Prescale value bit 2 T3SYNC Timer3 External Clock Input Synchronization Control bit Not usable if the device clock comes from Timer1Timer3 When TMR3CS 1 1 Do not synchronize external clock input 0 Synchronize external clock input When TMR3CS 0 This bit is ignored Timer3 uses the internal clock when TMR3CS 0 bit 1 TMR3CS Timer3 Clock Source Select bit 1 External clock input from Timer1 oscillator or T13CKI on the rising edge after the first falling edge 0 Internal clock FOSC4 bit 0 TMR3ON Timer3 On bit 1 Enables Timer3 0 Stops Timer3 PIC18F2420252044204520 DS39631Epage 136 2008 Microchip Technology Inc 141 Timer3 Operation Timer3 can operate in one of three modes Timer Synchronous Counter Asynchronous Counter The operating mode is determined by the clock select bit TMR3CS T3CON1 When TMR3CS is cleared 0 Timer3 increments on every internal instruction cycle FOSC4 When the bit is set Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled As with Timer1 the RC1T1OSI and RC0T1OSO T13CKI pins become inputs when the Timer1 oscillator is enabled This means the values of TRISC10 are ignored and the pins are read as 0 FIGURE 141 TIMER3 BLOCK DIAGRAM FIGURE 142 TIMER3 BLOCK DIAGRAM 16BIT READWRITE MODE T3SYNC TMR3CS T3CKPS10 Sleep Input T1OSCEN1 FOSC4 Internal Clock Prescaler 1 2 4 8 Synchronize Detect 1 0 2 T1OSOT13CKI T1OSI 1 0 TMR3ON TMR3L Set TMR3IF on Overflow TMR3 High Byte Timer1 Oscillator Note 1 When enable bit T1OSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain OnOff Timer3 CCP1CCP2 Special Event Trigger CCP1CCP2 Select from T3CON63 Clear TMR3 Timer1 Clock Input T3SYNC TMR3CS T3CKPS10 Sleep Input T1OSCEN1 FOSC4 Internal Clock Prescaler 1 2 4 8 Synchronize Detect 1 0 2 T13CKIT1OSO T1OSI Note 1 When enable bit T1OSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain 1 0 TMR3L Internal Data Bus 8 Set TMR3IF on Overflow TMR3 TMR3H High Byte 8 8 8 Read TMR1L Write TMR1L 8 TMR3ON CCP1CCP2 Special Event Trigger Timer1 Oscillator OnOff Timer3 Timer1 Clock Input CCP1CCP2 Select from T3CON63 Clear TMR3 2008 Microchip Technology Inc DS39631Epage 137 PIC18F2420252044204520 142 Timer3 16Bit ReadWrite Mode Timer3 can be configured for 16bit reads and writes see Figure 142 When the RD16 control bit T3CON7 is set the address for TMR3H is mapped to a buffer register for the high byte of Timer3 A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte followed by a read of the low byte has become invalid due to a rollover between reads A write to the high byte of Timer3 must also take place through the TMR3H Buffer register The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L This allows a user to write all 16 bits to both the high and low bytes of Timer3 at once The high byte of Timer3 is not directly readable or writable in this mode All reads and writes must take place through the Timer3 High Byte Buffer register Writes to TMR3H do not clear the Timer3 prescaler The prescaler is only cleared on writes to TMR3L 143 Using the Timer1 Oscillator as the Timer3 Clock Source The Timer1 internal oscillator may be used as the clock source for Timer3 The Timer1 oscillator is enabled by setting the T1OSCEN T1CON3 bit To use it as the Timer3 clock source the TMR3CS bit must also be set As previously noted this also configures Timer3 to increment on every rising edge of the oscillator source The Timer1 oscillator is described in Section 120 Timer1 Module 144 Timer3 Interrupt The TMR3 register pair TMR3HTMR3L increments from 0000h to FFFFh and overflows to 0000h The Timer3 interrupt if enabled is generated on overflow and is latched in interrupt flag bit TMR3IF PIR21 This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit TMR3IE PIE21 145 Resetting Timer3 Using the CCP Special Event Trigger If either of the CCP modules is configured to use Timer3 and to generate a Special Event Trigger in Compare mode CCP1M30 or CCP2M30 1011 this signal will reset Timer3 It will also start an AD conver sion if the AD module is enabled see Section 1534 Special Event Trigger for more information The module must be configured as either a timer or synchronous counter to take advantage of this feature When used this way the CCPRxHCCPRxL register pair effectively becomes a Period register for Timer3 If Timer3 is running in Asynchronous Counter mode the Reset operation may not work In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP module the write will take precedence TABLE 141 REGISTERS ASSOCIATED WITH TIMER3 AS A TIMERCOUNTER Note The Special Event Triggers from the CCP2 module will not set the TMR3IF interrupt flag bit PIR10 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 TMR3L Timer3 Register Low Byte 51 TMR3H Timer3 Register High Byte 51 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51 Legend unimplemented read as 0 Shaded cells are not used by the Timer3 module PIC18F2420252044204520 DS39631Epage 138 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 139 PIC18F2420252044204520 150 CAPTURECOMPAREPWM CCP MODULES PIC18F2420252044204520 devices all have two CCP CaptureComparePWM modules Each module contains a 16bit register which can operate as a 16bit Capture register a 16bit Compare register or a PWM MasterSlave Duty Cycle register In 28pin devices the two standard CCP modules CCP1 and CCP2 operate as described in this chapter In 40 44pin devices CCP1 is implemented as an Enhanced CCP module with standard Capture and Compare modes and Enhanced PWM modes The ECCP imple mentation is discussed in Section 160 Enhanced CaptureComparePWM ECCP Module The capture and compare operations described in this chapter apply to all standard and Enhanced CCP modules Note Throughout this section and Section 160 Enhanced CaptureComparePWM ECCP Module references to the register and bit names for CCP modules are referred to gener ically by the use of x or y in place of the specific module number Thus CCPxCON might refer to the control register for CCP1 CCP2 or ECCP1 CCPxCON is used throughout these sections to refer to the mod ule control register regardless of whether the CCP module is a standard or enhanced implementation REGISTER 151 CCPxCON CCPx CONTROL REGISTER 28PIN DEVICES U0 U0 RW0 RW0 RW0 RW0 RW0 RW0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 76 Unimplemented Read as 0 bit 54 DCxB10 PWM Duty Cycle bit 1 and bit 0 for CCPx Module Capture mode Unused Compare mode Unused PWM mode These bits are the two LSbs bit 1 and bit 0 of the 10bit PWM duty cycle The eight MSbs DCxB92 of the duty cycle are found in CCPRxL bit 30 CCPxM30 CCPx Module Mode Select bits 0000 CaptureComparePWM disabled resets CCPx module 0001 Reserved 0010 Compare mode toggle output on match CCPxIF bit is set 0011 Reserved 0100 Capture mode every falling edge 0101 Capture mode every rising edge 0110 Capture mode every 4th rising edge 0111 Capture mode every 16th rising edge 1000 Compare mode initialize CCPx pin low on compare match force CCPx pin high CCPxIF bit is set 1001 Compare mode initialize CCPx pin high on compare match force CCPx pin low CCPxIF bit is set 1010 Compare mode generate software interrupt on compare match CCPxIF bit is set CCPx pin reflects IO state 1011 Compare mode trigger special event reset timer CCP2 match starts AD conversion CCPxIF bit is set 11xx PWM mode PIC18F2420252044204520 DS39631Epage 140 2008 Microchip Technology Inc 151 CCP Module Configuration Each CaptureComparePWM module is associated with a control register generically CCPxCON and a data register CCPRx The data register in turn is comprised of two 8bit registers CCPRxL low byte and CCPRxH high byte All registers are both readable and writable 1511 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers 1 2 or 3 depending on the mode selected Timer1 and Timer3 are available to modules in Capture or Compare modes while Timer2 is available for modules in PWM mode TABLE 151 CCP MODE TIMER RESOURCE The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the T3CON register Register 141 Both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode CaptureCompare or PWM at the same time The interactions between the two modules are summarized in Figure 151 and Figure 152 In Timer1 in Asynchronous Counter mode the capture operation will not work 1512 CCP2 PIN ASSIGNMENT The pin assignment for CCP2 Capture input Compare and PWM output can change based on device config uration The CCP2MX Configuration bit determines which pin CCP2 is multiplexed to By default it is assigned to RC1 CCP2MX 1 If the Configuration bit is cleared CCP2 is multiplexed with RB3 Changing the pin assignment of CCP2 does not auto matically change any requirements for configuring the port pin Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation regardless of where it is located TABLE 152 INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCPECCP Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base The time base can be different for each CCP Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3 depending upon which time base is used Automatic AD conversions on trigger event can also be done Operation of CCP1 could be affected if it is using the same timer as a time base Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 depending upon which time base is used Operation of CCP2 could be affected if it is using the same timer as a time base Compare Compare Either module can be configured for the Special Event Trigger to reset the time base Automatic AD conversions on CCP2 trigger event can be done Conflicts may occur if both modules are using the same time base Capture PWM1 None Compare PWM1 None PWM1 Capture None PWM1 Compare None PWM1 PWM1 Both PWMs will have the same frequency and update rate TMR2 interrupt Note 1 Includes standard and Enhanced PWM operation 2008 Microchip Technology Inc DS39631Epage 141 PIC18F2420252044204520 152 Capture Mode In Capture mode the CCPRxHCCPRxL register pair captures the 16bit value of the TMR1 or TMR3 register when an event occurs on the corresponding CCPx pin An event is defined as one of the following every falling edge every rising edge every 4th rising edge every 16th rising edge The event is selected by the mode select bits CCPxM30 CCPxCON30 When a capture is made the interrupt request flag bit CCPxIF is set it must be cleared in software If another capture occurs before the value in register CCPRx is read the old captured value is overwritten by the new captured value 1521 CCP PIN CONFIGURATION In Capture mode the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit 1522 TIMER1TIMER3 MODE SELECTION The timers that are to be used with the capture feature Timer1 andor Timer3 must be running in Timer mode or Synchronized Counter mode In Asynchronous Counter mode the capture operation will not work The timer to be used with each CCP module is selected in the T3CON register see Section 1511 CCP Modules and Timer Resources 1523 SOFTWARE INTERRUPT When the Capture mode is changed a false capture interrupt may be generated The user should keep the CCPxIE interrupt enable bit clear to avoid false inter rupts The interrupt flag bit CCPxIF should also be cleared following any such change in operating mode 1524 CCP PRESCALER There are four prescaler settings in Capture mode they are specified as part of the operating mode selected by the mode select bits CCPxM30 Whenever the CCP module is turned off or Capture mode is disabled the prescaler counter is cleared This means that any Reset will clear the prescaler counter Switching from one capture prescaler to another may generate an interrupt Also the prescaler counter will not be cleared therefore the first capture may be from a nonzero prescaler Example 151 shows the recommended method for switching between capture prescalers This example also clears the prescaler counter and will not generate the false interrupt EXAMPLE 151 CHANGING BETWEEN CAPTURE PRESCALERS CCP2 SHOWN FIGURE 151 CAPTURE MODE OPERATION BLOCK DIAGRAM Note If RB3CCP2 or RC1CCP2 is configured as an output a write to the port can cause a capture condition CLRF CCP2CON Turn CCP module off MOVLW NEWCAPTPS Load WREG with the new prescaler mode value and CCP ON MOVWF CCP2CON Load CCP2CON with this value CCPR1H CCPR1L TMR1H TMR1L Set CCP1IF TMR3 Enable Q1Q4 CCP1CON30 CCP1 pin Prescaler 1 4 16 and Edge Detect TMR1 Enable T3CCP2 T3CCP2 CCPR2H CCPR2L TMR1H TMR1L Set CCP2IF TMR3 Enable CCP2CON30 CCP2 pin Prescaler 1 4 16 TMR3H TMR3L TMR1 Enable T3CCP2 T3CCP1 T3CCP2 T3CCP1 TMR3H TMR3L and Edge Detect 4 4 4 PIC18F2420252044204520 DS39631Epage 142 2008 Microchip Technology Inc 153 Compare Mode In Compare mode the 16bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value When a match occurs the CCPx pin can be driven high driven low toggled hightolow or lowtohigh remain unchanged that is reflects the state of the IO latch The action on the pin is based on the value of the mode select bits CCPxM30 At the same time the interrupt flag bit CCPxIF is set 1531 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit 1532 TIMER1TIMER3 MODE SELECTION Timer1 andor Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature In Asynchronous Counter mode the compare operation may not work 1533 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen CCPxM30 1010 the corresponding CCPx pin is not affected A CCP interrupt is generated when the CCPxIF interrupt flag is set while the CCPxIE bit is set 1534 SPECIAL EVENT TRIGGER Both CCP modules are equipped with a Special Event Trigger This is an internal hardware signal generated in Compare mode to trigger actions by other modules The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode CCPxM30 1011 For either CCP module the Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the modules time base This allows the CCPRx registers to serve as a programmable Period register for either timer The Special Event Trigger for CCP2 can also start an AD conversion In order to do this the AD Converter must already be enabled FIGURE 152 COMPARE MODE OPERATION BLOCK DIAGRAM Note Clearing the CCP2CON register will force the RB3 or RC1 compare output latch depending on device configuration to the default low level This is not the PORTB or PORTC IO data latch CCPR1H CCPR1L TMR1H TMR1L Comparator Q S R Output Logic Special Event Trigger Set CCP1IF CCP1 pin TRIS CCP1CON30 Output Enable TMR3H TMR3L CCPR2H CCPR2L Comparator 1 0 T3CCP2 T3CCP1 Set CCP2IF 1 0 Compare 4 Timer1Timer3 Reset Q S R Output Logic Special Event Trigger CCP2 pin TRIS CCP2CON30 Output Enable 4 Timer1Timer3 Reset AD Trigger Match Compare Match 2008 Microchip Technology Inc DS39631Epage 143 PIC18F2420252044204520 TABLE 153 REGISTERS ASSOCIATED WITH CAPTURE COMPARE TIMER1 AND TIMER3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 RCON IPEN SBOREN RI TO PD POR BOR 48 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 TRISB PORTB Data Direction Register 52 TRISC PORTC Data Direction Register 52 TMR1L Timer1 Register Low Byte 50 TMR1H Timer1 Register High Byte 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 TMR3H Timer3 Register High Byte 51 TMR3L Timer3 Register Low Byte 51 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51 CCPR1L CaptureComparePWM Register 1 Low Byte 51 CCPR1H CaptureComparePWM Register 1 High Byte 51 CCP1CON P1M11 P1M01 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 CCPR2L CaptureComparePWM Register 2 Low Byte 51 CCPR2H CaptureComparePWM Register 2 High Byte 51 CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51 Legend unimplemented read as 0 Shaded cells are not used by CaptureCompare Timer1 or Timer3 Note 1 These bits are unimplemented on 28pin devices always maintain these bits clear PIC18F2420252044204520 DS39631Epage 144 2008 Microchip Technology Inc 154 PWM Mode In PulseWidth Modulation PWM mode the CCPx pin produces up to a 10bit resolution PWM output Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch the appropriate TRIS bit must be cleared to make the CCP2 pin an output Figure 153 shows a simplified block diagram of the CCP module in PWM mode For a stepbystep procedure on how to set up the CCP module for PWM operation see Section 1544 Setup for PWM Operation FIGURE 153 SIMPLIFIED PWM BLOCK DIAGRAM A PWM output Figure 154 has a time base period and a time that the output stays high duty cycle The frequency of the PWM is the inverse of the period 1period FIGURE 154 PWM OUTPUT 1541 PWM PERIOD The PWM period is specified by writing to the PR2 register The PWM period can be calculated using the following formula EQUATION 151 PWM frequency is defined as 1PWM period When TMR2 is equal to PR2 the following three events occur on the next increment cycle TMR2 is cleared The CCPx pin is set exception if PWM duty cycle 0 the CCPx pin will not be set The PWM duty cycle is latched from CCPRxL into CCPRxH 1542 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON54 bits Up to 10bit resolution is available The CCPRxL contains the eight MSbs and the CCPxCON54 bits contain the two LSbs This 10bit value is represented by CCPRxLCCPxCON54 The following equation is used to calculate the PWM duty cycle in time EQUATION 152 CCPRxL and CCPxCON54 can be written to at any time but the duty cycle value is not latched into CCPRxH until after a match between PR2 and TMR2 occurs ie the period is complete In PWM mode CCPRxH is a readonly register Note Clearing the CCP2CON register will force the RB3 or RC1 output latch depending on device configuration to the default low level This is not the PORTB or PORTC IO data latch CCPRxL CCPRxH Slave Comparator TMR2 Comparator PR2 Note 1 R Q S Duty Cycle Registers CCPxCON54 Clear Timer CCPx pin and latch DC Note 1 The 8bit TMR2 value is concatenated with the 2bit internal Q clock or 2 bits of the prescaler to create the 10bit time base CCPx Output Corresponding TRIS bit Period Duty Cycle TMR2 PR2 TMR2 Duty Cycle TMR2 PR2 Note The Timer2 postscalers see Section 130 Timer2 Module are not used in the determination of the PWM frequency The postscaler could be used to have a servo update rate at a different frequency than the PWM output PWM Period PR2 1 4 TOSC TMR2 Prescale Value PWM Duty Cycle CCPRXLCCPXCON54 TOSC TMR2 Prescale Value 2008 Microchip Technology Inc DS39631Epage 145 PIC18F2420252044204520 The CCPRxH register and a 2bit internal latch are used to doublebuffer the PWM duty cycle This doublebuffering is essential for glitchless PWM operation When the CCPRxH and 2bit latch match TMR2 concatenated with an internal 2bit Q clock or 2 bits of the TMR2 prescaler the CCPx pin is cleared The maximum PWM resolution bits for a given PWM frequency is given by the equation EQUATION 153 TABLE 154 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz 1543 PWM AUTOSHUTDOWN CCP1 ONLY The PWM autoshutdown features of the Enhanced CCP module are also available to CCP1 in 28pin devices The operation of this feature is discussed in detail in Section 1647 Enhanced PWM AutoShutdown Autoshutdown features are not available for CCP2 1544 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation 1 Set the PWM period by writing to the PR2 register 2 Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON54 bits 3 Make the CCPx pin an output by clearing the appropriate TRIS bit 4 Set the TMR2 prescale value then enable Timer2 by writing to T2CON 5 Configure the CCPx module for PWM operation Note If the PWM duty cycle value is longer than the PWM period the CCPx pin will not be cleared FOSC FPWM log 2 log bits PWM Resolution max PWM Frequency 244 kHz 977 kHz 3906 kHz 15625 kHz 31250 kHz 41667 kHz Timer Prescaler 1 4 16 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution bits 10 10 10 8 7 658 PIC18F2420252044204520 DS39631Epage 146 2008 Microchip Technology Inc TABLE 155 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 RCON IPEN SBOREN RI TO PD POR BOR 48 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TRISB PORTB Data Direction Register 52 TRISC PORTC Data Direction Register 52 TMR2 Timer2 Register 50 PR2 Timer2 Period Register 50 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 CCPR1L CaptureComparePWM Register 1 Low Byte 51 CCPR1H CaptureComparePWM Register 1 High Byte 51 CCP1CON P1M11 P1M01 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 CCPR2L CaptureComparePWM Register 2 Low Byte 51 CCPR2H CaptureComparePWM Register 2 High Byte 51 CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD11 PSSBD01 51 PWM1CON PRSEN PDC61 PDC51 PDC41 PDC31 PDC21 PDC11 PDC01 51 Legend unimplemented read as 0 Shaded cells are not used by PWM or Timer2 Note 1 These bits are unimplemented on 28pin devices always maintain these bits clear 2008 Microchip Technology Inc DS39631Epage 147 PIC18F2420252044204520 160 ENHANCED CAPTURE COMPAREPWM ECCP MODULE In PIC18F44204520 devices CCP1 is implemented as a standard CCP module with Enhanced PWM capabilities These include the provision for 2 or 4 output channels userselectable polarity deadband control and automatic shutdown and restart The enhanced features are discussed in detail in Section 164 Enhanced PWM Mode Capture Compare and single output PWM functions of the ECCP module are the same as described for the standard CCP module The control register for the Enhanced CCP module is shown in Register 162 It differs from the CCPxCON registers in PIC18F24202520 devices in that the two Most Significant bits are implemented to control PWM functionality Note The ECCP module is implemented only in 4044pin devices REGISTER 161 CCP1CON ECCP CONTROL REGISTER 4044PIN DEVICES RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 76 P1M10 Enhanced PWM Output Configuration bits If CCP1M3CCP1M2 00 01 10 xx P1A assigned as capturecompare inputoutput P1B P1C P1D assigned as port pins If CCP1M3CCP1M2 11 00 Single output P1A modulated P1B P1C P1D assigned as port pins 01 Fullbridge output forward P1D modulated P1A active P1B P1C inactive 10 Halfbridge output P1A P1B modulated with deadband control P1C P1D assigned as port pins 11 Fullbridge output reverse P1B modulated P1C active P1A P1D inactive bit 54 DC1B10 PWM Duty Cycle bit 1 and bit 0 Capture mode Unused Compare mode Unused PWM mode These bits are the two LSbs of the 10bit PWM duty cycle The eight MSbs of the duty cycle are found in CCPR1L bit 30 CCP1M30 Enhanced CCP Mode Select bits 0000 CaptureComparePWM off resets ECCP module 0001 Reserved 0010 Compare mode toggle output on match 0011 Capture mode 0100 Capture mode every falling edge 0101 Capture mode every rising edge 0110 Capture mode every 4th rising edge 0111 Capture mode every 16th rising edge 1000 Compare mode initialize CCP1 pin low set output on compare match set CCP1IF 1001 Compare mode initialize CCP1 pin high clear output on compare match set CCP1IF 1010 Compare mode generate software interrupt only CCP1 pin reverts to IO state 1011 Compare mode trigger special event ECCP resets TMR1 or TMR3 sets CCP1IF bit 1100 PWM mode P1A P1C activehigh P1B P1D activehigh 1101 PWM mode P1A P1C activehigh P1B P1D activelow 1110 PWM mode P1A P1C activelow P1B P1D activehigh 1111 PWM mode P1A P1C activelow P1B P1D activelow PIC18F2420252044204520 DS39631Epage 148 2008 Microchip Technology Inc In addition to the expanded range of modes available through the CCP1CON register and ECCP1AS register the ECCP module has an additional register associated with Enhanced PWM operation and autoshutdown features It is PWM1CON PWM DeadBand Delay 161 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs depending on the selected operating mode These outputs designated P1A through P1D are multiplexed with IO pins on PORTC and PORTD The outputs that are active depend on the CCP operating mode selected The pin assignments are summarized in Table 161 To configure the IO pins as PWM outputs the proper PWM mode must be selected by setting the P1M10 and CCP1M30 bits The appropriate TRISC and TRISD direction bits for the port pins must also be set as outputs 1611 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules the ECCP module can utilize Timers 1 2 or 3 depending on the mode selected Timer1 and Timer3 are available for modules in Capture or Compare modes while Timer2 is avail able for modules in PWM mode Interactions between the standard and Enhanced CCP modules are identical to those described for standard CCP modules Additional details on timer resources are provided in Section 1511 CCP Modules and Timer Resources 162 Capture and Compare Modes Except for the operation of the Special Event Trigger discussed below the Capture and Compare modes of the ECCP module are identical in operation to that of CCP2 These are discussed in detail in Section 152 Capture Mode and Section 153 Compare Mode No changes are required when moving between 28pin and 4044pin devices 1621 SPECIAL EVENT TRIGGER The Special Event Trigger output of ECCP resets the TMR1 or TMR3 register pair depending on which timer resource is currently selected This allows the CCPR1 register to effectively be a 16Bit Programmable Period register for Timer1 or Timer3 163 Standard PWM Mode When configured in Single Output mode the ECCP module functions identically to the standard CCP module in PWM mode as described in Section 154 PWM Mode This is also sometimes referred to as Compatible CCP mode as in Table 161 TABLE 161 PIN ASSIGNMENTS FOR VARIOUS ECCP MODES Note When setting up single output PWM operations users are free to use either of the processes described in Section 1544 Setup for PWM Operation or Section 1649 Setup for PWM Opera tion The latter is more generic and will work for either single or multioutput PWM ECCP Mode CCP1CON Configuration RC2 RD5 RD6 RD7 All 4044Pin Devices Compatible CCP 00xx 11xx CCP1 RD5PSP5 RD6PSP6 RD7PSP7 Dual PWM 10xx 11xx P1A P1B RD6PSP6 RD7PSP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend x Dont care Shaded cells indicate pin assignments not used by ECCP in a given mode 2008 Microchip Technology Inc DS39631Epage 149 PIC18F2420252044204520 164 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applica tions The module is a backward compatible version of the standard CCP module and offers up to four outputs designated P1A through P1D Users are also able to select the polarity of the signal either activehigh or activelow The modules output mode and polarity are configured by setting the P1M10 and CCP1M30 bits of the CCP1CON register Figure 161 shows a simplified block diagram of PWM operation All control registers are doublebuffered and are loaded at the beginning of a new PWM cycle the period boundary when Timer2 resets in order to pre vent glitches on any of the outputs The exception is the PWM DeadBand Delay register PWM1CON which is loaded at either the duty cycle boundary or the period boundary whichever comes first Because of the buff ering the module waits until the assigned timer resets instead of starting immediately This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle 4 TOSC As before the user must manually configure the appropriate TRIS bits for output 1641 PWM PERIOD The PWM period is specified by writing to the PR2 register The PWM period can be calculated using the following equation EQUATION 161 PWM frequency is defined as 1PWM period When TMR2 is equal to PR2 the following three events occur on the next increment cycle TMR2 is cleared The CCP1 pin is set if PWM duty cycle 0 the CCP1 pin will not be set The PWM duty cycle is copied from CCPR1L into CCPR1H FIGURE 161 SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE Note The Timer2 postscaler see Section 130 Timer2 Module is not used in the determination of the PWM frequency The postscaler could be used to have a servo update rate at a different frequency than the PWM output PWM Period PR2 1 4 TOSC TMR2 Prescale Value CCPR1L CCPR1H Slave Comparator TMR2 Comparator PR2 Note 1 R Q S Duty Cycle Registers CCP1CON54 Clear Timer set CCP1 pin and latch DC Note The 8bit TMR2 register is concatenated with the 2bit internal Q clock or 2 bits of the prescaler to create the 10bit time base TRISxx CCP1P1A TRISxx P1B TRISxx TRISxx P1D Output Controller P1M110 2 CCP1M30 4 PWM1CON CCP1P1A P1B P1C P1D P1C PIC18F2420252044204520 DS39631Epage 150 2008 Microchip Technology Inc 1642 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON54 bits Up to 10bit resolution is available The CCPR1L contains the eight MSbs and the CCP1CON54 bits contain the two LSbs This 10bit value is represented by CCPR1LCCP1CON54 The PWM duty cycle is calculated by the following equation EQUATION 162 CCPR1L and CCP1CON54 can be written to at any time but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs ie the period is complete In PWM mode CCPR1H is a readonly register The CCPR1H register and a 2bit internal latch are used to doublebuffer the PWM duty cycle This doublebuffering is essential for glitchless PWM opera tion When the CCPR1H and 2bit latch match TMR2 concatenated with an internal 2bit Q clock or two bits of the TMR2 prescaler the CCP1 pin is cleared The maximum PWM resolution bits for a given PWM frequency is given by the following equation EQUATION 163 1643 PWM OUTPUT CONFIGURATIONS The P1M10 bits in the CCP1CON register allow one of four configurations Single Output HalfBridge Output FullBridge Output Forward mode FullBridge Output Reverse mode The Single Output mode is the standard PWM mode discussed in Section 164 Enhanced PWM Mode The HalfBridge and FullBridge Output modes are covered in detail in the sections that follow The general relationship of the outputs in all configurations is summarized in Figure 162 and Figure 163 TABLE 162 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Duty Cycle CCPR1LCCP1CON54 TOSC TMR2 Prescale Value Note If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared PWM Resolution max FOSC FPWM log log2 bits PWM Frequency 244 kHz 977 kHz 3906 kHz 15625 kHz 31250 kHz 41667 kHz Timer Prescaler 1 4 16 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution bits 10 10 10 8 7 658 2008 Microchip Technology Inc DS39631Epage 151 PIC18F2420252044204520 FIGURE 162 PWM OUTPUT RELATIONSHIPS ACTIVEHIGH STATE FIGURE 163 PWM OUTPUT RELATIONSHIPS ACTIVELOW STATE 0 Period 00 10 01 11 SIGNAL PR2 1 CCP1CON76 P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated P1A Inactive P1B Modulated P1C Active P1D Inactive Duty Cycle Single Output HalfBridge FullBridge Forward FullBridge Reverse Delay1 Delay1 0 Period 00 10 01 11 SIGNAL PR2 1 CCP1CON76 P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated P1A Inactive P1B Modulated P1C Active P1D Inactive Duty Cycle Single Output HalfBridge FullBridge Forward FullBridge Reverse Delay1 Delay1 Relationships Period 4 TOSC PR2 1 TMR2 Prescale Value Duty Cycle TOSC CCPR1L70CCP1CON54 TMR2 Prescale Value Delay 4 TOSC PWM1CON60 Note 1 Deadband delay is programmed using the PWM1CON register see Section 1646 Programmable DeadBand Delay PIC18F2420252044204520 DS39631Epage 152 2008 Microchip Technology Inc 1644 HALFBRIDGE MODE In the HalfBridge Output mode two pins are used as outputs to drive pushpull loads The PWM output signal is output on the P1A pin while the complementary PWM output signal is output on the P1B pin Figure 164 This mode can be used for halfbridge applications as shown in Figure 165 or for fullbridge applications where four power switches are being modulated with two PWM signals In HalfBridge Output mode the programmable dead band delay can be used to prevent shootthrough current in halfbridge power devices The value of bits PDC60 sets the number of instruction cycles before the output is driven active If the value is greater than the duty cycle the corresponding output remains inactive during the entire cycle See Section 1646 Programmable DeadBand Delay for more details of the deadband delay operations Since the P1A and P1B outputs are multiplexed with the PORTC2 and PORTD5 data latches the TRISC2 and TRISD5 bits must be cleared to configure P1A and P1B as outputs FIGURE 164 HALFBRIDGE PWM OUTPUT FIGURE 165 EXAMPLES OF HALFBRIDGE OUTPUT MODE APPLICATIONS Period Duty Cycle td td 1 P1A2 P1B2 td DeadBand Delay Period 1 1 Note 1 At this time the TMR2 register is equal to the PR2 register 2 Output signals are shown as activehigh PIC18F4X2X P1A P1B FET Driver FET Driver V V Load V V FET Driver FET Driver V V Load FET Driver FET Driver PIC18F4X2X P1A P1B Standard HalfBridge Circuit PushPull HalfBridge Output Driving a FullBridge Circuit 2008 Microchip Technology Inc DS39631Epage 153 PIC18F2420252044204520 1645 FULLBRIDGE MODE In FullBridge Output mode four pins are used as outputs however only two outputs are active at a time In the Forward mode pin P1A is continuously active and pin P1D is modulated In the Reverse mode pin P1C is continuously active and pin P1B is modulated These are illustrated in Figure 166 P1A P1B P1C and P1D outputs are multiplexed with the PORTC2 and PORTD75 data latches The TRISC2 and TRISD75 bits must be cleared to make the P1A P1B P1C and P1D pins outputs FIGURE 166 FULLBRIDGE PWM OUTPUT Period Duty Cycle P1A2 P1B2 P1C2 P1D2 Forward Mode 1 Period Duty Cycle P1A2 P1C2 P1D2 P1B2 Reverse Mode 1 1 1 Note 1 At this time the TMR2 register is equal to the PR2 register Note 2 Output signal is shown as activehigh PIC18F2420252044204520 DS39631Epage 154 2008 Microchip Technology Inc FIGURE 167 EXAMPLE OF FULLBRIDGE OUTPUT MODE APPLICATION 16451 Direction Change in FullBridge Mode In the FullBridge Output mode the P1M1 bit in the CCP1CON register allows user to control the forward reverse direction When the application firmware changes this direction control bit the module will assume the new direction on the next PWM cycle Just before the end of the current PWM period the modulated outputs P1B and P1D are placed in their inactive state while the unmodulated outputs P1A and P1C are switched to drive in the opposite direction This occurs in a time interval of 4 TOSC Timer2 Prescale Value before the next PWM period begins The Timer2 prescaler will be either 1 4 or 16 depend ing on the value of the T2CKPS10 bits T2CON10 During the interval from the switch of the unmodulated outputs to the beginning of the next period the modulated outputs P1B and P1D remain inactive This relationship is shown in Figure 168 Note that in the FullBridge Output mode the CCP1 module does not provide any deadband delay In gen eral since only one output is modulated at all times deadband delay is not required However there is a situation where a deadband delay might be required This situation occurs when both of the following conditions are true 1 The direction of the PWM output changes when the duty cycle of the output is at or near 100 2 The turnoff time of the power switch including the power device and driver circuit is greater than the turnon time Figure 169 shows an example where the PWM direction changes from forward to reverse at a near 100 duty cycle At time t1 the outputs P1A and P1D become inactive while output P1C becomes active In this example since the turnoff time of the power devices is longer than the turnon time a shootthrough current may flow through power devices QC and QD see Figure 167 for the duration of t The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward If changing PWM direction at high duty cycle is required for an application one of the following requirements must be met 1 Reduce PWM for a PWM period before changing directions 2 Use switch drivers that can drive the switches off faster than they can drive them on Other options to prevent shootthrough current may exist P1A P1C FET Driver FET Driver V V Load FET Driver FET Driver P1B P1D QA QB QD QC PIC18F4X2X 2008 Microchip Technology Inc DS39631Epage 155 PIC18F2420252044204520 FIGURE 168 PWM DIRECTION CHANGE FIGURE 169 PWM DIRECTION CHANGE AT NEAR 100 DUTY CYCLE DC Period1 SIGNAL Note 1 The direction bit in the CCP1 Control register CCP1CON7 is written any time during the PWM cycle 2 When changing directions the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC 16 TOSC or 64 TOSC depending on the Timer2 prescaler value The modulated P1B and P1D signals are inactive at this time Period Note 2 P1A ActiveHigh P1B ActiveHigh P1C ActiveHigh P1D ActiveHigh DC Forward Period Reverse Period P1A1 tON 2 tOFF 3 t tOFF tON 23 P1B1 P1C1 P1D1 External Switch D1 Potential ShootThrough Current1 Note 1 All signals are shown as activehigh 2 tON is the turnon delay of power switch QC and its driver 3 tOFF is the turnoff delay of power switch QD and its driver External Switch C1 t1 DC DC PIC18F2420252044204520 DS39631Epage 156 2008 Microchip Technology Inc 1646 PROGRAMMABLE DEADBAND DELAY In halfbridge applications where all power switches are modulated at the PWM frequency at all times the power switches normally require more time to turn off than to turn on If both the upper and lower power switches are switched at the same time one turned on and the other turned off both switches may be on for a short period of time until one switch completely turns off During this brief interval a very high current shoot through current may flow through both power switches shorting the bridge supply To avoid this potentially destructive shootthrough current from flow ing during switching turning on either of the power switches is normally delayed to allow the other switch to completely turn off In the HalfBridge Output mode a digitally programmable deadband delay is available to avoid shootthrough current from destroying the bridge power switches The delay occurs at the signal transition from the nonactive state to the active state see Figure 164 for illustration Bits PDC60 of the PWM1CON register Register 162 set the delay period in terms of micro controller instruction cycles TCY or 4 TOSC These bits are not available on 28pin devices as the standard CCP module does not support halfbridge operation 1647 ENHANCED PWM AUTOSHUTDOWN When the CCP1 is programmed for any of the Enhanced PWM modes the active output pins may be configured for autoshutdown Autoshutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs A shutdown event can be caused by either of the comparator modules a low level on the Fault input pin FLT0 or any combination of these three sources The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit If the voltage exceeds a threshold the comparator switches state and triggers a shutdown Alternatively a low digital signal on FLT0 can also trigger a shutdown The autoshutdown feature can be disabled by not selecting any autoshutdown sources The auto shutdown sources to be used are selected using the ECCPAS20 bits ECCP1AS64 When a shutdown occurs the output pins are asynchronously placed in their shutdown states specified by the PSSAC10 and PSSBD10 bits ECCPAS20 Each pin pair P1AP1C and P1B P1D may be set to drive high drive low or be tristated not driving The ECCPASE bit ECCP1AS7 is also set to hold the Enhanced PWM outputs in their shutdown states The ECCPASE bit is set by hardware when a shutdown event occurs If automatic restarts are not enabled the ECCPASE bit is cleared by firmware when the cause of the shutdown clears If automatic restarts are enabled the ECCPASE bit is automatically cleared when the cause of the autoshutdown has cleared If the ECCPASE bit is set when a PWM period begins the PWM outputs remain in their shutdown state for that entire PWM period When the ECCPASE bit is cleared the PWM outputs will return to normal operation at the beginning of the next PWM period Note Programmable deadband delay is not implemented in 28pin devices with standard CCP modules Note Writing to the ECCPASE bit is disabled while a shutdown condition is active REGISTER 162 PWM1CON PWM DEADBAND DELAY REGISTER RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 PRSEN PDC61 PDC51 PDC41 PDC31 PDC21 PDC11 PDC01 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 PRSEN PWM Restart Enable bit 1 Upon autoshutdown the ECCPASE bit clears automatically once the shutdown event goes away the PWM restarts automatically 0 Upon autoshutdown ECCPASE must be cleared in software to restart the PWM bit 60 PDC6PDC0 PWM Delay Count bits1 Delay time in number of FOSC4 4 TOSC cycles between the scheduled and actual time for a PWM signal to transition to active Note 1 Reserved on 28pin devices maintain these bits clear 2008 Microchip Technology Inc DS39631Epage 157 PIC18F2420252044204520 REGISTER 163 ECCP1AS ECCP AUTOSHUTDOWN CONTROL REGISTER RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD11 PSSBD01 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 ECCPASE ECCP AutoShutdown Event Status bit 1 A shutdown event has occurred ECCP outputs are in shutdown state 0 ECCP outputs are operating bit 64 ECCPAS20 ECCP AutoShutdown Source Select bits 111 FLT0 or Comparator 1 or Comparator 2 110 FLT0 or Comparator 2 101 FLT0 or Comparator 1 100 FLT0 011 Either Comparator 1 or 2 010 Comparator 2 output 001 Comparator 1 output 000 Autoshutdown is disabled bit 32 PSSAC10 Pins A and C Shutdown State Control bits 1x Pins A and C are tristate 4044pin devices PWM output is tristate 28pin devices 01 Drive Pins A and C to 1 00 Drive Pins A and C to 0 bit 10 PSSBD10 Pins B and D Shutdown State Control bits1 1x Pins B and D tristate 01 Drive Pins B and D to 1 00 Drive Pins B and D to 0 Note 1 Reserved on 28pin devices maintain these bits clear PIC18F2420252044204520 DS39631Epage 158 2008 Microchip Technology Inc 16471 AutoShutdown and Automatic Restart The autoshutdown feature can be configured to allow automatic restarts of the module following a shutdown event This is enabled by setting the PRSEN bit of the PWM1CON register PWM1CON7 In Shutdown mode with PRSEN 1 Figure 1610 the ECCPASE bit will remain set for as long as the cause of the shutdown continues When the shutdown condi tion clears the ECCPASE bit is cleared If PRSEN 0 Figure 1611 once a shutdown condition occurs the ECCPASE bit will remain set until it is cleared by firm ware Once ECCPASE is cleared the Enhanced PWM will resume at the beginning of the next PWM period Independent of the PRSEN bit setting if the auto shutdown source is one of the comparators the shutdown condition is a level The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists The AutoShutdown mode can be forced by writing a 1 to the ECCPASE bit 1648 STARTUP CONSIDERATIONS When the ECCP module is used in the PWM mode the application hardware must use the proper external pull up andor pulldown resistors on the PWM output pins When the microcontroller is released from Reset all of the IO pins are in the highimpedance state The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the IO pins with the proper signal levels or activates the PWM outputs The CCP1M10 bits CCP1CON10 allow the user to choose whether the PWM output signals are activehigh or activelow for each pair of PWM output pins P1AP1C and P1BP1D The PWM output polarities must be selected before the PWM pins are configured as outputs Changing the polarity configura tion while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits The P1A P1B P1C and P1D output latches may not be in the proper states when the PWM module is initialized Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the applica tion circuit The ECCP module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs The com pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins FIGURE 1610 PWM AUTOSHUTDOWN PRSEN 1 AUTORESTART ENABLED FIGURE 1611 PWM AUTOSHUTDOWN PRSEN 0 AUTORESTART DISABLED Note Writing to the ECCPASE bit is disabled while a shutdown condition is active Shutdown PWM ECCPASE bit Activity Event Shutdown Event Occurs Shutdown Event Clears PWM Resumes Normal PWM Start of PWM Period PWM Period Shutdown PWM ECCPASE bit Activity Event Shutdown Event Occurs Shutdown Event Clears PWM Resumes Normal PWM Start of PWM Period ECCPASE Cleared by Firmware PWM Period 2008 Microchip Technology Inc DS39631Epage 159 PIC18F2420252044204520 1649 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation 1 Configure the PWM pins P1A and P1B and P1C and P1D if used as inputs by setting the corresponding TRIS bits 2 Set the PWM period by loading the PR2 register 3 If autoshutdown is required Disable autoshutdown ECCPASE 0 Configure source FLT0 Comparator 1 or Comparator 2 Wait for nonshutdown condition 4 Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values Select one of the available output configurations and direction with the P1M10 bits Select the polarities of the PWM output signals with the CCP1M30 bits 5 Set the PWM duty cycle by loading the CCPR1L register and CCP1CON54 bits 6 For HalfBridge Output mode set the dead band delay by loading PWM1CON60 with the appropriate value 7 If autoshutdown operation is required load the ECCP1AS register Select the autoshutdown sources using the ECCPAS20 bits Select the shutdown states of the PWM output pins using the PSSAC10 and PSSBD10 bits Set the ECCPASE bit ECCP1AS7 Configure the comparators using the CMCON register Configure the comparator inputs as analog inputs 8 If autorestart operation is required set the PRSEN bit PWM1CON7 9 Configure and start TMR2 Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit PIR11 Set the TMR2 prescale value by loading the T2CKPS bits T2CON10 Enable Timer2 by setting the TMR2ON bit T2CON2 10 Enable PWM outputs after a new PWM cycle has started Wait until TMRx overflows TMRxIF bit is set Enable the CCP1P1A P1B P1C andor P1D pin outputs by clearing the respective TRIS bits Clear the ECCPASE bit ECCP1AS7 16410 OPERATION IN POWERMANAGED MODES In Sleep mode all clock sources are disabled Timer2 will not increment and the state of the module will not change If the ECCP pin is driving a value it will con tinue to drive that value When the device wakes up it will continue from this state If TwoSpeed Startups are enabled the initial startup frequency from INTOSC and the postscaler may not be stable immediately In PRIIDLE mode the primary clock will continue to clock the ECCP module without change In all other powermanaged modes the selected powermanaged mode clock will clock Timer2 Other powermanaged mode clocks will most likely be different than the primary clock frequency 164101 Operation with FailSafe Clock Monitor If the FailSafe Clock Monitor is enabled a clock failure will force the device into the powermanaged RCRUN mode and the OSCFIF bit PIR27 will be set The ECCP will then be clocked from the internal oscillator clock source which may have a different clock frequency than the primary clock See the previous section for additional details 16411 EFFECTS OF A RESET Both Poweron Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module PIC18F2420252044204520 DS39631Epage 160 2008 Microchip Technology Inc TABLE 163 REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 RCON IPEN SBOREN RI TO PD POR BOR 48 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 TRISB PORTB Data Direction Register 52 TRISC PORTC Data Direction Register 52 TRISD PORTD Data Direction Register 52 TMR1L Timer1 Register Low Byte 50 TMR1H Timer1 Register High Byte 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 TMR2 Timer2 Register 50 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 PR2 Timer2 Period Register 50 TMR3L Timer3 Register Low Byte 51 TMR3H Timer3 Register High Byte 51 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51 CCPR1L CaptureComparePWM Register 1 Low Byte 51 CCPR1H CaptureComparePWM Register 1 High Byte 51 CCP1CON P1M11 P1M01 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD11 PSSBD01 51 PWM1CON PRSEN PDC61 PDC51 PDC41 PDC31 PDC21 PDC11 PDC01 51 Legend unimplemented read as 0 Shaded cells are not used during ECCP operation Note 1 These bits are unimplemented on 28pin devices always maintain these bits clear 2008 Microchip Technology Inc DS39631Epage 161 PIC18F2420252044204520 170 MASTER SYNCHRONOUS SERIAL PORT MSSP MODULE 171 Master SSP MSSP Module Overview The Master Synchronous Serial Port MSSP module is a serial interface useful for communicating with other peripheral or microcontroller devices These peripheral devices may be serial EEPROMs shift registers display drivers AD Converters etc The MSSP module can operate in one of two modes Serial Peripheral Interface SPI InterIntegrated Circuit I2C Full Master mode Slave mode with general address call The I2C interface supports the following modes in hardware Master mode MultiMaster mode Slave mode 172 Control Registers The MSSP module has three associated registers These include a status register SSPSTAT and two control registers SSPCON1 and SSPCON2 The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode Additional details are provided under the individual sections 173 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously All four modes of SPI are supported To accomplish communication typically three pins are used Serial Data Out SDO RC5SDO Serial Data In SDI RC4SDISDA Serial Clock SCK RC3SCKSCL Additionally a fourth pin may be used when in a Slave mode of operation Slave Select SS RA5SS Figure 171 shows the block diagram of the MSSP module when operating in SPI mode FIGURE 171 MSSP BLOCK DIAGRAM SPI MODE Read Write Internal Data Bus SSPSR reg SSPM30 bit 0 Shift Clock SS Control Enable Edge Select Clock Select TMR2 Output Prescaler TOSC 4 16 64 2 Edge Select 2 4 Data to TXRX in SSPSR TRIS bit 2 SMPCKE RC5SDO SSPBUF reg RC4SDISDA RA5AN4SS RC3SCK SCL HLVDINC2OUT PIC18F2420252044204520 DS39631Epage 162 2008 Microchip Technology Inc 1731 REGISTERS The MSSP module has four registers for SPI mode operation These are MSSP Control Register 1 SSPCON1 MSSP Status Register SSPSTAT Serial ReceiveTransmit Buffer Register SSPBUF MSSP Shift Register SSPSR Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation The SSPCON1 regis ter is readable and writable The lower 6 bits of the SSPSTAT are readonly The upper two bits of the SSPSTAT are readwrite SSPSR is the shift register used for shifting data in or out SSPBUF is the buffer register to which data bytes are written to or read from In receive operations SSPSR and SSPBUF together create a doublebuffered receiver When SSPSR receives a complete byte it is transferred to SSPBUF and the SSPIF interrupt is set During transmission the SSPBUF is not double buffered A write to SSPBUF will write to both SSPBUF and SSPSR REGISTER 171 SSPSTAT MSSP STATUS REGISTER SPI MODE RW0 RW0 R0 R0 R0 R0 R0 R0 SMP CKE1 DA P S RW UA BF bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 SMP Sample bit SPI Master mode 1 Input data sampled at end of data output time 0 Input data sampled at middle of data output time SPI Slave mode SMP must be cleared when SPI is used in Slave mode bit 6 CKE SPI Clock Select bit1 1 Transmit occurs on transition from active to Idle clock state 0 Transmit occurs on transition from Idle to active clock state bit 5 DA DataAddress bit Used in I2C mode only bit 4 P Stop bit Used in I2C mode only This bit is cleared when the MSSP module is disabled SSPEN is cleared bit 3 S Start bit Used in I2C mode only bit 2 RW ReadWrite Information bit Used in I2C mode only bit 1 UA Update Address bit Used in I2C mode only bit 0 BF Buffer Full Status bit Receive mode only 1 Receive complete SSPBUF is full 0 Receive not complete SSPBUF is empty Note 1 Polarity of clock state is set by the CKP bit SSPCON14 2008 Microchip Technology Inc DS39631Epage 163 PIC18F2420252044204520 REGISTER 172 SSPCON1 MSSP CONTROL REGISTER 1 SPI MODE RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 WCOL SSPOV1 SSPEN2 CKP SSPM33 SSPM23 SSPM13 SSPM03 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 WCOL Write Collision Detect bit 1 The SSPxBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision bit 6 SSPOV Receive Overflow Indicator bit1 SPI Slave mode 1 A new byte is received while the SSPBUF register is still holding the previous data In case of over flow the data in SSPSR is lost Overflow can only occur in Slave mode The user must read the SSPBUF even if only transmitting data to avoid setting overflow must be cleared in software 0 No overflow bit 5 SSPEN Master Synchronous Serial Port Enable bit2 1 Enables serial port and configures SCK SDO SDI and SS as serial port pins 0 Disables serial port and configures these pins as IO port pins bit 4 CKP Clock Polarity Select bit 1 Idle state for clock is a high level 0 Idle state for clock is a low level bit 30 SSPM30 Master Synchronous Serial Port Mode Select bits3 0101 SPI Slave mode clock SCK pin SS pin control disabled SS can be used as IO pin 0100 SPI Slave mode clock SCK pin SS pin control enabled 0011 SPI Master mode clock TMR2 output2 0010 SPI Master mode clock FOSC64 0001 SPI Master mode clock FOSC16 0000 SPI Master mode clock FOSC4 Note 1 In Master mode the overflow bit is not set since each new reception and transmission is initiated by writing to the SSPBUF register 2 When enabled these pins must be properly configured as input or output 3 Bit combinations not specifically listed here are either reserved or implemented in I2C mode only PIC18F2420252044204520 DS39631Epage 164 2008 Microchip Technology Inc 1732 OPERATION When initializing the SPI several options need to be specified This is done by programming the appropriate control bits SSPCON150 and SSPSTAT76 These control bits allow the following to be specified Master mode SCK is the clock output Slave mode SCK is the clock input Clock Polarity Idle state of SCK Data Input Sample Phase middle or end of data output time Clock Edge output data on risingfalling edge of SCK Clock Rate Master mode only Slave Select mode Slave mode only The MSSP consists of a transmitreceive shift register SSPSR and a buffer register SSPBUF The SSPSR shifts the data in and out of the device MSb first The SSPBUF holds the data that was written to the SSPSR until the received data is ready Once the 8 bits of data have been received that byte is moved to the SSPBUF register Then the Buffer Full detect bit BF SSPSTAT0 and the interrupt flag bit SSPIF are set This doublebuffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received Any write to the SSPBUF register during transmissionreception of data will be ignored and the write collision detect bit WCOL SSPCON17 will be set User software must clear the WCOL bit so that it can be determined if the follow ing writes to the SSPBUF register completed successfully When the application software is expecting to receive valid data the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF The Buffer Full bit BF SSPSTAT0 indicates when SSPBUF has been loaded with the received data transmission is complete When the SSPBUF is read the BF bit is cleared This data may be irrelevant if the SPI is only a transmitter Generally the MSSP interrupt is used to determine when the transmissionreception has completed The SSPBUF must be read andor written If the interrupt method is not going to be used then software polling can be done to ensure that a write collision does not occur Example 171 shows the loading of the SSPBUF SSPSR for data transmission The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register Additionally the MSSP Status register SSPSTAT indicates the various status conditions EXAMPLE 171 LOADING THE SSPBUF SSPSR REGISTER Note The SSPBUF register cannot be used with readmodifywrite instructions such as BCF BTFSC and COMF etc LOOP BTFSS SSPSTAT BF Has data been received transmit complete BRA LOOP No MOVF SSPBUF W WREG reg contents of SSPBUF MOVWF RXDATA Save in user RAM if data is meaningful MOVF TXDATA W W reg contents of TXDATA MOVWF SSPBUF New data to xmit Note To avoid lost data in Master mode a read of the SSPBUF must be performed to clear the Buffer Full BF detect bit SSPSTAT0 between each transmission 2008 Microchip Technology Inc DS39631Epage 165 PIC18F2420252044204520 1733 ENABLING SPI IO To enable the serial port MSSP Enable bit SSPEN SSPCON15 must be set To reset or reconfigure SPI mode clear the SSPEN bit reinitialize the SSPCON registers and then set the SSPEN bit This configures the SDI SDO SCK and SS pins as serial port pins For the pins to behave as the serial port func tion some must have their data direction bits in the TRIS register appropriately programmed as follows SDI is automatically controlled by the SPI module SDO must have TRISC5 bit cleared SCK Master mode must have TRISC3 bit cleared SCK Slave mode must have TRISC3 bit set SS must have TRISA5 bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction TRIS register to the opposite value 1734 TYPICAL CONNECTION Figure 172 shows a typical connection between two microcontrollers The master controller Processor 1 initiates the data transfer by sending the SCK signal Data is shifted out of both shift registers on their pro grammed clock edge and latched on the opposite edge of the clock Both processors should be programmed to the same Clock Polarity CKP then both controllers would send and receive data at the same time Whether the data is meaningful or dummy data depends on the application software This leads to three scenarios for data transmission Master sends data Slave sends dummy data Master sends data Slave sends data Master sends dummy data Slave sends data FIGURE 172 SPI MASTERSLAVE CONNECTION Serial Input Buffer SSPBUF Shift Register SSPSR MSb LSb SDO SDI PROCESSOR 1 SCK SPI Master SSPM30 00xxb Serial Input Buffer SSPBUF Shift Register SSPSR LSb MSb SDI SDO PROCESSOR 2 SCK SPI Slave SSPM30 010xb Serial Clock PIC18F2420252044204520 DS39631Epage 166 2008 Microchip Technology Inc 1735 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK The master determines when the slave Processor 2 Figure 172 is to broadcast data by the software protocol In Master mode the data is transmittedreceived as soon as the SSPBUF register is written to If the SPI is only going to receive the SDO output could be dis abled programmed as an input The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate As each byte is received it will be loaded into the SSPBUF register as if a normal received byte interrupts and status bits appropriately set This could be useful in receiver applications as a Line Activity Monitor mode The clock polarity is selected by appropriately programming the CKP bit SSPCON14 This then would give waveforms for SPI communication as shown in Figure 173 Figure 175 and Figure 176 where the MSB is transmitted first In Master mode the SPI clock rate bit rate is userprogrammable to be one of the following FOSC4 or TCY FOSC16 or 4 TCY FOSC64 or 16 TCY Timer2 output2 This allows a maximum data rate at 40 MHz of 1000 Mbps Figure 173 shows the waveforms for Master mode When the CKE bit is set the SDO data is valid before there is a clock edge on SCK The change of the input sample is shown based on the state of the SMP bit The time when the SSPBUF is loaded with the received data is shown FIGURE 173 SPI MODE WAVEFORM MASTER MODE SCK CKP 0 SCK CKP 1 SCK CKP 0 SCK CKP 1 4 Clock Modes Input Sample Input Sample SDI bit 7 bit 0 SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 SDI SSPIF SMP 1 SMP 0 SMP 1 CKE 1 CKE 0 CKE 1 CKE 0 SMP 0 Write to SSPBUF SSPSR to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CKE 0 CKE 1 Next Q4 Cycle after Q2 bit 0 2008 Microchip Technology Inc DS39631Epage 167 PIC18F2420252044204520 1736 SLAVE MODE In Slave mode the data is transmitted and received as the external clock pulses appear on SCK When the last bit is latched the SSPIF interrupt flag bit is set Before enabling the module in SPI Slave mode the clock line must match the proper Idle state The clock line can be observed by reading the SCK pin The Idle state is determined by the CKP bit SSPCON14 While in Slave mode the external clock is supplied by the external clock source on the SCK pin This external clock must meet the minimum high and low times as specified in the electrical specifications While in Sleep mode the slave can transmitreceive data When a byte is received the device will wakeup from Sleep 1737 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode The SPI must be in Slave mode with SS pin control enabled SSPCON130 04h The pin must not be driven low for the SS pin to function as an input The data latch must be high When the SS pin is low transmission and reception are enabled and the SDO pin is driven When the SS pin goes high the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output External pulluppulldown resistors may be desirable depending on the application When the SPI module resets the bit counter is forced to 0 This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit To emulate twowire communication the SDO pin can be connected to the SDI pin When the SPI needs to operate as a receiver the SDO pin can be configured as an input This disables transmissions from the SDO The SDI can always be left as an input SDI function since it cannot create a bus conflict FIGURE 174 SLAVE SYNCHRONIZATION WAVEFORM Note 1 When the SPI is in Slave mode with SS pin control enabled SSPCON30 0100 the SPI module will reset if the SS pin is set to VDD 2 If the SPI is used in Slave mode with CKE set then the SS pin control must be enabled SCK CKP 1 SCK CKP 0 Input Sample SDI bit 7 SDO bit 7 bit 6 bit 7 SSPIF Interrupt SMP 0 CKE 0 CKE 0 SMP 0 Write to SSPBUF SSPSR to SSPBUF SS Flag bit 0 bit 7 bit 0 Next Q4 Cycle after Q2 PIC18F2420252044204520 DS39631Epage 168 2008 Microchip Technology Inc FIGURE 175 SPI MODE WAVEFORM SLAVE MODE WITH CKE 0 FIGURE 176 SPI MODE WAVEFORM SLAVE MODE WITH CKE 1 SCK CKP 1 SCK CKP 0 Input Sample SDI bit 7 SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPIF Interrupt SMP 0 CKE 0 CKE 0 SMP 0 Write to SSPBUF SSPSR to SSPBUF SS Flag Optional Next Q4 Cycle after Q2 bit 0 SCK CKP 1 SCK CKP 0 Input Sample SDI bit 7 bit 0 SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPIF Interrupt SMP 0 CKE 1 CKE 1 SMP 0 Write to SSPBUF SSPSR to SSPBUF SS Flag Not Optional Next Q4 Cycle after Q2 2008 Microchip Technology Inc DS39631Epage 169 PIC18F2420252044204520 1738 OPERATION IN POWERMANAGED MODES In SPI Master mode module clocks may be operating at a different speed than when in fullpower mode in the case of Sleep mode all clocks are halted In most Idle modes a clock is provided to the peripher als That clock should be from the primary clock source the secondary clock Timer1 oscillator at 32768 kHz or the INTOSC source See Section 27 Clock Sources and Oscillator Switching for additional information In most cases the speed that the master clocks SPI data is not important however this should be evaluated for each system If MSSP interrupts are enabled they can wake the con troller from Sleep mode or one of the Idle modes when the master completes sending data If an exit from Sleep or Idle mode is not desired MSSP interrupts should be disabled If the Sleep mode is selected all module clocks are halted and the transmissionreception will remain in that state until the devices wakes After the device returns to Run mode the module will resume transmitting and receiving data In SPI Slave mode the SPI TransmitReceive Shift register operates asynchronously to the device This allows the device to be placed in any powermanaged mode and data to be shifted into the SPI Transmit Receive Shift register When all 8 bits have been received the MSSP interrupt flag bit will be set and if enabled will wake the device 1739 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer 17310 BUS MODE COMPATIBILITY Table 171 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits TABLE 171 SPI BUS MODES There is also an SMP bit which controls when the data is sampled TABLE 172 REGISTERS ASSOCIATED WITH SPI OPERATION Standard SPI Mode Terminology Control Bits State CKP CKE 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TRISA TRISA72 TRISA62 PORTA Data Direction Register 52 TRISC PORTC Data Direction Register 52 SSPBUF MSSP Receive BufferTransmit Register 50 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50 SSPSTAT SMP CKE DA P S RW UA BF 50 Legend Shaded cells are not used by the MSSP in SPI mode Note 1 These bits are unimplemented in 28pin devices always maintain these bits clear 2 PORTA76 and their direction bits are individually configured as port pins based on various primary oscillator modes When disabled these bits read as 0 PIC18F2420252044204520 DS39631Epage 170 2008 Microchip Technology Inc 174 I2C Mode The MSSP module in I2C mode fully implements all master and slave functions including general call support and provides interrupts on Start and Stop bits in hardware to determine a free bus multimaster function The MSSP module implements the standard mode specifications as well as 7Bit and 10Bit Addressing modes Two pins are used for data transfer Serial clock SCL RC3SCKSCL Serial data SDA RC4SDISDA The user must configure these pins as inputs or outputs through the TRISC43 bits FIGURE 177 MSSP BLOCK DIAGRAM I2C MODE 1741 REGISTERS The MSSP module has six registers for I2C operation These are MSSP Control Register 1 SSPCON1 MSSP Control Register 2 SSPCON2 MSSP Status Register SSPSTAT Serial ReceiveTransmit Buffer Register SSPBUF MSSP Shift Register SSPSR Not directly accessible MSSP Address Register SSPADD SSPCON1 SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation The SSPCON1 and SSPCON2 registers are readable and writable The lower 6 bits of the SSPSTAT are readonly The upper two bits of the SSPSTAT are readwrite SSPSR is the shift register used for shifting data in or out SSPBUF is the buffer register to which data bytes are written to or read from SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode When the MSSP is configured in Master mode the lower seven bits of SSPADD act as the Baud Rate Generator reload value In receive operations SSPSR and SSPBUF together create a doublebuffered receiver When SSPSR receives a complete byte it is transferred to SSPBUF and the SSPIF interrupt is set During transmission the SSPBUF is not double buffered A write to SSPBUF will write to both SSPBUF and SSPSR Read Write SSPSR reg Match Detect SSPADD reg Start and Stop bit Detect SSPBUF reg Internal Data Bus Addr Match Set Reset S P bits SSPSTAT reg RC3SCKSCL RC4SDI Shift Clock MSb SDA LSb 2008 Microchip Technology Inc DS39631Epage 171 PIC18F2420252044204520 REGISTER 173 SSPSTAT MSSP STATUS REGISTER I2C MODE RW0 RW0 R0 R0 R0 R0 R0 R0 SMP CKE DA P1 S1 RW23 UA BF bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 SMP Slew Rate Control bit In Master or Slave mode 1 Slew rate control disabled for Standard Speed mode 100 kHz and 1 MHz 0 Slew rate control enabled for HighSpeed mode 400 kHz bit 6 CKE SMBus Select bit In Master or Slave mode 1 Enable SMBus specific inputs 0 Disable SMBus specific inputs bit 5 DA DataAddress bit In Master mode Reserved In Slave mode 1 Indicates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was address bit 4 P Stop bit1 1 Indicates that a Stop bit has been detected last 0 Stop bit was not detected last bit 3 S Start bit1 1 Indicates that a Start bit has been detected last 0 Start bit was not detected last bit 2 RW ReadWrite Information bit I2C mode only23 In Slave mode 1 Read 0 Write In Master mode 1 Transmit is in progress 0 Transmit is not in progress bit 1 UA Update Address bit 10Bit Slave mode only 1 Indicates that the user needs to update the address in the SSPADD register 0 Address does not need to be updated bit 0 BF Buffer Full Status bit In Transmit mode 1 SSPBUF is full 0 SSPBUF is empty In Receive mode 1 SSPBUF is full does not include the ACK and Stop bits 0 SSPBUF is empty does not include the ACK and Stop bits Note 1 This bit is cleared on Reset and when SSPEN is cleared 2 This bit holds the RW bit information following the last address match This bit is only valid from the address match to the next Start bit Stop bit or not ACK bit 3 ORing this bit with SEN RSEN PEN RCEN or ACKEN will indicate if the MSSP is in Active mode PIC18F2420252044204520 DS39631Epage 172 2008 Microchip Technology Inc REGISTER 174 SSPCON1 MSSP CONTROL REGISTER 1 I2C MODE RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 WCOL SSPOV SSPEN1 CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 WCOL Write Collision Detect bit In Master Transmit mode 1 A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started must be cleared in software 0 No collision In Slave Transmit mode 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision In Receive mode Master or Slave modes This is a dont care bit bit 6 SSPOV Receive Overflow Indicator bit In Receive mode 1 A byte is received while the SSPBUF register is still holding the previous byte must be cleared in software 0 No overflow In Transmit mode This is a dont care bit in Transmit mode bit 5 SSPEN Master Synchronous Serial Port Enable bit1 1 Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 Disables serial port and configures these pins as IO port pins bit 4 CKP SCK Release Control bit In Slave mode 1 Releases clock 0 Holds clock low clock stretch used to ensure data setup time In Master mode Unused in this mode bit 30 SSPM30 Master Synchronous Serial Port Mode Select bits2 1111 I2C Slave mode 10bit address with Start and Stop bit interrupts enabled 1110 I2C Slave mode 7bit address with Start and Stop bit interrupts enabled 1011 I2C Firmware Controlled Master mode Slave Idle 1000 I2C Master mode clock FOSC4 SSPADD 1 0111 I2C Slave mode 10bit address 0110 I2C Slave mode 7bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only Note 1 When enabled the SDA and SCL pins must be properly configured as inputs or outputs 2008 Microchip Technology Inc DS39631Epage 173 PIC18F2420252044204520 REGISTER 175 SSPCON2 MSSP CONTROL REGISTER 2 I2C MODE RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 GCEN ACKSTAT ACKDT2 ACKEN1 RCEN1 PEN1 RSEN1 SEN1 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 GCEN General Call Enable bit Slave mode only 1 Enables interrupt when a general call address 0000h is received in the SSPSR 0 General call address disabled bit 6 ACKSTAT Acknowledge Status bit Master Transmit mode only 1 Acknowledge was not received from slave 0 Acknowledge was received from slave bit 5 ACKDT Acknowledge Data bit Master Receive mode only2 1 Not Acknowledge 0 Acknowledge bit 4 ACKEN Acknowledge Sequence Enable bit Master Receive mode only1 1 Initiates Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit Automatically cleared by hardware 0 Acknowledge sequence Idle bit 3 RCEN Receive Enable bit Master mode only1 1 Enables Receive mode for I2C 0 Receive Idle bit 2 PEN Stop Condition Enable bit Master mode only1 1 Initiates Stop condition on SDA and SCL pins Automatically cleared by hardware 0 Stop condition Idle bit 1 RSEN Repeated Start Condition Enable bit Master mode only1 1 Initiates Repeated Start condition on SDA and SCL pins Automatically cleared by hardware 0 Repeated Start condition Idle bit 0 SEN Start Condition EnableStretch Enable bit1 In Master mode 1 Initiates Start condition on SDA and SCL pins Automatically cleared by hardware 0 Start condition Idle In Slave mode 1 Clock stretching is enabled for both slave transmit and slave receive stretch enabled 0 Clock stretching is disabled Note 1 For bits ACKEN RCEN PEN RSEN SEN If the I2C module is not in the Idle mode these bits may not be set no spooling and the SSPBUF may not be written or writes to the SSPBUF are disabled 2 Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive PIC18F2420252044204520 DS39631Epage 174 2008 Microchip Technology Inc 1742 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit SSPEN SSPCON15 The SSPCON1 register allows control of the I2C operation Four mode selection bits SSPCON130 allow one of the following I2C modes to be selected I2C Master mode clock FOSC4 x SSPADD 1 I2C Slave mode 7bit addressing I2C Slave mode 10bit addressing I2C Slave mode 7bit addressing with Start and Stop bit interrupts enabled I2C Slave mode 10bit addressing with Start and Stop bit interrupts enabled I2C Firmware Controlled Master mode slave is Idle Selection of any I2C mode with the SSPEN bit set forces the SCL and SDA pins to be opendrain provided these pins are programmed to inputs by setting the appropriate TRISC bits To ensure proper operation of the module pullup resistors must be provided externally to the SCL and SDA pins 1743 SLAVE MODE In Slave mode the SCL and SDA pins must be config ured as inputs TRISC43 set The MSSP module will override the input state with the output data when required slavetransmitter The I2C Slave mode hardware will always generate an interrupt on an address match Through the mode select bits the user can also choose to interrupt on Start and Stop bits When an address is matched or the data transfer after an address match is received the hardware automati cally will generate the Acknowledge ACK pulse and load the SSPBUF register with the received value currently in the SSPSR register Any combination of the following conditions will cause the MSSP module not to give this ACK pulse The Buffer Full bit BF SSPSTAT0 was set before the transfer was received The overflow bit SSPOV SSPCON26 was set before the transfer was received In this case the SSPSR register value is not loaded into the SSPBUF but bit SSPIF PIR13 is set The BF bit is cleared by reading the SSPBUF register while bit SSPOV is cleared through software The SCL clock input must have a minimum high and low for proper operation The high and low times of the I2C specification as well as the requirement of the MSSP module are shown in timing parameter 100 and parameter 101 17431 Addressing Once the MSSP module has been enabled it waits for a Start condition to occur Following the Start condition the 8 bits are shifted into the SSPSR register All incoming bits are sampled with the rising edge of the clock SCL line The value of register SSPSR71 is compared to the value of the SSPADD register The address is compared on the falling edge of the eighth clock SCL pulse If the addresses match and the BF and SSPOV bits are clear the following events occur 1 The SSPSR register value is loaded into the SSPBUF register 2 The Buffer Full bit BF is set 3 An ACK pulse is generated 4 MSSP Interrupt Flag bit SSPIF PIR13 is set interrupt is generated if enabled on the falling edge of the ninth SCL pulse In 10Bit Addressing mode two address bytes need to be received by the slave The five Most Significant bits MSbs of the first address byte specify if this is a 10bit address Bit RW SSPSTAT2 must specify a write so the slave device will receive the second address byte For a 10bit address the first byte would equal 11110 A9 A8 0 where A9 and A8 are the two MSbs of the address The sequence of events for 10Bit Addressing mode is as follows with steps 7 through 9 for the slavetransmitter 1 Receive first high byte of address bits SSPIF BF and UA SSPSTAT1 are set 2 Update the SSPADD register with second low byte of address clears UA bit and releases the SCL line 3 Read the SSPBUF register clears BF bit and clear flag bit SSPIF 4 Receive second low byte of address bits SSPIF BF and UA are set 5 Update the SSPADD register with the first high byte of address If match releases SCL line this will clear bit UA 6 Read the SSPBUF register clears BF bit and clear flag bit SSPIF 7 Receive Repeated Start condition 8 Receive first high byte of address bits SSPIF and BF are set 9 Read the SSPBUF register clears BF bit and clear flag bit SSPIF 2008 Microchip Technology Inc DS39631Epage 175 PIC18F2420252044204520 17432 Reception When the RW bit of the address byte is clear and an address match occurs the RW bit of the SSPSTAT register is cleared The received address is loaded into the SSPBUF register and the SDA line is held low ACK When the address byte overflow condition exists then the no Acknowledge ACK pulse is given An overflow condition is defined as either bit BF SSPSTAT0 is set or bit SSPOV SSPCON16 is set An MSSP interrupt is generated for each data transfer byte Flag bit SSPIF PIR13 must be cleared in software The SSPSTAT register is used to determine the status of the byte If SEN is enabled SSPCON20 1 RC3SCKSCL will be held low clock stretch following each data transfer The clock must be released by setting bit CKP SSPCON4 See Section 1744 Clock Stretching for more details 17433 Transmission When the RW bit of the incoming address byte is set and an address match occurs the RW bit of the SSPSTAT register is set The received address is loaded into the SSPBUF register The ACK pulse will be sent on the ninth bit and the RC3SCKSCL pin is held low regardless of SEN see Section 1744 Clock Stretching for more detail By stretching the clock the master will be unable to assert another clock pulse until the slave is done preparing the transmit data The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register Then the RC3SCKSCL pin should be enabled by set ting bit CKP SSPCON14 The eight data bits are shifted out on the falling edge of the SCL input This ensures that the SDA signal is valid during the SCL high time Figure 179 The ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse If the SDA line is high not ACK then the data transfer is com plete In this case when the ACK is latched by the slave the slave logic is reset resets SSPSTAT regis ter and the slave monitors for another occurrence of the Start bit If the SDA line was low ACK the next transmit data must be loaded into the SSPBUF register Again the RC3SCKSCL pin must be enabled by setting bit CKP An MSSP interrupt is generated for each data transfer byte The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte The SSPIF bit is set on the falling edge of the ninth clock pulse PIC18F2420252044204520 DS39631Epage 176 2008 Microchip Technology Inc FIGURE 178 I2C SLAVE MODE TIMING WITH SEN 0 RECEPTION 7BIT ADDRESSING SDA SCL SSPIF BF SSPSTAT0 SSPOV SSPCON16 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0 ACK Receiving Data ACK Receiving Data RW 0 ACK Receiving Address Cleared in software SSPBUF is read Bus master terminates transfer SSPOV is set because SSPBUF is still full ACK is not sent D2 6 PIR13 CKP SSPCON14 CKP does not reset to 0 when SEN 0 2008 Microchip Technology Inc DS39631Epage 177 PIC18F2420252044204520 FIGURE 179 I2C SLAVE MODE TIMING TRANSMISSION 7BIT ADDRESSING SDA SCL SSPIF PIR13 BF SSPSTAT0 A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 SSPBUF is written in software Cleared in software Data in sampled S ACK Transmitting Data RW 1 ACK Receiving Address A7 D7 9 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPBUF is written in software Cleared in software From SSPIF ISR Transmitting Data D7 1 CKP P ACK CKP is set in software CKP is set in software SCL held low while CPU responds to SSPIF Clear by reading From SSPIF ISR PIC18F2420252044204520 DS39631Epage 178 2008 Microchip Technology Inc FIGURE 1710 I2C SLAVE MODE TIMING WITH SEN 0 RECEPTION 10BIT ADDRESSING SDA SCL SSPIF BF SSPSTAT0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte ACK RW 0 ACK Receive First Byte of Address Cleared in software D2 6 PIR13 Cleared in software Receive Second Byte of Address Cleared by hardware when SSPADD is updated with low byte of address UA SSPSTAT1 Clock is held low until update of SSPADD has taken place UA is set indicating that the SSPADD needs to be updated UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag ACK CKP SSPCON14 1 2 3 4 5 7 8 9 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte Bus master terminates transfer D2 6 ACK Cleared in software Cleared in software SSPOV SSPCON16 SSPOV is set because SSPBUF is still full ACK is not sent CKP does not reset to 0 when SEN 0 Clock is held low until update of SSPADD has taken place 2008 Microchip Technology Inc DS39631Epage 179 PIC18F2420252044204520 FIGURE 1711 I2C SLAVE MODE TIMING TRANSMISSION 10BIT ADDRESSING SDA SCL SSPIF BF SSPSTAT0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 A8 RW1 ACK ACK RW 0 ACK Receive First Byte of Address Cleared in software Bus master terminates transfer A9 6 PIR13 Receive Second Byte of Address Cleared by hardware when SSPADD is updated with low byte of address UA SSPSTAT1 Clock is held low until update of SSPADD has taken place UA is set indicating that the SSPADD needs to be updated UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag Receive First Byte of Address 1 2 3 4 5 7 8 9 D7 D6 D5 D4 D3 D1 ACK D2 6 Transmitting Data Byte D0 Dummy read of SSPBUF to clear BF flag Sr Cleared in software Write of SSPBUF initiates transmit Cleared in software Completion of clears BF flag CKP SSPCON14 CKP is set in software CKP is automatically cleared in hardware holding SCL low Clock is held low until update of SSPADD has taken place data transmission Clock is held low until CKP is set to 1 third address sequence BF flag is clear at the end of the PIC18F2420252044204520 DS39631Epage 180 2008 Microchip Technology Inc 1744 CLOCK STRETCHING Both 7Bit and 10Bit Slave modes implement automatic clock stretching during a transmit sequence The SEN bit SSPCON20 allows clock stretching to be enabled during receives Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence 17441 Clock Stretching for 7Bit Slave Receive Mode SEN 1 In 7Bit Slave Receive mode on the falling edge of the ninth clock at the end of the ACK sequence if the BF bit is set the CKP bit in the SSPCON1 register is automatically cleared forcing the SCL output to be held low The CKP being cleared to 0 will assert the SCL line low The CKP bit must be set in the users Interrupt Service Routine ISR before reception is allowed to continue By holding the SCL line low the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence This will prevent buffer overruns from occurring see Figure 1713 17442 Clock Stretching for 10Bit Slave Receive Mode SEN 1 In 10Bit Slave Receive mode during the address sequence clock stretching automatically takes place but CKP is not cleared During this time if the UA bit is set after the ninth clock clock stretching is initiated The UA bit is set after receiving the upper byte of the 10bit address and following the receive of the second byte of the 10bit address with the RW bit cleared to 0 The release of the clock line occurs upon updating SSPADD Clock stretching will occur on each data receive sequence as described in 7bit mode 17443 Clock Stretching for 7Bit Slave Transmit Mode 7Bit Slave Transmit mode implements clock stretch ing by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear This occurs regardless of the state of the SEN bit The users ISR must set the CKP bit before transmis sion is allowed to continue By holding the SCL line low the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence see Figure 179 17444 Clock Stretching for 10Bit Slave Transmit Mode In 10Bit Slave Transmit mode clock stretching is con trolled during the first two address sequences by the state of the UA bit just as it is in 10Bit Slave Receive mode The first two addresses are followed by a third address sequence which contains the highorder bits of the 10bit address and the RW bit set to 1 After the third address sequence is performed the UA bit is not set the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7Bit Slave Transmit mode see Figure 1711 Note 1 If the user reads the contents of the SSPBUF before the falling edge of the ninth clock thus clearing the BF bit the CKP bit will not be cleared and clock stretching will not occur 2 The CKP bit can be set in software regard less of the state of the BF bit The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition Note If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasnt cleared the BF bit by read ing the SSPBUF register before that time then the CKP bit will still NOT be asserted low Clock stretching on the basis of the state of the BF bit only occurs during a data sequence not an address sequence Note 1 If the user loads the contents of SSPBUF setting the BF bit before the falling edge of the ninth clock the CKP bit will not be cleared and clock stretching will not occur 2 The CKP bit can be set in software regardless of the state of the BF bit 2008 Microchip Technology Inc DS39631Epage 181 PIC18F2420252044204520 17445 Clock Synchronization and the CKP bit When the CKP bit is cleared the SCL output is forced to 0 However clearing the CKP bit will not assert the SCL output low until the SCL output is already sam pled low Therefore the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL see Figure 1712 FIGURE 1712 CLOCK SYNCHRONIZATION TIMING SDA SCL DX 1 DX WR Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SSPCONx CKP Master device deasserts clock Master device asserts clock PIC18F2420252044204520 DS39631Epage 182 2008 Microchip Technology Inc FIGURE 1713 I2C SLAVE MODE TIMING WITH SEN 1 RECEPTION 7BIT ADDRESSING SDA SCL SSPIF BF SSPSTAT0 SSPOV SSPCON16 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0 ACK Receiving Data ACK Receiving Data RW 0 ACK Receiving Address Cleared in software SSPBUF is read Bus master terminates transfer SSPOV is set because SSPBUF is still full ACK is not sent D2 6 PIR13 CKP SSPCON14 CKP written to 1 in If BF is cleared prior to the falling edge of the 9th clock CKP will not be reset to 0 and no clock stretching will occur software Clock is held low until CKP is set to 1 Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is not held low because ACK 1 BF is set after falling edge of the 9th clock CKP is reset to 0 and clock stretching occurs 2008 Microchip Technology Inc DS39631Epage 183 PIC18F2420252044204520 FIGURE 1714 I2C SLAVE MODE TIMING WITH SEN 1 RECEPTION 10BIT ADDRESSING SDA SCL SSPIF BF SSPSTAT0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte ACK RW 0 ACK Receive First Byte of Address Cleared in software D2 6 PIR13 Cleared in software Receive Second Byte of Address Cleared by hardware when SSPADD is updated with low byte of address after falling edge UA SSPSTAT1 Clock is held low until update of SSPADD has taken place UA is set indicating that the SSPADD needs to be updated UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address after falling edge SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag ACK CKP SSPCON14 1 2 3 4 5 7 8 9 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte Bus master terminates transfer D2 6 ACK Cleared in software Cleared in software SSPOV SSPCON16 CKP written to 1 Note An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set Note An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set in software Clock is held low until update of SSPADD has taken place of ninth clock of ninth clock SSPOV is set because SSPBUF is still full ACK is not sent Dummy read of SSPBUF to clear BF flag Clock is held low until CKP is set to 1 Clock is not held low because ACK 1 PIC18F2420252044204520 DS39631Epage 184 2008 Microchip Technology Inc 1745 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master The exception is the general call address which can address all devices When this address is used all devices should in theory respond with an Acknowledge The general call address is one of eight addresses reserved for specific purposes by the I2C protocol It consists of all 0s with RW 0 The general call address is recognized when the Gen eral Call Enable bit GCEN is enabled SSPCON27 is set Following a Start bit detect 8 bits are shifted into the SSPSR and the address is compared against the SSPADD It is also compared to the general call address and fixed in hardware If the general call address matches the SSPSR is transferred to the SSPBUF the BF flag bit is set eighth bit and on the falling edge of the ninth bit ACK bit the SSPIF interrupt flag bit is set When the interrupt is serviced the source for the interrupt can be checked by reading the contents of the SSPBUF The value can be used to determine if the address was device specific or a general call address In 10bit mode the SSPADD is required to be updated for the second half of the address to match and the UA bit is set SSPSTAT1 If the general call address is sampled when the GCEN bit is set while the slave is configured in 10Bit Addressing mode then the second half of the address is not necessary the UA bit will not be set and the slave will begin receiving data after the Acknowledge Figure 1715 FIGURE 1715 SLAVE MODE GENERAL CALL ADDRESS SEQUENCE 7 OR 10BIT ADDRESSING MODE SDA SCL S SSPIF BF SSPSTAT0 SSPOV SSPCON16 Cleared in software SSPBUF is read RW 0 ACK General Call Address Address is compared to General Call Address GCEN SSPCON27 Receiving Data ACK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 after ACK set interrupt 0 1 2008 Microchip Technology Inc DS39631Epage 185 PIC18F2420252044204520 1746 MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit In Master mode the SCL and SDA lines are manipulated by the MSSP hardware Master mode of operation is supported by interrupt generation on the detection of the Start and Stop con ditions The Stop P and Start S bits are cleared from a Reset or when the MSSP module is disabled Control of the I2C bus may be taken when the P bit is set or the bus is Idle with both the S and P bits clear In Firmware Controlled Master mode user code conducts all I2C bus operations based on Start and Stop bit conditions Once Master mode is enabled the user has six options 1 Assert a Start condition on SDA and SCL 2 Assert a Repeated Start condition on SDA and SCL 3 Write to the SSPBUF register initiating transmission of dataaddress 4 Configure the I2C port to receive data 5 Generate an Acknowledge condition at the end of a received byte of data 6 Generate a Stop condition on SDA and SCL The following events will cause the MSSP Interrupt Flag bit SSPIF to be set MSSP interrupt if enabled Start condition Stop condition Data transfer byte transmittedreceived Acknowledge transmit Repeated Start FIGURE 1716 MSSP BLOCK DIAGRAM I2C MASTER MODE Note The MSSP module when configured in I2C Master mode does not allow queueing of events For instance the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condi tion is complete In this case the SSPBUF will not be written to and the WCOL bit will be set indicating that a write to the SSPBUF did not occur Read Write SSPSR Start bit Stop bit SSPBUF Internal Data Bus SetReset S P WCOL SSPSTAT Shift Clock MSb LSb SDA Acknowledge Generate Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMITRCV SCL SCL In Bus Collision SDA In Receive Enable Clock Cntl Clock ArbitrateWCOL Detect hold off clock source SSPADD60 Baud Set SSPIF BCLIF Reset ACKSTAT PEN SSPCON2 Rate Generator SSPM30 Start bit Detect PIC18F2420252044204520 DS39631Epage 186 2008 Microchip Technology Inc 17461 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions A transfer is ended with a Stop condition or with a Repeated Start condition Since the Repeated Start condition is also the beginning of the next serial transfer the I2C bus will not be released In Master Transmitter mode serial data is output through SDA while SCL outputs the serial clock The first byte transmitted contains the slave address of the receiving device 7 bits and the ReadWrite RW bit In this case the RW bit will be logic 0 Serial data is transmitted 8 bits at a time After each byte is transmit ted an Acknowledge bit is received Start and Stop conditions are output to indicate the beginning and the end of a serial transfer In Master Receive mode the first byte transmitted con tains the slave address of the transmitting device 7 bits and the RW bit In this case the RW bit will be logic 1 Thus the first byte transmitted is a 7bit slave address followed by a 1 to indicate the receive bit Serial data is received via SDA while SCL outputs the serial clock Serial data is received 8 bits at a time After each byte is received an Acknowledge bit is transmit ted Start and Stop conditions indicate the beginning and end of transmission The Baud Rate Generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz 400 kHz or 1 MHz I2C operation See Section 1747 Baud Rate for more detail A typical transmit sequence would go as follows 1 The user generates a Start condition by setting the Start Enable bit SEN SSPCON20 2 SSPIF is set The MSSP module will wait the required start time before any other operation takes place 3 The user loads the SSPBUF with the slave address to transmit 4 Address is shifted out the SDA pin until all 8 bits are transmitted 5 The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register SSPCON26 6 The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit 7 The user loads the SSPBUF with eight bits of data 8 Data is shifted out the SDA pin until all 8 bits are transmitted 9 The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register SSPCON26 10 The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit 11 The user generates a Stop condition by setting the Stop Enable bit PEN SSPCON22 12 Interrupt is generated once the Stop condition is complete 2008 Microchip Technology Inc DS39631Epage 187 PIC18F2420252044204520 1747 BAUD RATE In I2C Master mode the Baud Rate Generator BRG reload value is placed in the lower 7 bits of the SSPADD register Figure 1717 When a write occurs to SSPBUF the Baud Rate Generator will automatically begin counting The BRG counts down to 0 and stops until another reload has taken place The BRG count is decremented twice per instruction cycle TCY on the Q2 and Q4 clocks In I2C Master mode the BRG is reloaded automatically Once the given operation is complete ie transmis sion of the last data bit is followed by ACK the internal clock will automatically stop counting and the SCL pin will remain in its last state Table 173 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD FIGURE 1717 BAUD RATE GENERATOR BLOCK DIAGRAM TABLE 173 I2C CLOCK RATE WBRG SSPM30 BRG Down Counter CLKO FOSC4 SSPADD60 SSPM30 SCL Reload Control Reload FCY FCY 2 BRG Value FSCL 2 Rollovers of BRG 10 MHz 20 MHz 18h 400 kHz1 10 MHz 20 MHz 1Fh 3125 kHz 10 MHz 20 MHz 63h 100 kHz 4 MHz 8 MHz 09h 400 kHz1 4 MHz 8 MHz 0Ch 308 kHz 4 MHz 8 MHz 27h 100 kHz 1 MHz 2 MHz 02h 333 kHz1 1 MHz 2 MHz 09h 100 kHz 1 MHz 2 MHz 00h 1 MHz1 Note 1 The I2C interface does not conform to the 400 kHz I2C specification which applies to rates greater than 100 kHz in all details but may be used with care where higher rates are required by the application PIC18F2420252044204520 DS39631Epage 188 2008 Microchip Technology Inc 17471 Clock Arbitration Clock arbitration occurs when the master during any receive transmit or Repeated StartStop condition deasserts the SCL pin SCL allowed to float high When the SCL pin is allowed to float high the Baud Rate Generator BRG is suspended from counting until the SCL pin is actually sampled high When the SCL pin is sampled high the Baud Rate Generator is reloaded with the contents of SSPADD60 and begins counting This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device Figure 1718 FIGURE 1718 BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA SCL SCL deasserted but slave holds DX 1 DX BRG SCL is sampled high reload takes place and BRG starts its count 03h 02h 01h 00h hold off 03h 02h Reload BRG Value SCL low clock arbitration SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 2008 Microchip Technology Inc DS39631Epage 189 PIC18F2420252044204520 1748 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition the user sets the Start Enable bit SEN SSPCON20 If the SDA and SCL pins are sampled high the Baud Rate Generator is reloaded with the contents of SSPADD60 and starts its count If SCL and SDA are both sampled high when the Baud Rate Generator times out TBRG the SDA pin is driven low The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit SSPSTAT3 to be set Following this the Baud Rate Generator is reloaded with the contents of SSPADD60 and resumes its count When the Baud Rate Generator times out TBRG the SEN bit SSPCON20 will be automatically cleared by hardware the Baud Rate Generator is suspended leaving the SDA line held low and the Start condition is complete 17481 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress the WCOL is set and the contents of the buffer are unchanged the write doesnt occur FIGURE 1719 FIRST START BIT TIMING Note If at the beginning of the Start condition the SDA and SCL pins are already sam pled low or if during the Start condition the SCL line is sampled low before the SDA line is driven low a bus collision occurs the Bus Collision Interrupt Flag BCLIF is set the Start condition is aborted and the I2C module is reset into its Idle state Note Because queueing of events is not allowed writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete SDA SCL S TBRG 1st bit 2nd bit TBRG SDA 1 At completion of Start bit SCL 1 Write to SSPBUF occurs here TBRG hardware clears SEN bit TBRG Write to SEN bit occurs here Set S bit SSPSTAT3 and sets SSPIF bit PIC18F2420252044204520 DS39631Epage 190 2008 Microchip Technology Inc 1749 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit SSPCON21 is programmed high and the I2C logic module is in the Idle state When the RSEN bit is set the SCL pin is asserted low When the SCL pin is sam pled low the Baud Rate Generator is loaded with the contents of SSPADD50 and begins counting The SDA pin is released brought high for one Baud Rate Generator count TBRG When the Baud Rate Genera tor times out if SDA is sampled high the SCL pin will be deasserted brought high When SCL is sampled high the Baud Rate Generator is reloaded with the contents of SSPADD60 and begins counting SDA and SCL must be sampled high for one TBRG This action is then followed by assertion of the SDA pin SDA 0 for one TBRG while SCL is high Following this the RSEN bit SSPCON21 will be automatically cleared and the Baud Rate Generator will not be reloaded leaving the SDA pin held low As soon as a Start condition is detected on the SDA and SCL pins the S bit SSPSTAT3 will be set The SSPIF bit will not be set until the Baud Rate Generator has timed out Immediately following the SSPIF bit getting set the user may write the SSPBUF with the 7bit address in 7bit mode or the default first address in 10bit mode After the first eight bits are transmitted and an ACK is received the user may then transmit an additional eight bits of address 10bit mode or eight bits of data 7bit mode 17491 WCOL Status Flag If the user writes the SSPBUF when a Repeated Start sequence is in progress the WCOL is set and the contents of the buffer are unchanged the write doesnt occur FIGURE 1720 REPEATED START CONDITION WAVEFORM Note 1 If RSEN is programmed while any other event is in progress it will not take effect 2 A bus collision during the Repeated Start condition occurs if SDA is sampled low when SCL goes from lowtohigh SCL goes low before SDA is asserted low This may indicate that another master is attempting to transmit a data 1 Note Because queueing of events is not allowed writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete SDA SCL Sr Repeated Start Write to SSPCON2 Write to SSPBUF occurs here on falling edge of ninth clock end of Xmit At completion of Start bit hardware clears RSEN bit 1st bit S bit set by hardware TBRG TBRG SDA 1 SDA 1 SCL no change SCL 1 occurs here TBRG TBRG TBRG and sets SSPIF RSEN bit set by hardware 2008 Microchip Technology Inc DS39631Epage 191 PIC18F2420252044204520 17410 I2C MASTER MODE TRANSMISSION Transmission of a data byte a 7bit address or the other half of a 10bit address is accomplished by simply writing a value to the SSPBUF register This action will set the Buffer Full flag bit BF and allow the Baud Rate Generator to begin counting and start the next trans mission Each bit of addressdata will be shifted out onto the SDA pin after the falling edge of SCL is asserted see data hold time specification parameter 106 SCL is held low for one Baud Rate Generator rollover count TBRG Data should be valid before SCL is released high see data setup time spec ification parameter 107 When the SCL pin is released high it is held that way for TBRG The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL After the eighth bit is shifted out the falling edge of the eighth clock the BF flag is cleared and the master releases SDA This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred or if data was received prop erly The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock If the master receives an Acknowledge the Acknowledge Status bit ACKSTAT is cleared If not the bit is set After the ninth clock the SSPIF bit is set and the master clock Baud Rate Generator is suspended until the next data byte is loaded into the SSPBUF leaving SCL low and SDA unchanged Figure 1721 After the write to the SSPBUF each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the RW bit are completed On the falling edge of the eighth clock the master will deassert the SDA pin allowing the slave to respond with an Acknowledge On the falling edge of the ninth clock the master will sample the SDA pin to see if the address was recognized by a slave The status of the ACK bit is loaded into the ACKSTAT status bit SSPCON26 Following the falling edge of the ninth clock transmission of the address the SSPIF is set the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place holding SCL low and allowing SDA to float 174101 BF Status Flag In Transmit mode the BF bit SSPSTAT0 is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out 174102 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress ie SSPSR is still shifting out a data byte the WCOL is set and the contents of the buffer are unchanged the write doesnt occur WCOL must be cleared in software 174103 ACKSTAT Status Flag In Transmit mode the ACKSTAT bit SSPCON26 is cleared when the slave has sent an Acknowledge ACK 0 and is set when the slave does not Acknowl edge ACK 1 A slave sends an Acknowledge when it has recognized its address including a general call or when the slave has properly received its data 17411 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit RCEN SSPCON23 The Baud Rate Generator begins counting and on each rollover the state of the SCL pin changes hightolow lowtohigh and data is shifted into the SSPSR After the falling edge of the eighth clock the receive enable flag is automatically cleared the contents of the SSPSR are loaded into the SSPBUF the BF flag bit is set the SSPIF flag bit is set and the Baud Rate Gener ator is suspended from counting holding SCL low The MSSP is now in Idle state awaiting the next command When the buffer is read by the CPU the BF flag bit is automatically cleared The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit ACKEN SSPCON24 174111 BF Status Flag In receive operation the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR It is cleared when the SSPBUF register is read 174112 SSPOV Status Flag In receive operation the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception 174113 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress ie SSPSR is still shifting in a data byte the WCOL bit is set and the contents of the buffer are unchanged the write doesnt occur Note The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded PIC18F2420252044204520 DS39631Epage 192 2008 Microchip Technology Inc FIGURE 1721 I2C MASTER MODE WAVEFORM TRANSMISSION 7 OR 10BIT ADDRESSING SDA SCL SSPIF BF SSPSTAT0 SEN A7 A6 A5 A4 A3 A2 A1 ACK 0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data or Second Half RW 0 Transmit Address to Slave 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software service routine SSPBUF is written in software from MSSP interrupt After Start condition SEN cleared by hardware S SSPBUF written with 7bit address and RW start transmit SCL held low while CPU responds to SSPIF SEN 0 of 10Bit Address Write SSPCON20 SEN 1 Start condition begins From slave clear ACKSTAT bit SSPCON26 ACKSTAT in SSPCON2 1 Cleared in software SSPBUF written PEN RW Cleared in software 2008 Microchip Technology Inc DS39631Epage 193 PIC18F2420252044204520 FIGURE 1722 I2C MASTER MODE WAVEFORM RECEPTION 7BIT ADDRESSING P 9 8 7 6 5 D0 D1 D2 D3 D4 D5 D6 D7 S A7 A6 A5 A4 A3 A2 A1 SDA SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 Bus master terminates transfer ACK Receiving Data from Slave Receiving Data from Slave D0 D1 D2 D3 D4 D5 D6 D7 ACK RW 0 Transmit Address to Slave SSPIF BF ACK is not sent Write to SSPCON20 SEN 1 Write to SSPBUF occurs here ACK from Slave Master configured as a receiver by programming SSPCON23 RCEN 1 PEN bit 1 written here Data shifted in on falling edge of CLK Cleared in software start XMIT SEN 0 SSPOV SDA 0 SCL 1 while CPU SSPSTAT0 ACK Cleared in software Cleared in software Set SSPIF interrupt at end of receive Set P bit SSPSTAT4 and SSPIF Cleared in software ACK from Master Set SSPIF at end Set SSPIF interrupt at end of Acknowledge sequence Set SSPIF interrupt at end of Acknowledge sequence of receive Set ACKEN start Acknowledge sequence SSPOV is set because SSPBUF is still full SDA ACKDT 1 RCEN cleared automatically RCEN 1 start next receive Write to SSPCON24 to start Acknowledge sequence SDA ACKDT SSPCON25 0 RCEN cleared automatically responds to SSPIF ACKEN begin Start condition Cleared in software SDA ACKDT 0 Last bit is shifted into SSPSR and contents are unloaded into SSPBUF PIC18F2420252044204520 DS39631Epage 194 2008 Microchip Technology Inc 17412 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit ACKEN SSPCON24 When this bit is set the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin If the user wishes to gen erate an Acknowledge then the ACKDT bit should be cleared If not the user should set the ACKDT bit before starting an Acknowledge sequence The Baud Rate Generator then counts for one rollover period TBRG and the SCL pin is deasserted pulled high When the SCL pin is sampled high clock arbitration the Baud Rate Generator counts for TBRG The SCL pin is then pulled low Following this the ACKEN bit is automatically cleared the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode Figure 1723 174121 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress then WCOL is set and the contents of the buffer are unchanged the write doesnt occur 17413 STOP CONDITION TIMING A Stop bit is asserted on the SDA pin at the end of a receivetransmit by setting the Stop Sequence Enable bit PEN SSPCON22 At the end of a receive transmit the SCL line is held low after the falling edge of the ninth clock When the PEN bit is set the master will assert the SDA line low When the SDA line is sampled low the Baud Rate Generator is reloaded and counts down to 0 When the Baud Rate Generator times out the SCL pin will be brought high and one TBRG Baud Rate Generator rollover count later the SDA pin will be deasserted When the SDA pin is sampled high while SCL is high the P bit SSPSTAT4 is set A TBRG later the PEN bit is cleared and the SSPIF bit is set Figure 1724 174131 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence is in progress then the WCOL bit is set and the con tents of the buffer are unchanged the write doesnt occur FIGURE 1723 ACKNOWLEDGE SEQUENCE WAVEFORM FIGURE 1724 STOP CONDITION RECEIVE OR TRANSMIT MODE Note TBRG one Baud Rate Generator period SDA SCL SSPIF set at Acknowledge sequence starts here write to SSPCON2 ACKEN automatically cleared Cleared in TBRG TBRG the end of receive 8 ACKEN 1 ACKDT 0 D0 9 SSPIF software SSPIF set at the end of Acknowledge sequence Cleared in software ACK SCL SDA SDA asserted low before rising edge of clock Write to SSPCON2 set PEN Falling edge of SCL 1 for TBRG followed by SDA 1 for TBRG 9th clock SCL brought high after TBRG Note TBRG one Baud Rate Generator period TBRG TBRG after SDA sampled high P bit SSPSTAT4 is set TBRG to setup Stop condition ACK P TBRG PEN bit SSPCON22 is cleared by hardware and the SSPIF bit is set 2008 Microchip Technology Inc DS39631Epage 195 PIC18F2420252044204520 17414 SLEEP OPERATION While in Sleep mode the I2C module can receive addresses or data and when an address match or complete byte transfer occurs wake the processor from Sleep if the MSSP interrupt is enabled 17415 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer 17416 MULTIMASTER MODE In MultiMaster mode the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free The Stop P and Start S bits are cleared from a Reset or when the MSSP module is disabled Control of the I2C bus may be taken when the P bit SSPSTAT4 is set or the bus is Idle with both the S and P bits clear When the bus is busy enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs In multimaster operation the SDA line must be monitored for arbitration to see if the signal level is the expected output level This check is performed in hardware with the result placed in the BCLIF bit The states where arbitration can be lost are Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition 17417 MULTI MASTER COMMUNICATION BUS COLLISION AND BUS ARBITRATION MultiMaster mode support is achieved by bus arbitra tion When the master outputs addressdata bits onto the SDA pin arbitration takes place when the master outputs a 1 on SDA by letting SDA float high and another master asserts a 0 When the SCL pin floats high data should be stable If the expected data on SDA is a 1 and the data sampled on the SDA pin 0 then a bus collision has taken place The master will set the Bus Collision Interrupt Flag BCLIF and reset the I2C port to its Idle state Figure 1725 If a transmit was in progress when the bus collision occurred the transmission is halted the BF flag is cleared the SDA and SCL lines are deasserted and the SSPBUF can be written to When the user services the bus collision Interrupt Service Routine and if the I2C bus is free the user can resume communication by asserting a Start condition If a Start Repeated Start Stop or Acknowledge condi tion was in progress when the bus collision occurred the condition is aborted the SDA and SCL lines are deas serted and the respective control bits in the SSPCON2 register are cleared When the user services the bus collision Interrupt Service Routine and if the I2C bus is free the user can resume communication by asserting a Start condition The master will continue to monitor the SDA and SCL pins If a Stop condition occurs the SSPIF bit will be set A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred In MultiMaster mode the interrupt generation on the detection of Start and Stop conditions allows the deter mination of when the bus is free Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register or the bus is Idle and the S and P bits are cleared FIGURE 1725 BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA SCL BCLIF SDA released SDA line pulled low by another source Sample SDA While SCL is high data doesnt match what is driven Bus collision has occurred Set bus collision interrupt BCLIF by the master by master Data changes while SCL 0 PIC18F2420252044204520 DS39631Epage 196 2008 Microchip Technology Inc 174171 Bus Collision During a Start Condition During a Start condition a bus collision occurs if a SDA or SCL is sampled low at the beginning of the Start condition Figure 1726 b SCL is sampled low before SDA is asserted low Figure 1727 During a Start condition both the SDA and the SCL pins are monitored If the SDA pin is already low or the SCL pin is already low then all of the following occur the Start condition is aborted the BCLIF flag is set and the MSSP module is reset to its Idle state Figure 1726 The Start condition begins with the SDA and SCL pins deasserted When the SDA pin is sampled high the Baud Rate Generator is loaded from SSPADD60 and counts down to 0 If the SCL pin is sampled low while SDA is high a bus collision occurs because it is assumed that another master is attempting to drive a data 1 during the Start condition If the SDA pin is sampled low during this count the BRG is reset and the SDA line is asserted early Figure 1728 If however a 1 is sampled on the SDA pin the SDA pin is asserted low at the end of the BRG count The Baud Rate Generator is then reloaded and counts down to 0 if the SCL pin is sampled as 0 during this time a bus collision does not occur At the end of the BRG count the SCL pin is asserted low FIGURE 1726 BUS COLLISION DURING START CONDITION SDA ONLY Note The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time Therefore one master will always assert SDA before the other This condition does not cause a bus colli sion because the two masters must be allowed to arbitrate the first address fol lowing the Start condition If the address is the same arbitration must be allowed to continue into the data portion Repeated Start or Stop conditions SDA SCL SEN SDA sampled low before SDA goes low before the SEN bit is set S bit and SSPIF set because MSSP module reset into Idle state SEN cleared automatically because of bus collision S bit and SSPIF set because Set SEN enable Start condition if SDA 1 SCL 1 SDA 0 SCL 1 BCLIF S SSPIF SDA 0 SCL 1 SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software Set BCLIF Start condition Set BCLIF 2008 Microchip Technology Inc DS39631Epage 197 PIC18F2420252044204520 FIGURE 1727 BUS COLLISION DURING START CONDITION SCL 0 FIGURE 1728 BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA SCL SEN bus collision occurs Set BCLIF SCL 0 before SDA 0 Set SEN enable Start sequence if SDA 1 SCL 1 TBRG TBRG SDA 0 SCL 1 BCLIF S SSPIF Interrupt cleared in software bus collision occurs Set BCLIF SCL 0 before BRG timeout 0 0 0 0 SDA SCL SEN Set S Less than TBRG TBRG SDA 0 SCL 1 BCLIF S SSPIF S Interrupts cleared in software set SSPIF SDA 0 SCL 1 SCL pulled low after BRG timeout Set SSPIF 0 SDA pulled low by other master Reset BRG and assert SDA Set SEN enable Start sequence if SDA 1 SCL 1 PIC18F2420252044204520 DS39631Epage 198 2008 Microchip Technology Inc 174172 Bus Collision During a Repeated Start Condition During a Repeated Start condition a bus collision occurs if a A low level is sampled on SDA when SCL goes from low level to high level b SCL goes low before SDA is asserted low indicating that another master is attempting to transmit a data 1 When the user deasserts SDA and the pin is allowed to float high the BRG is loaded with SSPADD60 and counts down to 0 The SCL pin is then deasserted and when sampled high the SDA pin is sampled If SDA is low a bus collision has occurred ie another master is attempting to transmit a data 0 Figure 1729 If SDA is sampled high the BRG is reloaded and begins counting If SDA goes from hightolow before the BRG times out no bus collision occurs because no two masters can assert SDA at exactly the same time If SCL goes from hightolow before the BRG times out and SDA has not already been asserted a bus collision occurs In this case another master is attempting to transmit a data 1 during the Repeated Start condition see Figure 1730 If at the end of the BRG timeout both SCL and SDA are still high the SDA pin is driven low and the BRG is reloaded and begins counting At the end of the count regardless of the status of the SCL pin the SCL pin is driven low and the Repeated Start condition is complete FIGURE 1729 BUS COLLISION DURING A REPEATED START CONDITION CASE 1 FIGURE 1730 BUS COLLISION DURING REPEATED START CONDITION CASE 2 SDA SCL RSEN BCLIF S SSPIF Sample SDA when SCL goes high If SDA 0 set BCLIF and release SDA and SCL Cleared in software 0 0 SDA SCL BCLIF RSEN S SSPIF Interrupt cleared in software SCL goes low before SDA set BCLIF Release SDA and SCL TBRG TBRG 0 2008 Microchip Technology Inc DS39631Epage 199 PIC18F2420252044204520 174173 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if a After the SDA pin has been deasserted and allowed to float high SDA is sampled low after the BRG has timed out b After the SCL pin is deasserted SCL is sampled low before SDA goes high The Stop condition begins with SDA asserted low When SDA is sampled low the SCL pin is allowed to float When the pin is sampled high clock arbitration the Baud Rate Generator is loaded with SSPADD60 and counts down to 0 After the BRG times out SDA is sampled If SDA is sampled low a bus collision has occurred This is due to another master attempting to drive a data 0 Figure 1731 If the SCL pin is sampled low before SDA is allowed to float high a bus collision occurs This is another case of another master attempting to drive a data 0 Figure 1732 FIGURE 1731 BUS COLLISION DURING A STOP CONDITION CASE 1 FIGURE 1732 BUS COLLISION DURING A STOP CONDITION CASE 2 SDA SCL BCLIF PEN P SSPIF TBRG TBRG TBRG SDA asserted low SDA sampled low after TBRG set BCLIF 0 0 SDA SCL BCLIF PEN P SSPIF TBRG TBRG TBRG Assert SDA SCL goes low before SDA goes high set BCLIF 0 0 PIC18F2420252044204520 DS39631Epage 200 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 201 PIC18F2420252044204520 180 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER EUSART The Enhanced Universal Synchronous Asynchronous Receiver Transmitter EUSART module is one of the two serial IO modules Generically the USART is also known as a Serial Communications Interface or SCI The EUSART can be configured as a fullduplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers It can also be configured as a half duplex synchronous system that can communicate with peripheral devices such as AD or DA integrated circuits serial EEPROMs etc The Enhanced USART module implements additional features including automatic baud rate detection and calibration automatic wakeup on Sync Break recep tion and 12bit Break character transmit These make it ideally suited for use in Local Interconnect Network bus LIN bus systems The EUSART can be configured in the following modes Asynchronous full duplex with Autowakeup on character reception Autobaud calibration 12bit Break character transmission Synchronous Master half duplex with selectable clock polarity Synchronous Slave half duplex with selectable clock polarity The pins of the Enhanced USART are multiplexed with PORTC In order to configure RC6TXCK and RC7RXDT as an EUSART bit SPEN RCSTA7 must be set 1 bit TRISC7 must be set 1 bit TRISC6 must be set 1 The operation of the Enhanced USART module is controlled through three registers Transmit Status and Control TXSTA Receive Status and Control RCSTA Baud Rate Control BAUDCON These are detailed on the following pages in Register 181 Register 182 and Register 183 respectively Note The EUSART control will automatically reconfigure the pin from input to output as needed PIC18F2420252044204520 DS39631Epage 202 2008 Microchip Technology Inc REGISTER 181 TXSTA TRANSMIT STATUS AND CONTROL REGISTER RW0 RW0 RW0 RW0 RW0 RW0 R1 RW0 CSRC TX9 TXEN1 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 CSRC Clock Source Select bit Asynchronous mode Dont care Synchronous mode 1 Master mode clock generated internally from BRG 0 Slave mode clock from external source bit 6 TX9 9Bit Transmit Enable bit 1 Selects 9bit transmission 0 Selects 8bit transmission bit 5 TXEN Transmit Enable bit1 1 Transmit enabled 0 Transmit disabled bit 4 SYNC EUSART Mode Select bit 1 Synchronous mode 0 Asynchronous mode bit 3 SENDB Send Break Character bit Asynchronous mode 1 Send Sync Break on next transmission cleared by hardware upon completion 0 Sync Break transmission completed Synchronous mode Dont care bit 2 BRGH High Baud Rate Select bit Asynchronous mode 1 High speed 0 Low speed Synchronous mode Unused in this mode bit 1 TRMT Transmit Shift Register Status bit 1 TSR empty 0 TSR full bit 0 TX9D 9th Bit of Transmit Data Can be addressdata bit or a parity bit Note 1 SRENCREN overrides TXEN in Sync mode 2008 Microchip Technology Inc DS39631Epage 203 PIC18F2420252044204520 REGISTER 182 RCSTA RECEIVE STATUS AND CONTROL REGISTER RW0 RW0 RW0 RW0 RW0 R0 R0 Rx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 SPEN Serial Port Enable bit 1 Serial port enabled configures RXDT and TXCK pins as serial port pins 0 Serial port disabled held in Reset bit 6 RX9 9Bit Receive Enable bit 1 Selects 9bit reception 0 Selects 8bit reception bit 5 SREN Single Receive Enable bit Asynchronous mode Dont care Synchronous mode Master 1 Enables single receive 0 Disables single receive This bit is cleared after reception is complete Synchronous mode Slave Dont care bit 4 CREN Continuous Receive Enable bit Asynchronous mode 1 Enables receiver 0 Disables receiver Synchronous mode 1 Enables continuous receive until enable bit CREN is cleared CREN overrides SREN 0 Disables continuous receive bit 3 ADDEN Address Detect Enable bit Asynchronous mode 9Bit RX9 1 1 Enables address detection enables interrupt and loads the receive buffer when RSR8 is set 0 Disables address detection all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9Bit RX9 0 Dont care bit 2 FERR Framing Error bit 1 Framing error can be cleared by reading RCREG register and receiving next valid byte 0 No framing error bit 1 OERR Overrun Error bit 1 Overrun error can be cleared by clearing bit CREN 0 No overrun error bit 0 RX9D 9th Bit of Received Data This can be addressdata bit or a parity bit and must be calculated by user firmware PIC18F2420252044204520 DS39631Epage 204 2008 Microchip Technology Inc REGISTER 183 BAUDCON BAUD RATE CONTROL REGISTER RW0 R1 RW0 RW0 RW0 U0 RW0 RW0 ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 ABDOVF AutoBaud Acquisition Rollover Status bit 1 A BRG rollover has occurred during AutoBaud Rate Detect mode must be cleared in software 0 No BRG rollover has occurred bit 6 RCIDL Receive Operation Idle Status bit 1 Receive operation is Idle 0 Receive operation is active bit 5 RXDTP DataReceive Polarity Select bit Asynchronous mode 1 Receive data RX is inverted activelow 0 Receive data RX is not inverted activehigh Synchronous mode 1 Data DT is inverted activelow 0 Data DT is not inverted activehigh bit 4 TXCKP Clock and Data Polarity Select bit Asynchronous mode 1 Idle state for transmit TX is a low level 0 Idle state for transmit TX is a high level Synchronous mode 1 Idle state for clock CK is a high level 0 Idle state for clock CK is a low level bit 3 BRG16 16Bit Baud Rate Register Enable bit 1 16bit Baud Rate Generator SPBRGH and SPBRG 0 8bit Baud Rate Generator SPBRG only Compatible mode SPBRGH value ignored bit 2 Unimplemented Read as 0 bit 1 WUE Wakeup Enable bit Asynchronous mode 1 EUSART will continue to sample the RX pin interrupt generated on falling edge bit cleared in hardware on following rising edge 0 RX pin not monitored or rising edge detected Synchronous mode Unused in this mode bit 0 ABDEN AutoBaud Detect Enable bit Asynchronous mode 1 Enable baud rate measurement on the next character Requires reception of a Sync field 55h cleared in hardware upon completion 0 Baud rate measurement disabled or completed Synchronous mode Unused in this mode 2008 Microchip Technology Inc DS39631Epage 205 PIC18F2420252044204520 181 Baud Rate Generator BRG The BRG is a dedicated 8bit or 16bit generator that supports both the Asynchronous and Synchronous modes of the EUSART By default the BRG operates in 8bit mode setting the BRG16 bit BAUDCON3 selects 16bit mode The SPBRGHSPBRG register pair controls the period of a freerunning timer In Asynchronous mode bits BRGH TXSTA2 and BRG16 BAUDCON3 also control the baud rate In Synchronous mode BRGH is ignored Table 181 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode internally generated clock Given the desired baud rate and FOSC the nearest integer value for the SPBRGHSPBRG registers can be calculated using the formulas in Table 181 From this the error in baud rate can be determined An example calculation is shown in Example 181 Typical baud rates and error values for the various Asynchronous modes are shown in Table 182 It may be advantageous to use the high baud rate BRGH 1 or the 16bit BRG to reduce the baud rate error or achieve a slow baud rate for a fast oscillator frequency Writing a new value to the SPBRGHSPBRG registers causes the BRG timer to be reset or cleared This ensures the BRG does not wait for a timer overflow before outputting the new baud rate 1811 OPERATION IN POWERMANAGED MODES The device clock is used to generate the desired baud rate When one of the powermanaged modes is entered the new clock source may be operating at a different frequency This may require an adjustment to the value in the SPBRG register pair 1812 SAMPLING The data on the RX pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin TABLE 181 BAUD RATE FORMULAS Configuration Bits BRGEUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8BitAsynchronous FOSC64 n 1 0 0 1 8BitAsynchronous FOSC16 n 1 0 1 0 16BitAsynchronous 0 1 1 16BitAsynchronous FOSC4 n 1 1 0 x 8BitSynchronous 1 1 x 16BitSynchronous Legend x Dont care n value of SPBRGHSPBRG register pair PIC18F2420252044204520 DS39631Epage 206 2008 Microchip Technology Inc EXAMPLE 181 CALCULATING BAUD RATE ERROR TABLE 182 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend unimplemented read as 0 Shaded cells are not used by the BRG For a device with FOSC of 16 MHz desired baud rate of 9600 Asynchronous mode 8bit BRG Desired Baud Rate FOSC64 SPBRGHSPBRG 1 Solving for SPBRGHSPBRG X FOSCDesired Baud Rate64 1 16000000960064 1 25042 25 Calculated Baud Rate 1600000064 25 1 9615 Error Calculated Baud Rate Desired Baud RateDesired Baud Rate 9615 96009600 016 2008 Microchip Technology Inc DS39631Epage 207 PIC18F2420252044204520 TABLE 183 BAUD RATES FOR ASYNCHRONOUS MODES BAUD RATE K SYNC 0 BRGH 0 BRG16 0 FOSC 40000 MHz FOSC 20000 MHz FOSC 10000 MHz FOSC 8000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 12 1221 173 255 1202 016 129 1201 016 103 24 2441 173 255 2404 016 129 2404 016 64 2403 016 51 96 9615 016 64 9766 173 31 9766 173 15 9615 016 12 192 19531 173 31 19531 173 15 19531 173 7 576 56818 136 10 62500 851 4 52083 958 2 1152 125000 851 4 104167 958 2 78125 3218 1 BAUD RATE K SYNC 0 BRGH 0 BRG16 0 FOSC 4000 MHz FOSC 2000 MHz FOSC 1000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 0300 016 207 0300 016 103 0300 016 51 12 1202 016 51 1201 016 25 1201 016 12 24 2404 016 25 2403 016 12 96 8929 699 6 192 20833 851 2 576 62500 851 0 1152 62500 4575 0 BAUD RATE K SYNC 0 BRGH 1 BRG16 0 FOSC 40000 MHz FOSC 20000 MHz FOSC 10000 MHz FOSC 8000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 12 24 2441 173 255 2403 016 207 96 9766 173 255 9615 016 129 9615 016 64 9615 016 51 192 19231 016 129 19231 016 64 19531 173 31 19230 016 25 576 58140 094 42 56818 136 21 56818 136 10 55555 355 8 1152 113636 136 21 113636 136 10 125000 851 4 BAUD RATE K SYNC 0 BRGH 1 BRG16 0 FOSC 4000 MHz FOSC 2000 MHz FOSC 1000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 0300 016 207 12 1202 016 207 1201 016 103 1201 016 51 24 2404 016 103 2403 016 51 2403 016 25 96 9615 016 25 9615 016 12 192 19231 016 12 576 62500 851 3 1152 125000 851 1 PIC18F2420252044204520 DS39631Epage 208 2008 Microchip Technology Inc BAUD RATE K SYNC 0 BRGH 0 BRG16 1 FOSC 40000 MHz FOSC 20000 MHz FOSC 10000 MHz FOSC 8000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 0300 000 8332 0300 002 4165 0300 002 2082 0300 004 1665 12 1200 002 2082 1200 003 1041 1200 003 520 1201 016 415 24 2402 006 1040 2399 003 520 2404 016 259 2403 016 207 96 9615 016 259 9615 016 129 9615 016 64 9615 016 51 192 19231 016 129 19231 016 64 19531 173 31 19230 016 25 576 58140 094 42 56818 136 21 56818 136 10 55555 355 8 1152 113636 136 21 113636 136 10 125000 851 4 BAUD RATE K SYNC 0 BRGH 0 BRG16 1 FOSC 4000 MHz FOSC 2000 MHz FOSC 1000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 0300 004 832 0300 016 415 0300 016 207 12 1202 016 207 1201 016 103 1201 016 51 24 2404 016 103 2403 016 51 2403 016 25 96 9615 016 25 9615 016 12 192 19231 016 12 576 62500 851 3 1152 125000 851 1 BAUD RATE K SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 FOSC 40000 MHz FOSC 20000 MHz FOSC 10000 MHz FOSC 8000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 0300 000 33332 0300 000 16665 0300 000 8332 0300 001 6665 12 1200 000 8332 1200 002 4165 1200 002 2082 1200 004 1665 24 2400 002 4165 2400 002 2082 2402 006 1040 2400 004 832 96 9606 006 1040 9596 003 520 9615 016 259 9615 016 207 192 19193 003 520 19231 016 259 19231 016 129 19230 016 103 576 57803 035 172 57471 022 86 58140 094 42 57142 079 34 1152 114943 022 86 116279 094 42 113636 136 21 117647 212 16 BAUD RATE K SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 FOSC 4000 MHz FOSC 2000 MHz FOSC 1000 MHz Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal Actual Rate K Error SPBRG Value decimal 03 0300 001 3332 0300 004 1665 0300 004 832 12 1200 004 832 1201 016 415 1201 016 207 24 2404 016 415 2403 016 207 2403 016 103 96 9615 016 103 9615 016 51 9615 016 25 192 19231 016 51 19230 016 25 19230 016 12 576 58824 212 16 55555 355 8 1152 111111 355 8 TABLE 183 BAUD RATES FOR ASYNCHRONOUS MODES CONTINUED 2008 Microchip Technology Inc DS39631Epage 209 PIC18F2420252044204520 1813 AUTOBAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate This feature is active only in Asynchronous mode and while the WUE bit is clear The automatic baud rate measurement sequence Figure 181 begins whenever a Start bit is received and the ABDEN bit is set The calculation is selfaveraging In the AutoBaud Rate Detect ABD mode the clock to the BRG is reversed Rather than the BRG clocking the incoming RX signal the RX signal is timing the BRG In ABD mode the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream Once the ABDEN bit is set the state machine will clear the BRG and look for a Start bit The AutoBaud Rate Detect must receive a byte with the value 55h ASCII U which is also the LIN bus Sync character in order to calculate the proper bit rate The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal After a Start bit the SPBRG begins counting up using the preselected clock source on the first rising edge of RX After eight bits on the RX pin or the fifth rising edge an accumulated value totalling the proper BRG period is left in the SPBRGHSPBRG register pair Once the 5th edge is seen this should correspond to the Stop bit the ABDEN bit is automatically cleared If a rollover of the BRG occurs an overflow from FFFFh to 0000h the event is trapped by the ABDOVF status bit BAUDCON7 It is set in hardware by BRG roll overs and can be set or cleared by the user in software ABD mode remains active after rollover events and the ABDEN bit remains set Figure 182 While calibrating the baud rate period the BRG regis ters are clocked at 18th the preconfigured clock rate Note that the BRG clock will be configured by the BRG16 and BRGH bits Independent of the BRG16 bit setting both the SPBRG and SPBRGH will be used as a 16bit counter This allows the user to verify that no carry occurred for 8bit modes by checking for 00h in the SPBRGH register Refer to Table 184 for counter clock rates to the BRG While the ABD sequence takes place the EUSART state machine is held in Idle The RCIF interrupt is set once the fifth rising edge on RX is detected The value in the RCREG needs to be read to clear the RCIF interrupt The contents of RCREG should be discarded TABLE 184 BRG COUNTER CLOCK RATES 18131 ABD and EUSART Transmission Since the BRG clock is reversed during ABD acquisi tion the EUSART transmitter cannot be used during ABD This means that whenever the ABDEN bit is set TXREG cannot be written to Users should also ensure that ABDEN does not become set during a transmit sequence Failing to do this may result in unpredictable EUSART operation Note 1 If the WUE bit is set with the ABDEN bit AutoBaud Rate Detection will occur on the byte following the Break character 2 It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates Overall system tim ing and communication baud rates must be taken into consideration when using the AutoBaud Rate Detection feature BRG16 BRGH BRG Counter Clock 0 0 FOSC512 0 1 FOSC128 1 0 FOSC128 1 1 FOSC32 Note During the ABD sequence SPBRG and SPBRGH are both used as a 16bit counter independent of BRG16 setting PIC18F2420252044204520 DS39631Epage 210 2008 Microchip Technology Inc FIGURE 181 AUTOMATIC BAUD RATE CALCULATION FIGURE 182 BRG OVERFLOW SEQUENCE BRG Value RX pin ABDEN bit RCIF bit Bit 0 Bit 1 Interrupt Read RCREG BRG Clock Start AutoCleared Set by User XXXXh 0000h Edge 1 Bit 2 Bit 3 Edge 2 Bit 4 Bit 5 Edge 3 Bit 6 Bit 7 Edge 4 Stop Bit Edge 5 001Ch Note The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE 0 SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Start Bit 0 XXXXh 0000h 0000h FFFFh BRG Clock ABDEN bit RX pin ABDOVF bit BRG Value 2008 Microchip Technology Inc DS39631Epage 211 PIC18F2420252044204520 182 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit TXSTA4 In this mode the EUSART uses standard NonReturntoZero NRZ for mat one Start bit eight or nine data bits and one Stop bit The most common data format is 8 bits An onchip dedicated 8bit16bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator The EUSART transmits and receives the LSb first The EUSARTs transmitter and receiver are functionally independent but use the same data format and baud rate The Baud Rate Generator produces a clock either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits TXSTA2 and BAUDCON3 Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit When operating in Asynchronous mode the EUSART module consists of the following important elements Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver AutoWakeup on Sync Break Character 12Bit Break Character Transmit AutoBaud Rate Detection 1821 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 183 The heart of the transmitter is the Transmit Serial Shift Register TSR The Shift register obtains its data from the ReadWrite Transmit Buffer register TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the Stop bit has been transmitted from the previous load As soon as the Stop bit is transmitted the TSR is loaded with new data from the TXREG register if available Once the TXREG register transfers the data to the TSR register occurs in one TCY the TXREG register is empty and the TXIF flag bit PIR14 is set This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit TXIE PIE14 TXIF will be set regardless of the state of TXIE it cannot be cleared in software TXIF is also not cleared immediately upon loading TXREG but becomes valid in the second instruction cycle following the load instruction Polling TXIF immediately following a load of TXREG will return invalid results While TXIF indicates the status of the TXREG register another bit TRMT TXSTA1 shows the status of the TSR register TRMT is a readonly bit which is set when the TSR register is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty To set up an Asynchronous Transmission 1 Initialize the SPBRGHSPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 2 Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN 3 If interrupts are desired set enable bit TXIE 4 If 9bit transmission is desired set transmit bit TX9 Can be used as addressdata bit 5 Enable the transmission by setting bit TXEN which will also set bit TXIF 6 If 9bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Load data to the TXREG register starts transmission 8 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON76 are set FIGURE 183 EUSART TRANSMIT BLOCK DIAGRAM Note 1 The TSR register is not mapped in data memory so it is not available to the user 2 Flag bit TXIF is set when enable bit TXEN is set TXIF TXIE Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator TX9D MSb LSb Data Bus TXREG Register TSR Register 8 0 TX9 TRMT SPEN TX pin Pin Buffer and Control 8 SPBRGH BRG16 PIC18F2420252044204520 DS39631Epage 212 2008 Microchip Technology Inc FIGURE 184 ASYNCHRONOUS TRANSMISSION FIGURE 185 ASYNCHRONOUS TRANSMISSION BACK TO BACK TABLE 185 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 TXREG EUSART Transmit Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend unimplemented locations read as 0 Shaded cells are not used for asynchronous transmission Note 1 Reserved in 28pin devices always maintain these bits clear Word 1 Word 1 Transmit Shift Reg Start bit bit 0 bit 1 bit 78 Write to TXREG BRG Output Shift Clock TX pin TXIF bit Transmit Buffer Reg Empty Flag TRMT bit Transmit Shift Reg Empty Flag 1 TCY Stop bit Word 1 Transmit Shift Reg Write to TXREG BRG Output Shift Clock TX pin TXIF bit Interrupt Reg Flag TRMT bit Transmit Shift Reg Empty Flag Word 1 Word 2 Word 1 Word 2 Stop bit Start bit Transmit Shift Reg Word 1 Word 2 bit 0 bit 1 bit 78 bit 0 Note This timing diagram shows two consecutive transmissions 1 TCY 1 TCY Start bit 2008 Microchip Technology Inc DS39631Epage 213 PIC18F2420252044204520 1822 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 186 The data is received on the RX pin and drives the data recovery block The data recovery block is actually a highspeed shifter operating at x16 times the baud rate whereas the main receive serial shifter operates at the bit rate or at FOSC This mode would typically be used in RS232 systems To set up an Asynchronous Reception 1 Initialize the SPBRGHSPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 2 Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN 3 If interrupts are desired set enable bit RCIE 4 If 9bit reception is desired set bit RX9 5 Enable the reception by setting bit CREN 6 Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set 7 Read the RCSTA register to get the 9th bit if enabled and determine if any error occurred during reception 8 Read the 8bit received data by reading the RCREG register 9 If any error occurred clear the error by clearing enable bit CREN 10 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON76 are set 1823 SETTING UP 9BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS485 systems To set up an Asynchronous Reception with Address Detect Enable 1 Initialize the SPBRGHSPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 2 Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit 3 If interrupts are required set the RCEN bit and select the desired priority level with the RCIP bit 4 Set the RX9 bit to enable 9bit reception 5 Set the ADDEN bit to enable address detect 6 Enable reception by setting the CREN bit 7 The RCIF bit will be set when reception is complete The interrupt will be Acknowledged if the RCIE and GIE bits are set 8 Read the RCSTA register to determine if any error occurred during reception as well as read bit 9 of data if applicable 9 Read RCREG to determine if the device is being addressed 10 If any error occurred clear the CREN bit 11 If the device has been addressed clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU FIGURE 186 EUSART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK Baud Rate Generator RX Pin Buffer and Control SPEN Data Recovery CREN OERR FERR RSR Register MSb LSb RX9D RCREG Register FIFO Interrupt RCIF RCIE Data Bus 8 64 16 or Stop Start 8 7 1 0 RX9 SPBRG SPBRGH BRG16 or 4 PIC18F2420252044204520 DS39631Epage 214 2008 Microchip Technology Inc FIGURE 187 ASYNCHRONOUS RECEPTION TABLE 186 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION 1824 AUTOWAKEUP ON SYNC BREAK CHARACTER During Sleep mode all clocks to the EUSART are suspended Because of this the Baud Rate Generator is inactive and a proper byte reception cannot be per formed The autowakeup feature allows the controller to wakeup due to activity on the RXDT line while the EUSART is operating in Asynchronous mode The autowakeup feature is enabled by setting the WUE bit BAUDCON1 Once set the typical receive sequence on RXDT is disabled and the EUSART remains in an Idle state monitoring for a wakeup event independent of the CPU mode A wakeup event con sists of a hightolow transition on the RXDT line This coincides with the start of a Sync Break or a Wakeup Signal character for the LIN protocol Following a wakeup event the module generates an RCIF interrupt The interrupt is generated synchro nously to the Q clocks in normal operating modes Figure 188 and asynchronously if the device is in Sleep mode Figure 189 The interrupt condition is cleared by reading the RCREG register The WUE bit is automatically cleared once a lowto high transition is observed on the RX line following the wakeup event At this point the EUSART module is in Idle mode and returns to normal operation This signals to the user that the Sync Break event is over Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCREG EUSART Receive Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend unimplemented locations read as 0 Shaded cells are not used for asynchronous reception Note 1 Reserved in 28pin devices always maintain these bits clear Start bit bit 78 bit 1 bit 0 bit 78 bit 0 Stop bit Start bit Start bit bit 78 Stop bit RX pin Rcv Buffer Reg Rcv Shift Reg Read Rcv Buffer Reg RCREG RCIF Interrupt Flag OERR bit CREN Word 1 RCREG Word 2 RCREG Stop bit Note This timing diagram shows three words appearing on the RX input The RCREG receive buffer is read after the third word causing the OERR overrun bit to be set 2008 Microchip Technology Inc DS39631Epage 215 PIC18F2420252044204520 18241 Special Considerations Using AutoWakeup Since autowakeup functions by sensing rising edge transitions on RXDT information with any state changes before the Stop bit may signal a false Endof Character EOC and cause data or framing errors To work properly therefore the initial character in the transmission must be all 0s This can be 00h 8 bytes for standard RS232 devices or 000h 12 bits for LIN bus Oscillator startup time must also be considered especially in applications using oscillators with longer startup intervals ie XT or HS mode The Sync Break or Wakeup Signal character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART 18242 Special Considerations Using the WUE Bit The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data As noted setting the WUE bit places the EUSART in an Idle mode The wakeup event causes a receive interrupt by setting the RCIF bit The WUE bit is cleared after this when a rising edge is seen on RXDT The interrupt condition is then cleared by reading the RCREG register Ordinarily the data in RCREG will be dummy data and should be discarded The fact that the WUE bit has been cleared or is still set and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG Users should consider implementing a parallel method in firmware to verify received data integrity To assure that no actual data is lost check the RCIDL bit to verify that a receive operation is not in process If a receive operation is not occurring the WUE bit may then be set just prior to entering the Sleep mode FIGURE 188 AUTOWAKEUP BIT WUE TIMINGS DURING NORMAL OPERATION FIGURE 189 AUTOWAKEUP BIT WUE TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit1 RXDT Line RCIF Note 1 The EUSART remains in Idle while the WUE bit is set Bit Set by User Cleared Due to User Read of RCREG AutoCleared Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit2 RXDT Line RCIF Bit Set by User Cleared Due to User Read of RCREG Sleep Command Executed Note 1 If the wakeup event requires long oscillator warmup time the autoclear of the WUE bit can occur before the oscillator is ready This sequence should not depend on the presence of Q clocks 2 The EUSART remains in Idle while the WUE bit is set Sleep Ends Note 1 AutoCleared PIC18F2420252044204520 DS39631Epage 216 2008 Microchip Technology Inc 1825 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard The Break character transmit consists of a Start bit followed by twelve 0 bits and a Stop bit The frame Break character is sent whenever the SENDB and TXEN bits TXSTA3 and TXSTA5 are set while the Transmit Shift register is loaded with data Note that the value of data written to TXREG will be ignored and all 0s will be transmitted The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent This allows the user to preload the transmit FIFO with the next transmit byte following the Break character typically the Sync character in the LIN specification Note that the data value written to the TXREG for the Break character is ignored The write simply serves the purpose of initiating the proper sequence The TRMT bit indicates when the transmit operation is active or Idle just as it does during normal transmis sion See Figure 1810 for the timing of the Break character sequence 18251 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break followed by an AutoBaud Sync byte This sequence is typical of a LIN bus master 1 Configure the EUSART for the desired mode 2 Set the TXEN and SENDB bits to set up the Break character 3 Load the TXREG with a dummy character to initiate transmission the value is ignored 4 Write 55h to TXREG to load the Sync character into the transmit FIFO buffer 5 After the Break has been sent the SENDB bit is reset by hardware The Sync character now transmits in the preconfigured mode When the TXREG becomes empty as indicated by the TXIF the next data byte can be written to TXREG 1826 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways The first method forces configuration of the baud rate at a frequency of 913 the typical speed This allows for the Stop bit transition to be at the correct sampling loca tion 13 bits for Break versus Start bit and 8 data bits for typical data The second method uses the autowakeup feature described in Section 1824 AutoWakeup on Sync Break Character By enabling this feature the EUSART will sample the next two transitions on RXDT cause an RCIF interrupt and receive the next data byte followed by another interrupt Note that following a Break character the user will typically want to enable the AutoBaud Rate Detect feature For both methods the user can set the ABD bit once the TXIF interrupt is observed FIGURE 1810 SEND BREAK CHARACTER SEQUENCE Write to TXREG BRG Output Shift Clock Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit Transmit Buffer Reg Empty Flag TX pin TRMT bit Transmit Shift Reg Empty Flag SENDB Transmit Shift Reg Empty Flag SENDB Sampled Here AutoCleared Dummy Write 2008 Microchip Technology Inc DS39631Epage 217 PIC18F2420252044204520 183 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit TXSTA7 In this mode the data is transmitted in a halfduplex manner ie transmission and reception do not occur at the same time When transmitting data the reception is inhibited and vice versa Synchronous mode is entered by setting bit SYNC TXSTA4 In addition enable bit SPEN RCSTA7 is set in order to configure the TX and RX pins to CK clock and DT data lines respectively The Master mode indicates that the processor trans mits the master clock on the CK line Clock polarity is selected with the TXCKP bit BAUDCON4 setting TXCKP sets the Idle state on CK as high while clearing the bit sets the Idle state as low This option is provided to support Microwire devices with this module 1831 EUSART SYNCHRONOUS MASTER TRANSMISSION The EUSART transmitter block diagram is shown in Figure 183 The heart of the transmitter is the Transmit Serial Shift Register TSR The Shift register obtains its data from the ReadWrite Transmit Buffer register TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the last bit has been transmitted from the previous load As soon as the last bit is transmitted the TSR is loaded with new data from the TXREG if available Once the TXREG register transfers the data to the TSR register occurs in one TCY the TXREG is empty and the TXIF flag bit PIR14 is set The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit TXIE PIE14 TXIF is set regardless of the state of enable bit TXIE it cannot be cleared in software It will reset only when new data is loaded into the TXREG register While flag bit TXIF indicates the status of the TXREG register another bit TRMT TXSTA1 shows the status of the TSR register TRMT is a readonly bit which is set when the TSR is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to deter mine if the TSR register is empty The TSR is not mapped in data memory so it is not available to the user To set up a Synchronous Master Transmission 1 Initialize the SPBRGHSPBRG registers for the appropriate baud rate Set or clear the BRG16 bit as required to achieve the desired baud rate 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC 3 If interrupts are desired set enable bit TXIE 4 If 9bit transmission is desired set bit TX9 5 Enable the transmission by setting bit TXEN 6 If 9bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Start transmission by loading data to the TXREG register 8 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON76 are set FIGURE 1811 SYNCHRONOUS TRANSMISSION bit 0 bit 1 bit 7 Word 1 Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 2 bit 0 bit 1 bit 7 RC7RXDT RC6TXCK pin Write to TXREG Reg TXIF bit Interrupt Flag TXEN bit 1 1 Word 2 TRMT bit Write Word 1 Write Word 2 Note Sync Master mode SPBRG 0 continuous transmission of two 8bit words RC6TXCK pin TXCKP 0 TXCKP 1 PIC18F2420252044204520 DS39631Epage 218 2008 Microchip Technology Inc FIGURE 1812 SYNCHRONOUS TRANSMISSION THROUGH TXEN TABLE 187 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 TXREG EUSART Transmit Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend unimplemented read as 0 Shaded cells are not used for synchronous master transmission Note 1 Reserved in 28pin devices always maintain these bits clear RC7RXDT pin RC6TXCK pin Write to TXREG reg TXIF bit TRMT bit bit 0 bit 1 bit 2 bit 6 bit 7 TXEN bit 2008 Microchip Technology Inc DS39631Epage 219 PIC18F2420252044204520 1832 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected reception is enabled by setting either the Single Receive Enable bit SREN RCSTA5 or the Continuous Receive Enable bit CREN RCSTA4 Data is sampled on the RX pin on the falling edge of the clock If enable bit SREN is set only a single word is received If enable bit CREN is set the reception is continuous until CREN is cleared If both bits are set then CREN takes precedence To set up a Synchronous Master Reception 1 Initialize the SPBRGHSPBRG registers for the appropriate baud rate Set or clear the BRG16 bit as required to achieve the desired baud rate 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC 3 Ensure bits CREN and SREN are clear 4 If interrupts are desired set enable bit RCIE 5 If 9bit reception is desired set bit RX9 6 If a single reception is required set bit SREN For continuous reception set bit CREN 7 Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set 8 Read the RCSTA register to get the 9th bit if enabled and determine if any error occurred during reception 9 Read the 8bit received data by reading the RCREG register 10 If any error occurred clear the error by clearing bit CREN 11 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON76 are set FIGURE 1813 SYNCHRONOUS RECEPTION MASTER MODE SREN TABLE 188 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCREG EUSART Receive Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend unimplemented read as 0 Shaded cells are not used for synchronous master reception Note 1 Reserved in 28pin devices always maintain these bits clear CREN bit RC7RXDT RC6TXCK pin Write to bit SREN SREN bit RCIF bit Interrupt Read RXREG Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 Q1 Q2 Q3 Q4 Note Timing diagram demonstrates Sync Master mode with bit SREN 1 and bit BRGH 0 RC6TXCK pin pin TXCKP 0 TXCKP 1 PIC18F2420252044204520 DS39631Epage 220 2008 Microchip Technology Inc 184 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit CSRC TXSTA7 This mode differs from the Synchronous Master mode in that the shift clock is sup plied externally at the CK pin instead of being supplied internally in Master mode This allows the device to transfer or receive data while in any lowpower mode 1841 EUSART SYNCHRONOUS SLAVE TRANSMISSION The operation of the Synchronous Master and Slave modes is identical except in the case of the Sleep mode If two words are written to the TXREG and then the SLEEP instruction is executed the following will occur a The first word will immediately transfer to the TSR register and transmit b The second word will remain in the TXREG register c Flag bit TXIF will not be set d When the first word has been shifted out of TSR the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set e If enable bit TXIE is set the interrupt will wake the chip from Sleep If the global interrupt is enabled the program will branch to the interrupt vector To set up a Synchronous Slave Transmission 1 Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC 2 Clear bits CREN and SREN 3 If interrupts are desired set enable bit TXIE 4 If 9bit transmission is desired set bit TX9 5 Enable the transmission by setting enable bit TXEN 6 If 9bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Start transmission by loading data to the TXREG register 8 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON76 are set TABLE 189 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 TXREG EUSART Transmit Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend unimplemented read as 0 Shaded cells are not used for synchronous slave transmission Note 1 Reserved in 28pin devices always maintain these bits clear 2008 Microchip Technology Inc DS39631Epage 221 PIC18F2420252044204520 1842 EUSART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode and bit SREN which is a dont care in Slave mode If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode then a word may be received while in this lowpower mode Once the word is received the RSR register will transfer the data to the RCREG register if the RCIE enable bit is set the inter rupt generated will wake the chip from the lowpower mode If the global interrupt is enabled the program will branch to the interrupt vector To set up a Synchronous Slave Reception 1 Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC 2 If interrupts are desired set enable bit RCIE 3 If 9bit reception is desired set bit RX9 4 To enable reception set enable bit CREN 5 Flag bit RCIF will be set when reception is complete An interrupt will be generated if enable bit RCIE was set 6 Read the RCSTA register to get the 9th bit if enabled and determine if any error occurred during reception 7 Read the 8bit received data by reading the RCREG register 8 If any error occurred clear the error by clearing bit CREN 9 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON76 are set TABLE 1810 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCREG EUSART Receive Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend unimplemented read as 0 Shaded cells are not used for synchronous slave reception Note 1 Reserved in 28pin devices always maintain these bits clear PIC18F2420252044204520 DS39631Epage 222 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 223 PIC18F2420252044204520 190 10BIT ANALOGTODIGITAL CONVERTER AD MODULE The AnalogtoDigital AD Converter module has 10 inputs for the 28pin devices and 13 for the 4044pin devices This module allows conversion of an analog input signal to a corresponding 10bit digital number The module has five registers AD Result High Register ADRESH AD Result Low Register ADRESL AD Control Register 0 ADCON0 AD Control Register 1 ADCON1 AD Control Register 2 ADCON2 The ADCON0 register shown in Register 191 controls the operation of the AD module The ADCON1 register shown in Register 192 configures the functions of the port pins The ADCON2 register shown in Register 193 configures the AD clock source programmed acquisition time and justification REGISTER 191 ADCON0 AD CONTROL REGISTER 0 U0 U0 RW0 RW0 RW0 RW0 RW0 RW0 CHS3 CHS2 CHS1 CHS0 GODONE ADON bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 76 Unimplemented Read as 0 bit 52 CHS30 Analog Channel Select bits 0000 Channel 0 AN0 0001 Channel 1 AN1 0010 Channel 2 AN2 0011 Channel 3 AN3 0100 Channel 4 AN4 0101 Channel 5 AN512 0110 Channel 6 AN612 0111 Channel 7 AN712 1000 Channel 8 AN8 1001 Channel 9 AN9 1010 Channel 10 AN10 1011 Channel 11 AN11 1100 Channel 12 AN12 1101 Unimplemented2 1110 Unimplemented2 1111 Unimplemented2 bit 1 GODONE AD Conversion Status bit When ADON 1 1 AD conversion in progress 0 AD Idle bit 0 ADON AD On bit 1 AD Converter module is enabled 0 AD Converter module is disabled Note 1 These channels are not implemented on 28pin devices 2 Performing a conversion on unimplemented channels will return a floating input measurement PIC18F2420252044204520 DS39631Epage 224 2008 Microchip Technology Inc REGISTER 192 ADCON1 AD CONTROL REGISTER 1 U0 U0 RW0 RW0 RW0 RWq1 RWq1 RWq1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 76 Unimplemented Read as 0 bit 5 VCFG1 Voltage Reference Configuration bit VREF source 1 VREF AN2 0 VSS bit 4 VCFG0 Voltage Reference Configuration bit VREF source 1 VREF AN3 0 VDD bit 30 PCFG30 AD Port Configuration Control bits Note 1 The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit When PBADEN 1 PCFG20 000 when PBADEN 0 PCFG20 111 2 AN5 through AN7 are available only on 4044pin devices A Analog input D Digital IO PCFG3 PCFG0 AN12 AN11 AN10 AN9 AN8 AN72 AN62 AN52 AN4 AN3 AN2 AN1 AN0 00001 A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 01111 D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D 2008 Microchip Technology Inc DS39631Epage 225 PIC18F2420252044204520 REGISTER 193 ADCON2 AD CONTROL REGISTER 2 RW0 U0 RW0 RW0 RW0 RW0 RW0 RW0 ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 ADFM AD Result Format Select bit 1 Right justified 0 Left justified bit 6 Unimplemented Read as 0 bit 53 ACQT20 AD Acquisition Time Select bits 111 20 TAD 110 16 TAD 101 12 TAD 100 8 TAD 011 6 TAD 010 4 TAD 001 2 TAD 000 0 TAD1 bit 20 ADCS20 AD Conversion Clock Select bits 111 FRC clock derived from AD RC oscillator1 110 FOSC64 101 FOSC16 100 FOSC4 011 FRC clock derived from AD RC oscillator1 010 FOSC32 001 FOSC8 000 FOSC2 Note 1 If the AD FRC clock source is selected a delay of one TCY instruction cycle is added before the AD clock starts This allows the SLEEP instruction to be executed before starting a conversion PIC18F2420252044204520 DS39631Epage 226 2008 Microchip Technology Inc The analog reference voltage is software selectable to either the devices positive and negative supply voltage VDD and VSS or the voltage level on the RA3AN3 VREF and RA2AN2VREFCVREF pins The AD Converter has a unique feature of being able to operate while the device is in Sleep mode To oper ate in Sleep the AD conversion clock must be derived from the ADs internal RC oscillator The output of the sample and hold is the input into the converter which generates the result via successive approximation A device Reset forces all registers to their Reset state This forces the AD module to be turned off and any conversion in progress is aborted Each port pin associated with the AD Converter can be configured as an analog input or as a digital IO The ADRESH and ADRESL registers contain the result of the AD conversion When the AD conversion is complete the result is loaded into the ADRESHADRESL register pair the GODONE bit ADCON0 register is cleared and the AD Interrupt Flag bit ADIF is set The block diagram of the AD module is shown in Figure 191 FIGURE 191 AD BLOCK DIAGRAM Input Voltage VAIN VREF Reference Voltage VDD2 VCFG10 CHS30 AN71 AN61 AN51 AN4 AN3 AN2 AN1 AN0 0111 0110 0101 0100 0011 0010 0001 0000 10Bit AD VREF VSS2 Converter AN12 AN11 AN10 AN9 AN8 1100 1011 1010 1001 1000 Note 1 Channels AN5 through AN7 are not available on 28pin devices 2 IO pins have diode protection to VDD and VSS 0X 1X X1 X0 2008 Microchip Technology Inc DS39631Epage 227 PIC18F2420252044204520 The value in the ADRESHADRESL registers is not modified for a Poweron Reset The ADRESHADRESL registers will contain unknown data after a Poweron Reset After the AD module has been configured as desired the selected channel must be acquired before the conversion is started The analog input channels must have their corresponding TRIS bits selected as an input To determine acquisition time see Section 191 AD Acquisition Requirements After this acquisi tion time has elapsed the AD conversion can be started An acquisition time can be programmed to occur between setting the GODONE bit and the actual start of the conversion The following steps should be followed to perform an AD conversion 1 Configure the AD module Configure analog pins voltage reference and digital IO ADCON1 Select AD input channel ADCON0 Select AD acquisition time ADCON2 Select AD conversion clock ADCON2 Turn on AD module ADCON0 2 Configure AD interrupt if desired Clear ADIF bit Set ADIE bit Set GIE bit 3 Wait the required acquisition time if required 4 Start conversion Set GODONE bit ADCON0 register 5 Wait for AD conversion to complete by either Polling for the GODONE bit to be cleared OR Waiting for the AD interrupt 6 Read AD Result registers ADRESHADRESL clear bit ADIF if required 7 For next conversion go to step 1 or step 2 as required The AD conversion time per bit is defined as TAD A minimum wait of 2 TAD is required before the next acquisition starts FIGURE 192 AD TRANSFER FUNCTION FIGURE 193 ANALOG INPUT MODEL Digital Code Output 3FEh 003h 002h 001h 000h 05 LSB 1 LSB 15 LSB 2 LSB 25 LSB 1022 LSB 10225 LSB 3 LSB Analog Input Voltage 3FFh 1023 LSB 10235 LSB VAIN CPIN Rs ANx 5 pF VT 06V VT 06V ILEAKAGE RIC 1k Sampling Switch SS RSS CHOLD 25 pF VSS VDD 100 nA Legend CPIN VT ILEAKAGE RIC SS CHOLD Input Capacitance Threshold Voltage Leakage Current at the pin due to Interconnect Resistance Sampling Switch SampleHold Capacitance from DAC various junctions Sampling Switch Resistance RSS VDD 6V Sampling Switch 5V 4V 3V 2V 1 2 3 4 kΩ PIC18F2420252044204520 DS39631Epage 228 2008 Microchip Technology Inc 191 AD Acquisition Requirements For the AD Converter to meet its specified accuracy the charge holding capacitor CHOLD must be allowed to fully charge to the input channel voltage level The analog input model is shown in Figure 193 The source impedance RS and the internal sampling switch RSS impedance directly affect the time required to charge the capacitor CHOLD The sampling switch RSS impedance varies over the device voltage VDD The source impedance affects the offset voltage at the analog input due to pin leakage current The maximum recommended impedance for analog sources is 25 kΩ After the analog input channel is selected changed the channel must be sampled for at least the minimum acquisition time before starting a conversion To calculate the minimum acquisition time Equation 191 may be used This equation assumes that 12 LSb error is used 1024 steps for the AD The 12 LSb error is the maximum error allowed for the AD to meet its specified resolution Example 193 shows the calculation of the minimum required acquisition time TACQ This calculation is based on the following application system assumptions CHOLD 25 pF Rs 25 kΩ Conversion Error 12 LSb VDD 5V Rss 2 kΩ Temperature 85C system max EQUATION 191 ACQUISITION TIME EQUATION 192 AD MINIMUM CHARGING TIME EQUATION 193 CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME Note When the conversion is started the holding capacitor is disconnected from the input pin TACQ Amplifier Settling Time Holding Capacitor Charging Time Temperature Coefficient TAMP TC TCOFF VHOLD VREF VREF2048 1 eTCCHOLDRIC RSS RS or TC CHOLDRIC RSS RS ln12048 TACQ TAMP TC TCOFF TAMP 02 μs TCOFF Temp 25C002 μsC 85C 25C002 μsC 12 μs Temperature coefficient is only required for temperatures 25C Below 25C TCOFF 0 μs TC CHOLDRIC RSS RS ln12047 μs 25 pF 1 kΩ 2 kΩ 25 kΩ ln00004883 μs 105 μs TACQ 02 μs 1 μs 12 μs 24 μs 2008 Microchip Technology Inc DS39631Epage 229 PIC18F2420252044204520 192 Selecting and Configuring Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GODONE bit is set It also gives users the option to use an automatically determined acquisition time Acquisition time may be set with the ACQT20 bits ADCON253 which provides a range of 2 to 20 TAD When the GODONE bit is set the AD module continues to sample the input for the selected acquisi tion time then automatically begins a conversion Since the acquisition time is programmed there may be no need to wait for an acquisition time between selecting a channel and setting the GODONE bit Manual acquisition is selected when ACQT20 000 When the GODONE bit is set sampling is stopped and a conversion begins The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GODONE bit This option is also the default Reset state of the ACQT20 bits and is compatible with devices that do not offer programmable acquisition times In either case when the conversion is completed the GODONE bit is cleared the ADIF flag is set and the AD begins sampling the currently selected channel again If an acquisition time is programmed there is nothing to indicate if the acquisition time has ended or if the conversion has begun 193 Selecting the AD Conversion Clock The AD conversion time per bit is defined as TAD The AD conversion requires 11 TAD per 10bit conversion The source of the AD conversion clock is software selectable There are seven possible options for TAD 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator For correct AD conversions the AD conversion clock TAD must be as short as possible but greater than the minimum TAD see parameter 130 for more information Table 191 shows the resultant TAD times derived from the device operating frequencies and the AD clock source selected TABLE 191 TAD vs DEVICE OPERATING FREQUENCIES AD Clock Source TAD Maximum Device Frequency Operation ADCS20 PIC18F2X204X20 PIC18LF2X2X4X204 2 TOSC 000 286 MHz 143 kHz 4 TOSC 100 571 MHz 286 MHz 8 TOSC 001 1143 MHz 572 MHz 16 TOSC 101 2286 MHz 1143 MHz 32 TOSC 010 400 MHz 2286 MHz 64 TOSC 110 400 MHz 2286 MHz RC3 x11 100 MHz1 100 MHz2 Note 1 The RC source has a typical TAD time of 12 μs 2 The RC source has a typical TAD time of 25 μs 3 For device frequencies above 1 MHz the device must be in Sleep for the entire conversion or the AD accuracy may be out of specification 4 Lowpower PIC18LFXXXX devices only PIC18F2420252044204520 DS39631Epage 230 2008 Microchip Technology Inc 194 Operation in PowerManaged Modes The selection of the automatic acquisition time and AD conversion clock is determined in part by the clock source and frequency while in a powermanaged mode If the AD is expected to operate while the device is in a powermanaged mode the ACQT20 and ADCS20 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode After entering the mode an AD acquisition or conversion may be started Once started the device should continue to be clocked by the same clock source until the conversion has been completed If desired the device may be placed into the corresponding Idle mode during the conversion If the device clock frequency is less than 1 MHz the AD RC clock source should be selected Operation in Sleep mode requires the AD FRC clock to be selected If the ACQT20 bits are set to 000 and a conversion is started the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode The IDLEN bit OSCCON7 must have already been cleared prior to starting the conversion 195 Configuring Analog Port Pins The ADCON1 TRISA TRISB and TRISE registers all configure the AD port pins The port pins needed as analog inputs must have their corresponding TRIS bits set input If the TRIS bit is cleared output the digital output level VOH or VOL will be converted The AD operation is independent of the state of the CHS30 bits and the TRIS bits Note 1 When reading the PORT register all pins configured as analog input channels will read as cleared a low level Pins con figured as digital inputs will convert as analog inputs Analog levels on a digitally configured input will be accurately converted 2 Analog levels on any pin defined as a dig ital input may cause the digital input buffer to consume current out of the devices specification limits 3 The PBADEN bit in Configuration Register 3H configures PORTB pins to reset as analog or digital pins by control ling how the PCFG bits in ADCON1 are reset 2008 Microchip Technology Inc DS39631Epage 231 PIC18F2420252044204520 196 AD Conversions Figure 194 shows the operation of the AD Converter after the GODONE bit has been set and the ACQT20 bits are cleared A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins Figure 195 shows the operation of the AD Converter after the GODONE bit has been set and the ACQT20 bits are set to 010 and selecting a 4 TAD acquisition time before the conversion starts Clearing the GODONE bit during a conversion will abort the current conversion The AD Result register pair will NOT be updated with the partially completed AD conversion sample This means the ADRESHADRESL registers will continue to contain the value of the last completed conversion or the last value written to the ADRESHADRESL registers After the AD conversion is completed or aborted a 2 TAD wait is required before the next acquisition can be started After this wait acquisition on the selected channel is automatically started 197 Discharge The discharge phase is used to initialize the value of the capacitor array The array is discharged before every sample This feature helps to optimize the unity gain amplifier as the circuit always needs to charge the capacitor array rather than chargedischarge based on previous measure values FIGURE 194 AD CONVERSION TAD CYCLES ACQT20 000 TACQ 0 FIGURE 195 AD CONVERSION TAD CYCLES ACQT20 010 TACQ 4 TAD Note The GODONE bit should NOT be set in the same instruction that turns on the AD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11 Set GODONE bit Holding capacitor is disconnected from analog input typically 100 ns TAD9 TAD10 TCY TAD ADRESHADRESL are loaded GODONE bit is cleared ADIF bit is set holding capacitor is connected to analog input Conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 On the following cycle TAD1 Discharge 1 2 3 4 5 6 7 8 11 Set GODONE bit Holding capacitor is disconnected 9 10 Conversion starts 1 2 3 4 Holding capacitor continues acquiring input TACQT Cycles TAD Cycles Automatic Acquisition Time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 ADRESHADRESL are loaded GODONE bit is cleared ADIF bit is set holding capacitor is connected to analog input On the following cycle TAD1 Discharge PIC18F2420252044204520 DS39631Epage 232 2008 Microchip Technology Inc 198 Use of the CCP2 Trigger An AD conversion can be started by the Special Event Trigger of the CCP2 module This requires that the CCP2M30 bits CCP2CON30 be programmed as 1011 and that the AD module is enabled ADON bit is set When the trigger occurs the GODONE bit will be set starting the AD acquisition and conversion and the Timer1 or Timer3 counter will be reset to zero Timer1 or Timer3 is reset to automatically repeat the AD acquisition period with minimal software overhead moving ADRESHADRESL to the desired location The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user or an appropriate TACQ time is selected before the Special Event Trigger sets the GODONE bit starts a conversion If the AD module is not enabled ADON is cleared the Special Event Trigger will be ignored by the AD module but will still reset the Timer1 or Timer3 counter TABLE 192 REGISTERS ASSOCIATED WITH AD OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 ADRESH AD Result Register High Byte 51 ADRESL AD Result Register Low Byte 51 ADCON0 CHS3 CHS2 CHS1 CHS0 GODONE ADON 51 ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 ADCON2 ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 51 PORTA RA72 RA62 RA5 RA4 RA3 RA2 RA1 RA0 52 TRISA TRISA72 TRISA62 PORTA Data Direction Register 52 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 TRISB PORTB Data Direction Register 52 LATB PORTB Data Latch Register Read and Write to Data Latch 52 PORTE4 RE33 RE2 RE1 RE0 52 TRISE4 IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 52 LATE4 PORTE Data Latch Register 52 Legend unimplemented read as 0 Shaded cells are not used for AD conversion Note 1 These bits are unimplemented on 28pin devices always maintain these bits clear 2 PORTA76 and their direction bits are individually configured as port pins based on various primary oscillator modes When disabled these bits read as 0 3 RE3 port bit is available only as an input pin when the MCLRE Configuration bit is 0 4 These registers are not implemented on 28pin devices 2008 Microchip Technology Inc DS39631Epage 233 PIC18F2420252044204520 200 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5 as well as the onchip voltage reference see Section 210 Comparator Voltage Reference Module The digi tal outputs normal or inverted are available at the pin level and can also be read through the control register The CMCON register Register 201 selects the comparator input and output configuration Block diagrams of the various comparator configurations are shown in Figure 201 REGISTER 201 CMCON COMPARATOR CONTROL REGISTER R0 R0 RW0 RW0 RW0 RW1 RW1 RW1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 C2OUT Comparator 2 Output bit When C2INV 0 1 C2 VIN C2 VIN 0 C2 VIN C2 VIN When C2INV 1 1 C2 VIN C2 VIN 0 C2 VIN C2 VIN bit 6 C1OUT Comparator 1 Output bit When C1INV 0 1 C1 VIN C1 VIN 0 C1 VIN C1 VIN When C1INV 1 1 C1 VIN C1 VIN 0 C1 VIN C1 VIN bit 5 C2INV Comparator 2 Output Inversion bit 1 C2 output inverted 0 C2 output not inverted bit 4 C1INV Comparator 1 Output Inversion bit 1 C1 output inverted 0 C1 output not inverted bit 3 CIS Comparator Input Switch bit When CM20 110 1 C1 VIN connects to RA3AN3VREF C2 VIN connects to RA2AN2VREFCVREF 0 C1 VIN connects to RA0AN0 C2 VIN connects to RA1AN1 bit 20 CM20 Comparator Mode bits Figure 201 shows the Comparator modes and the CM20 bit settings PIC18F2420252044204520 DS39631Epage 234 2008 Microchip Technology Inc 201 Comparator Configuration There are eight modes of operation for the compara tors shown in Figure 201 Bits CM20 of the CMCON register are used to select these modes The TRISA register controls the data direction of the com parator pins for each mode If the Comparator mode is changed the comparator output level may not be valid for the specified mode change delay shown in Section 260 Electrical Characteristics FIGURE 201 COMPARATOR IO OPERATING MODES Note Comparator interrupts should be disabled during a Comparator mode change otherwise a false interrupt may occur C1 RA0AN0 VIN VIN RA3AN3 Off Read as 0 Comparators Reset A A CM20 000 C2 RA1AN1 VIN VIN RA2AN2 Off Read as 0 A A C1 VIN VIN C1OUT Two Independent Comparators A A CM20 010 C2 VIN VIN C2OUT A A C1 VIN VIN C1OUT Two Common Reference Comparators A A CM20 100 C2 VIN VIN C2OUT A D C2 VIN VIN Off Read as 0 One Independent Comparator with Output D D CM20 001 C1 VIN VIN C1OUT A A C1 VIN VIN Off Read as 0 Comparators Off POR Default Value D D CM20 111 C2 VIN VIN Off Read as 0 D D C1 VIN VIN C1OUT Four Inputs Multiplexed to Two Comparators A A CM20 110 C2 VIN VIN C2OUT A A From VREF Module CIS 0 CIS 1 CIS 0 CIS 1 C1 VIN VIN C1OUT Two Common Reference Comparators with Outputs A A CM20 101 C2 VIN VIN C2OUT A D A Analog Input port reads zeros always D Digital Input CIS CMCON3 is the Comparator Input Switch CVREF C1 VIN VIN C1OUT Two Independent Comparators with Outputs A A CM20 011 C2 VIN VIN C2OUT A A RA5AN4SSHLVDINC2OUT RA4T0CKIC1OUT VREF VREFCVREF RA0AN0 RA3AN3 RA1AN1 RA2AN2 VREF VREFCVREF RA0AN0 RA3AN3 RA1AN1 RA2AN2 VREF VREFCVREF RA0AN0 RA3AN3 RA1AN1 RA2AN2 VREF VREFCVREF RA0AN0 RA3AN3 RA1AN1 RA2AN2 VREF VREFCVREF RA0AN0 RA3AN3 RA1AN1 RA2AN2 VREF VREFCVREF RA0AN0 RA3AN3 VREF RA1AN1 RA2AN2 VREFCVREF RA4T0CKIC1OUT RA5AN4SSHLVDINC2OUT RA0AN0 RA3AN3 VREF RA1AN1 RA2AN2 VREFCVREF RA4T0CKIC1OUT Setting the TRISA54 bits will disable the comparator outputs by configuring the pins as inputs 2008 Microchip Technology Inc DS39631Epage 235 PIC18F2420252044204520 202 Comparator Operation A single comparator is shown in Figure 202 along with the relationship between the analog input levels and the digital output When the analog input at VIN is less than the analog input VIN the output of the comparator is a digital low level When the analog input at VIN is greater than the analog input VIN the output of the comparator is a digital high level The shaded areas of the output of the comparator in Figure 202 represent the uncertainty due to input offsets and response time 203 Comparator Reference Depending on the comparator operating mode either an external or internal voltage reference may be used The analog signal present at VIN is compared to the signal at VIN and the digital output of the comparator is adjusted accordingly Figure 202 FIGURE 202 SINGLE COMPARATOR 2031 EXTERNAL REFERENCE SIGNAL When external voltage references are used the comparator module can be configured to have the com parators operate from the same or different reference sources However threshold detector applications may require the same reference The reference signal must be between VSS and VDD and can be applied to either pin of the comparators 2032 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module This module is described in more detail in Section 210 Comparator Voltage Reference Module The internal reference is only available in the mode where four inputs are multiplexed to two comparators CM20 110 In this mode the internal voltage reference is applied to the VIN pin of both comparators 204 Comparator Response Time Response time is the minimum time after selecting a new reference voltage or input source before the comparator output has a valid level If the internal ref erence is changed the maximum delay of the internal voltage reference must be considered when using the comparator outputs Otherwise the maximum delay of the comparators should be used see Section 260 Electrical Characteristics 205 Comparator Outputs The comparator outputs are read through the CMCON register These bits are readonly The comparator outputs may also be directly output to the RA4 and RA5 IO pins When enabled multiplexers in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications Figure 203 shows the comparator output block diagram The TRISA bits will still function as an output enable disable for the RA4 and RA5 pins while in this mode The polarity of the comparator outputs can be changed using the C2INV and C1INV bits CMCON45 VIN VIN Output Output VIN VIN Note 1 When reading the PORT register all pins configured as analog inputs will read as 0 Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification 2 Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified PIC18F2420252044204520 DS39631Epage 236 2008 Microchip Technology Inc FIGURE 203 COMPARATOR OUTPUT BLOCK DIAGRAM 206 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator Software will need to maintain information about the status of the output bits as read from CMCON76 to determine the actual change that occurred The CMIF bit PIR26 is the Comparator Interrupt Flag The CMIF bit must be reset by clearing it Since it is also possible to write a 1 to this register a simulated interrupt may be initiated Both the CMIE bit PIE26 and the PEIE bit INTCON6 must be set to enable the interrupt In addition the GIE bit INTCON7 must also be set If any of these bits are clear the interrupt is not enabled though the CMIF bit will still be set if an interrupt condition occurs The user in the Interrupt Service Routine can clear the interrupt in the following manner a Any read or write of CMCON will end the mismatch condition b Clear flag bit CMIF A mismatch condition will continue to set flag bit CMIF Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared 207 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode the comparator remains active and the interrupt is functional if enabled This interrupt will wakeup the device from Sleep mode when enabled Each operational comparator will consume additional current as shown in the comparator specifications To minimize power consumption while in Sleep mode turn off the comparators CM20 111 before entering Sleep If the device wakes up from Sleep the contents of the CMCON register are not affected 208 Effects of a Reset A device Reset forces the CMCON register to its Reset state causing the comparator modules to be turned off CM20 111 However the input pins RA0 through RA3 are configured as analog inputs by default on device Reset The IO configuration for these pins is determined by the setting of the PCFG30 bits ADCON130 Therefore device current is minimized when analog inputs are present at Reset time D Q EN To RA4 or RA5 pin Bus Data Set MULTIPLEX CMIF bit Port pins Read CMCON Reset From Other Comparator CxINV D Q EN CL Note If a change in the CMCON register C1OUT or C2OUT should occur when a read operation is being executed start of the Q2 cycle then the CMIF PIR26 interrupt flag may not get set 2008 Microchip Technology Inc DS39631Epage 237 PIC18F2420252044204520 209 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 204 Since the analog pins are connected to a digital output they have reverse biased diodes to VDD and VSS The analog input therefore must be between VSS and VDD If the input voltage deviates from this range by more than 06V in either direction one of the diodes is forward biased and a latchup condition may occur A maximum source impedance of 10 kΩ is recommended for the analog sources Any external component connected to an analog input pin such as a capacitor or a Zener diode should have very little leakage current FIGURE 204 COMPARATOR ANALOG INPUT MODEL TABLE 201 REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 52 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 PORTA RA71 RA61 RA5 RA4 RA3 RA2 RA1 RA0 52 LATA LATA71 LATA61 PORTA Data Latch Register Read and Write to Data Latch 52 TRISA TRISA71 TRISA61 PORTA Data Direction Register 52 Legend unimplemented read as 0 Shaded cells are unused by the comparator module Note 1 PORTA76 and their direction and latch bits are individually configured as port pins based on various primary oscillator modes When disabled these bits are read as 0 VA RS 10k AIN CPIN 5 pF VDD VT 06V VT 06V RIC ILEAKAGE 100 nA VSS Legend CPIN Input Capacitance VT Threshold Voltage ILEAKAGE Leakage Current at the pin due to various junctions RIC Interconnect Resistance RS Source Impedance VA Analog Voltage Comparator Input PIC18F2420252044204520 DS39631Epage 238 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 239 PIC18F2420252044204520 210 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16tap resistor ladder network that provides a selectable reference voltage Although its primary purpose is to provide a reference for the analog comparators it may also be used independently of them A block diagram of the module is shown in Figure 211 The resistor ladder is segmented to provide two ranges of CVREF values and has a powerdown function to conserve power when the reference is not being used The modules supply reference can be provided from either device VDDVSS or an external voltage reference 211 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register Register 211 The comparator voltage reference provides two ranges of output volt age each with 16 distinct levels The range to be used is selected by the CVRR bit CVRCON5 The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits CVR30 with one range offering finer resolution The equations used to calculate the output of the comparator voltage reference are as follows If CVRR 1 CVREF CVR3024 x CVRSRC If CVRR 0 CVREF CVRSRC x 14 CVR3032 x CVRSRC The comparator reference supply voltage can come from either VDD and VSS or the external VREF and VREF that are multiplexed with RA2 and RA3 The voltage source is selected by the CVRSS bit CVRCON4 The settling time of the comparator voltage reference must be considered when changing the CVREF out put see Table 263 in Section 260 Electrical Characteristics REGISTER 211 CVRCON COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 CVREN CVROE1 CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 CVREN Comparator Voltage Reference Enable bit 1 CVREF circuit powered on 0 CVREF circuit powered down bit 6 CVROE Comparator VREF Output Enable bit1 1 CVREF voltage level is also output on the RA2AN2VREFCVREF pin 0 CVREF voltage is disconnected from the RA2AN2VREFCVREF pin bit 5 CVRR Comparator VREF Range Selection bit 1 0 to 0667 CVRSRC with CVRSRC24 step size low range 0 025 CVRSRC to 075 CVRSRC with CVRSRC32 step size high range bit 4 CVRSS Comparator VREF Source Selection bit 1 Comparator reference source CVRSRC VREF VREF 0 Comparator reference source CVRSRC VDD VSS bit 30 CVR3CVR0 Comparator VREF Value Selection bits 0 CVR30 15 When CVRR 1 CVREF CVR3024 CVRSRC When CVRR 0 CVREF CVRSRC4 CVR3032 CVRSRC Note 1 CVROE overrides the TRISA2 bit setting PIC18F2420252044204520 DS39631Epage 240 2008 Microchip Technology Inc FIGURE 211 COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 212 Voltage Reference AccuracyError The full range of voltage reference cannot be realized due to the construction of the module The transistors on the top and bottom of the resistor ladder network Figure 211 keep CVREF from approaching the refer ence source rails The voltage reference is derived from the reference source therefore the CVREF output changes with fluctuations in that source The tested absolute accuracy of the voltage reference can be found in Section 260 Electrical Characteristics 213 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer timeout the contents of the CVRCON register are not affected To minimize current consumption in Sleep mode the voltage reference should be disabled 214 Effects of a Reset A device Reset disables the voltage reference by clearing bit CVREN CVRCON7 This Reset also disconnects the reference from the RA2 pin by clearing bit CVROE CVRCON6 and selects the highvoltage range by clearing bit CVRR CVRCON5 The CVR value select bits are also cleared 215 Connection Considerations The voltage reference module operates independently of the comparator module The output of the reference generator may be connected to the RA2 pin if the CVROE bit is set Enabling the voltage reference out put onto RA2 when it is configured as a digital input will increase current consumption Connecting RA2 as a digital output with CVRSS enabled will also increase current consumption The RA2 pin can be used as a simple DA output with limited drive capability Due to the limited current drive capability a buffer must be used on the voltage reference output for external connections to VREF Figure 212 shows an example buffering technique 16to1 MUX CVR30 8R R CVREN CVRSS 0 VDD VREF CVRSS 1 8R CVRSS 0 VREF CVRSS 1 R R R R R R 16 Steps CVRR CVREF 2008 Microchip Technology Inc DS39631Epage 241 PIC18F2420252044204520 FIGURE 212 COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE TABLE 211 REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 TRISA TRISA71 TRISA61 PORTA Data Direction Register 52 Legend Shaded cells are not used with the comparator voltage reference Note 1 PORTA pins are enabled based on oscillator configuration CVREF Output CVREF Module Voltage Reference Output Impedance R1 RA2 Note 1 R is dependent upon the comparator voltage reference configuration bits CVRCON30 and CVRCON5 PIC18FXXXX PIC18F2420252044204520 DS39631Epage 242 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc Advance Information DS39631Epage 243 PIC18F2420252044204520 220 HIGHLOWVOLTAGE DETECT HLVD PIC18F2420252044204520 devices have a HighLowVoltage Detect module HLVD This is a pro grammable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point If the device experiences an excursion past the trip point in that direction an interrupt flag is set If the interrupt is enabled the program execution will branch to the interrupt vector address and the software can then respond to the interrupt The HighLowVoltage Detect Control register Register 221 completely controls the operation of the HLVD module This allows the circuitry to be turned off by the user under software control which minimizes the current consumption for the device The block diagram for the HLVD module is shown in Figure 221 REGISTER 221 HLVDCON HIGHLOWVOLTAGE DETECT CONTROL REGISTER RW0 U0 R0 RW0 RW0 RW1 RW0 RW1 VDIRMAG IRVST HLVDEN HLVDL31 HLVDL21 HLVDL11 HLVDL01 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 VDIRMAG Voltage Direction Magnitude Select bit 1 Event occurs when voltage equals or exceeds trip point HLVDL30 0 Event occurs when voltage equals or falls below trip point HLVDL30 bit 6 Unimplemented Read as 0 bit 5 IRVST Internal Reference Voltage Stable Flag bit 1 Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN HighLowVoltage Detect Power Enable bit 1 HLVD enabled 0 HLVD disabled bit 30 HLVDL30 Voltage Detection Limit bits1 1111 External analog input is used input comes from the HLVDIN pin 1110 Maximum setting 0000 Minimum setting Note 1 See Table 264 for specifications PIC18F2420252044204520 DS39631Epage 244 Advance Information 2008 Microchip Technology Inc The module is enabled by setting the HLVDEN bit Each time that the HLVD module is enabled the cir cuitry requires some time to stabilize The IRVST bit is a readonly bit and is used to indicate when the circuit is stable The module can only generate an interrupt after the circuit is stable and IRVST is set The VDIRMAG bit determines the overall operation of the module When VDIRMAG is cleared the module monitors for drops in VDD below a predetermined set point When the bit is set the module monitors for rises in VDD above the set point 221 Operation When the HLVD module is enabled a comparator uses an internally generated reference voltage as the set point The set point is compared with the trip point where each node in the resistor divider represents a trip point voltage The trip point voltage is the voltage level at which the device detects a high or lowvoltage event depending on the configuration of the module When the supply voltage is equal to the trip point the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module The comparator then generates an interrupt signal by setting the HLVDIF bit The trip point voltage is software programmable to any one of 16 values The trip point is selected by programming the HLVDL30 bits HLVDCON30 The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source This mode is enabled when bits HLVDL30 are set to 1111 In this state the comparator input is multiplexed from the external input pin HLVDIN This gives users flexibility because it allows them to configure the HighLowVoltage Detect interrupt to occur at any voltage in the valid operating range FIGURE 221 HLVD MODULE BLOCK DIAGRAM WITH EXTERNAL INPUT Set VDD 16to1 MUX HLVDEN HLVDCON HLVDIN HLVDL30 Register HLVDIN VDD Externally Generated Trip Point HLVDIF HLVDEN BOREN Internal Voltage Reference VDIRMAG 2008 Microchip Technology Inc Advance Information DS39631Epage 245 PIC18F2420252044204520 222 HLVD Setup The following steps are needed to set up the HLVD module 1 Write the value to the HLVDL30 bits that selects the desired HLVD trip point 2 Set the VDIRMAG bit to detect high voltage VDIRMAG 1 or low voltage VDIRMAG 0 3 Enable the HLVD module by setting the HLVDEN bit 4 Clear the HLVD interrupt flag PIR22 which may have been set from a previous interrupt 5 Enable the HLVD interrupt if interrupts are desired by setting the HLVDIE and GIE bits PIE22 and INTCON7 An interrupt will not be generated until the IRVST bit is set 223 Current Consumption When the module is enabled the HLVD comparator and voltage divider are enabled and will consume static current The total current consumption when enabled is specified in electrical specification parameter D022B Depending on the application the HLVD module does not need to be operating constantly To decrease the current requirements the HLVD circuitry may only need to be enabled for short periods where the voltage is checked After doing the check the HLVD module may be disabled 224 HLVD Startup Time The internal reference voltage of the HLVD module specified in electrical specification parameter D420 may be used by other internal circuitry such as the programmable Brownout Reset If the HLVD or other circuits using the voltage reference are disabled to lower the devices current consumption the reference voltage circuit will require time to become stable before a low or highvoltage condition can be reliably detected This startup time TIRVST is an interval that is independent of device clock speed It is specified in electrical specification parameter 36 The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached For this reason brief excursions beyond the set point may not be detected during this interval refer to Figure 222 or Figure 223 FIGURE 222 LOWVOLTAGE DETECT OPERATION VDIRMAG 0 VLVD VDD HLVDIF VLVD VDD Enable HLVD TIRVST HLVDIF may not be set Enable HLVD HLVDIF HLVDIF Cleared in Software HLVDIF Cleared in Software HLVDIF cleared in software CASE 1 CASE 2 HLVDIF remains set since HLVD condition still exists TIRVST Internal Reference is Stable Internal Reference is Stable IRVST IRVST PIC18F2420252044204520 DS39631Epage 246 Advance Information 2008 Microchip Technology Inc FIGURE 223 HIGHVOLTAGE DETECT OPERATION VDIRMAG 1 225 Applications In many applications the ability to detect a drop below or rise above a particular threshold is desirable For example the HLVD module could be periodically enabled to detect Universal Serial Bus USB attach or detach This assumes the device is powered by a lower voltage source than the USB when detached An attach would indicate a highvoltage detect from for example 33V to 5V the voltage on USB and vice versa for a detach This feature could save a design a few extra components and an attach signal input pin For general battery applications Figure 224 shows a possible voltage curve Over time the device voltage decreases When the device voltage reaches voltage VA the HLVD logic generates an interrupt at time TA The interrupt could cause the execution of an ISR which would allow the application to perform house keeping tasks and perform a controlled shutdown before the device voltage exits the valid operating range at TB The HLVD thus would give the applica tion a time window represented by the difference between TA and TB to safely exit FIGURE 224 TYPICAL LOWVOLTAGE DETECT APPLICATION VLVD VDD HLVDIF VLVD VDD Enable HLVD TIRVST HLVDIF may not be set Enable HLVD HLVDIF HLVDIF Cleared in Software HLVDIF Cleared in Software HLVDIF cleared in software CASE 1 CASE 2 HLVDIF remains set since HLVD condition still exists TIRVST IRVST Internal Reference is Stable Internal Reference is Stable IRVST Time Voltage VA VB TA TB VA HLVD trip point VB Minimum valid device operating voltage Legend 2008 Microchip Technology Inc Advance Information DS39631Epage 247 PIC18F2420252044204520 226 Operation During Sleep When enabled the HLVD circuitry continues to operate during Sleep If the device voltage crosses the trip point the HLVDIF bit will be set and the device will wakeup from Sleep Device execution will continue from the interrupt vector address if interrupts have been globally enabled 227 Effects of a Reset A device Reset forces all registers to their Reset state This forces the HLVD module to be turned off TABLE 221 REGISTERS ASSOCIATED WITH HIGHLOWVOLTAGE DETECT MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page HLVDCON VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 50 INTCON GIEGIEH PEIEGIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OCSFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 Legend unimplemented read as 0 Shaded cells are unused by the HLVD module PIC18F2420252044204520 DS39631Epage 248 Advance Information 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 249 PIC18F2420252044204520 230 SPECIAL FEATURES OF THE CPU PIC18F2420252044204520 devices include several features intended to maximize reliability and minimize cost through elimination of external components These are Oscillator Selection Resets Poweron Reset POR Powerup Timer PWRT Oscillator Startup Timer OST Brownout Reset BOR Interrupts Watchdog Timer WDT FailSafe Clock Monitor TwoSpeed Startup Code Protection ID Locations InCircuit Serial Programming The oscillator can be configured for the application depending on frequency power accuracy and cost All of the options are discussed in detail in Section 20 Oscillator Configurations A complete discussion of device Resets and interrupts is available in previous sections of this data sheet In addition to their Powerup and Oscillator Startup Timers provided for Resets PIC18F242025204420 4520 devices have a Watchdog Timer which is either permanently enabled via the Configuration bits or software controlled if configured as disabled The inclusion of an internal RC oscillator also provides the additional benefits of a FailSafe Clock Monitor FSCM and TwoSpeed Startup FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure Two Speed Startup enables code to be executed almost immediately on startup while the primary clock source completes its startup delays All of these features are enabled and configured by setting the appropriate Configuration register bits 231 Configuration Bits The Configuration bits can be programmed read as 0 or left unprogrammed read as 1 to select various device configurations These bits are mapped starting at program memory location 300000h The user will note that address 300000h is beyond the user program memory space In fact it belongs to the configuration memory space 300000h3FFFFFh which can only be accessed using table reads and table writes Programming the Configuration registers is done in a manner similar to programming the Flash memory The WR bit in the EECON1 register starts a selftimed write to the Configuration register In normal operation mode a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data for the Configuration register write Setting the WR bit starts a long write to the Configuration register The Configuration registers are written a byte at a time To write or erase a configuration cell a TBLWT instruction can write a 1 or a 0 into the cell For additional details on Flash programming refer to Section 65 Writing to Flash Program Memory TABLE 231 CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Unprogrammed Value 300001h CONFIG1H IESO FCMEN FOSC3 FOSC2 FOSC1 FOSC0 00 0111 300002h CONFIG2L BORV1 BORV0 BOREN1 BOREN0 PWRTEN 1 1111 300003h CONFIG2H WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 1 1111 300005h CONFIG3H MCLRE LPT1OSC PBADEN CCP2MX 1 011 300006h CONFIG4L DEBUG XINST LVP STVREN 10 11 300008h CONFIG5L CP31 CP21 CP1 CP0 1111 300009h CONFIG5H CPD CPB 11 30000Ah CONFIG6L WRT31 WRT21 WRT1 WRT0 1111 30000Bh CONFIG6H WRTD WRTB WRTC 111 30000Ch CONFIG7L EBTR31 EBTR21 EBTR1 EBTR0 1111 30000Dh CONFIG7H EBTRB 1 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx2 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx2 Legend x unknown u unchanged unimplemented q value depends on condition Shaded cells are unimplemented read as 0 Note 1 Unimplemented in PIC18F24204420 devices maintain this bit set 2 See Register 2312 for DEVID1 values DEVID registers are readonly and cannot be programmed by the user PIC18F2420252044204520 DS39631Epage 250 2008 Microchip Technology Inc REGISTER 231 CONFIG1H CONFIGURATION REGISTER 1 HIGH BYTE ADDRESS 300001h RP0 RP0 U0 U0 RP0 RP1 RP1 RP1 IESO FCMEN FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 IESO InternalExternal Oscillator Switchover bit 1 Oscillator Switchover mode enabled 0 Oscillator Switchover mode disabled bit 6 FCMEN FailSafe Clock Monitor Enable bit 1 FailSafe Clock Monitor enabled 0 FailSafe Clock Monitor disabled bit 54 Unimplemented Read as 0 bit 30 FOSC30 Oscillator Selection bits 11xx External RC oscillator CLKO function on RA6 101x External RC oscillator CLKO function on RA6 1001 Internal oscillator block CLKO function on RA6 port function on RA7 1000 Internal oscillator block port function on RA6 and RA7 0111 External RC oscillator port function on RA6 0110 HS oscillator PLL enabled Clock Frequency 4 x FOSC1 0101 EC oscillator port function on RA6 0100 EC oscillator CLKO function on RA6 0011 External RC oscillator CLKO function on RA6 0010 HS oscillator 0001 XT oscillator 0000 LP oscillator 2008 Microchip Technology Inc DS39631Epage 251 PIC18F2420252044204520 REGISTER 232 CONFIG2L CONFIGURATION REGISTER 2 LOW BYTE ADDRESS 300002h U0 U0 U0 RP1 RP1 RP1 RP1 RP1 BORV11 BORV01 BOREN12 BOREN02 PWRTEN2 bit 7 bit 0 Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 75 Unimplemented Read as 0 bit 43 BORV10 Brownout Reset Voltage bits1 11 Minimum setting 00 Maximum setting bit 21 BOREN10 Brownout Reset Enable bits2 11 Brownout Reset enabled in hardware only SBOREN is disabled 10 Brownout Reset enabled in hardware only and disabled in Sleep mode SBOREN is disabled 01 Brownout Reset enabled and controlled by software SBOREN is enabled 00 Brownout Reset disabled in hardware and software bit 0 PWRTEN Powerup Timer Enable bit2 1 PWRT disabled 0 PWRT enabled Note 1 See Section 261 DC Characteristics Supply Voltage for specifications 2 The Powerup Timer is decoupled from Brownout Reset allowing these features to be independently controlled PIC18F2420252044204520 DS39631Epage 252 2008 Microchip Technology Inc REGISTER 233 CONFIG2H CONFIGURATION REGISTER 2 HIGH BYTE ADDRESS 300003h U0 U0 U0 RP1 RP1 RP1 RP1 RP1 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 75 Unimplemented Read as 0 bit 41 WDTPS30 Watchdog Timer Postscale Select bits 1111 132768 1110 116384 1101 18192 1100 14096 1011 12048 1010 11024 1001 1512 1000 1256 0111 1128 0110 164 0101 132 0100 116 0011 18 0010 14 0001 12 0000 11 bit 0 WDTEN Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled control is placed on the SWDTEN bit 2008 Microchip Technology Inc DS39631Epage 253 PIC18F2420252044204520 REGISTER 234 CONFIG3H CONFIGURATION REGISTER 3 HIGH BYTE ADDRESS 300005h RP1 U0 U0 U0 U0 RP0 RP1 RP1 MCLRE LPT1OSC PBADEN CCP2MX bit 7 bit 0 Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 MCLRE MCLR Pin Enable bit 1 MCLR pin enabled RE3 input pin disabled 0 RE3 input pin enabled MCLR disabled bit 63 Unimplemented Read as 0 bit 2 LPT1OSC LowPower Timer1 Oscillator Enable bit 1 Timer1 configured for lowpower operation 0 Timer1 configured for higher power operation bit 1 PBADEN PORTB AD Enable bit Affects ADCON1 Reset state ADCON1 controls PORTB40 pin configuration 1 PORTB40 pins are configured as analog input channels on Reset 0 PORTB40 pins are configured as digital IO on Reset bit 0 CCP2MX CCP2 MUX bit 1 CCP2 inputoutput is multiplexed with RC1 0 CCP2 inputoutput is multiplexed with RB3 REGISTER 235 CONFIG4L CONFIGURATION REGISTER 4 LOW BYTE ADDRESS 300006h RP1 RP0 U0 U0 U0 RP1 U0 RP1 DEBUG XINST LVP STVREN bit 7 bit 0 Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 DEBUG Background Debugger Enable bit 1 Background debugger disabled RB6 and RB7 configured as general purpose IO pins 0 Background debugger enabled RB6 and RB7 are dedicated to InCircuit Debug bit 6 XINST Extended Instruction Set Enable bit 1 Instruction set extension and Indexed Addressing mode enabled 0 Instruction set extension and Indexed Addressing mode disabled Legacy mode bit 53 Unimplemented Read as 0 bit 2 LVP SingleSupply ICSP Enable bit 1 SingleSupply ICSP enabled 0 SingleSupply ICSP disabled bit 1 Unimplemented Read as 0 bit 0 STVREN Stack FullUnderflow Reset Enable bit 1 Stack fullunderflow will cause Reset 0 Stack fullunderflow will not cause Reset PIC18F2420252044204520 DS39631Epage 254 2008 Microchip Technology Inc REGISTER 236 CONFIG5L CONFIGURATION REGISTER 5 LOW BYTE ADDRESS 300008h U0 U0 U0 U0 RC1 RC1 RC1 RC1 CP31 CP21 CP1 CP0 bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 74 Unimplemented Read as 0 bit 3 CP3 Code Protection bit1 1 Block 3 006000007FFFh not codeprotected 0 Block 3 006000007FFFh codeprotected bit 2 CP2 Code Protection bit1 1 Block 2 004000005FFFh not codeprotected 0 Block 2 004000005FFFh codeprotected bit 1 CP1 Code Protection bit 1 Block 1 002000003FFFh not codeprotected 0 Block 1 002000003FFFh codeprotected bit 0 CP0 Code Protection bit 1 Block 0 000800001FFFh not codeprotected 0 Block 0 000800001FFFh codeprotected Note 1 Unimplemented in PIC18F24204420 devices maintain this bit set REGISTER 237 CONFIG5H CONFIGURATION REGISTER 5 HIGH BYTE ADDRESS 300009h RC1 RC1 U0 U0 U0 U0 U0 U0 CPD CPB bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 CPD Data EEPROM Code Protection bit 1 Data EEPROM not codeprotected 0 Data EEPROM codeprotected bit 6 CPB Boot Block Code Protection bit 1 Boot block 0000000007FFh not codeprotected 0 Boot block 0000000007FFh codeprotected bit 50 Unimplemented Read as 0 2008 Microchip Technology Inc DS39631Epage 255 PIC18F2420252044204520 REGISTER 238 CONFIG6L CONFIGURATION REGISTER 6 LOW BYTE ADDRESS 30000Ah U0 U0 U0 U0 RC1 RC1 RC1 RC1 WRT31 WRT21 WRT1 WRT0 bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 74 Unimplemented Read as 0 bit 3 WRT3 Write Protection bit1 1 Block 3 006000007FFFh not writeprotected 0 Block 3 006000007FFFh writeprotected bit 2 WRT2 Write Protection bit1 1 Block 2 004000005FFFh not writeprotected 0 Block 2 004000005FFFh writeprotected bit 1 WRT1 Write Protection bit 1 Block 1 002000003FFFh not writeprotected 0 Block 1 002000003FFFh writeprotected bit 0 WRT0 Write Protection bit 1 Block 0 000800001FFFh not writeprotected 0 Block 0 000800001FFFh writeprotected Note 1 Unimplemented in PIC18F24204420 devices maintain this bit set REGISTER 239 CONFIG6H CONFIGURATION REGISTER 6 HIGH BYTE ADDRESS 30000Bh RC1 RC1 RC1 U0 U0 U0 U0 U0 WRTD WRTB WRTC1 bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 WRTD Data EEPROM Write Protection bit 1 Data EEPROM not writeprotected 0 Data EEPROM writeprotected bit 6 WRTB Boot Block Write Protection bit 1 Boot block 0000000007FFh not writeprotected 0 Boot block 0000000007FFh writeprotected bit 5 WRTC Configuration Register Write Protection bit1 1 Configuration registers 3000003000FFh not writeprotected 0 Configuration registers 3000003000FFh writeprotected bit 40 Unimplemented Read as 0 Note 1 This bit is readonly in normal execution mode it can be written only in Program mode PIC18F2420252044204520 DS39631Epage 256 2008 Microchip Technology Inc REGISTER 2310 CONFIG7L CONFIGURATION REGISTER 7 LOW BYTE ADDRESS 30000Ch U0 U0 U0 U0 RC1 RC1 RC1 RC1 EBTR31 EBTR21 EBTR1 EBTR0 bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 74 Unimplemented Read as 0 bit 3 EBTR3 Table Read Protection bit1 1 Block 3 006000007FFFh not protected from table reads executed in other blocks 0 Block 3 006000007FFFh protected from table reads executed in other blocks bit 2 EBTR2 Table Read Protection bit1 1 Block 2 004000005FFFh not protected from table reads executed in other blocks 0 Block 2 004000005FFFh protected from table reads executed in other blocks bit 1 EBTR1 Table Read Protection bit 1 Block 1 002000003FFFh not protected from table reads executed in other blocks 0 Block 1 002000003FFFh protected from table reads executed in other blocks bit 0 EBTR0 Table Read Protection bit 1 Block 0 000800001FFFh not protected from table reads executed in other blocks 0 Block 0 000800001FFFh protected from table reads executed in other blocks Note 1 Unimplemented in PIC18F24204420 devices maintain this bit set REGISTER 2311 CONFIG7H CONFIGURATION REGISTER 7 HIGH BYTE ADDRESS 30000Dh U0 RC1 U0 U0 U0 U0 U0 U0 EBTRB bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 Unimplemented Read as 0 bit 6 EBTRB Boot Block Table Read Protection bit 1 Boot block 0000000007FFh not protected from table reads executed in other blocks 0 Boot block 0000000007FFh protected from table reads executed in other blocks bit 50 Unimplemented Read as 0 2008 Microchip Technology Inc DS39631Epage 257 PIC18F2420252044204520 REGISTER 2312 DEVID1 DEVICE ID REGISTER 1 FOR PIC18F2420252044204520 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 75 DEV20 Device ID bits 110 PIC18F4420 100 PIC18F4520 010 PIC18F2420 000 PIC18F2520 bit 40 REV40 Revision ID bits These bits are used to indicate the device revision REGISTER 2313 DEVID2 DEVICE ID REGISTER 2 FOR PIC18F2420252044204520 R R R R R R R R DEV101 DEV91 DEV81 DEV71 DEV61 DEV51 DEV41 DEV31 bit 7 bit 0 Legend R Readonly bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 70 DEV103 Device ID bits1 These bits are used with the DEV20 bits in Device ID Register 1 to identify the part number 0001 0001 PIC18F24202520 devices 0001 0000 PIC18F44204520 devices Note 1 These values for DEV103 may be shared with other devices The specific device is always identified by using the entire DEV100 bit sequence PIC18F2420252044204520 DS39631Epage 258 2008 Microchip Technology Inc 232 Watchdog Timer WDT For PIC18F2420252044204520 devices the WDT is driven by the INTRC source When the WDT is enabled the clock source is also enabled The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator The 4 ms period of the WDT is multiplied by a 16bit postscaler Any output of the WDT postscaler is selected by a multiplexer controlled by bits in Configu ration Register 2H Available periods range from 4 ms to 131072 seconds 218 minutes The WDT and postscaler are cleared when any of the following events occur a SLEEP or CLRWDT instruction is executed the IRCF bits OSCCON64 are changed or a clock failure has occurred 2321 CONTROL REGISTER Register 2314 shows the WDTCON register This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit but only if the Configuration bit has disabled the WDT FIGURE 231 WDT BLOCK DIAGRAM Note 1 The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed 2 Changing the setting of the IRCF bits OSCCON64 clears the WDT and postscaler counts 3 When a CLRWDT instruction is executed the postscaler count will be cleared INTRC Source WDT Wakeup from Reset WDT Counter Programmable Postscaler 11 to 132768 Enable WDT WDTPS30 SWDTEN WDTEN CLRWDT 4 PowerManaged Reset All Device Resets Sleep 128 Change on IRCF bits Modes 2008 Microchip Technology Inc DS39631Epage 259 PIC18F2420252044204520 TABLE 232 SUMMARY OF WATCHDOG TIMER REGISTERS REGISTER 2314 WDTCON WATCHDOG TIMER CONTROL REGISTER U0 U0 U0 U0 U0 U0 U0 RW0 SWDTEN1 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 71 Unimplemented Read as 0 bit 0 SWDTEN Software Controlled Watchdog Timer Enable bit1 1 Watchdog Timer is on 0 Watchdog Timer is off Note 1 This bit has no effect if the Configuration bit WDTEN is enabled Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RCON IPEN SBOREN1 RI TO PD POR BOR 48 WDTCON SWDTEN2 50 Legend unimplemented read as 0 Shaded cells are not used by the Watchdog Timer Note 1 The SBOREN bit is only available when the BOREN10 Configuration bits 01 otherwise it is disabled and reads as 0 See Section 44 Brownout Reset BOR 2 This bit has no effect if the Configuration bit WDTEN is enabled PIC18F2420252044204520 DS39631Epage 260 2008 Microchip Technology Inc 233 TwoSpeed Startup The TwoSpeed Startup feature helps to minimize the latency period from oscillator startup to code execution by allowing the microcontroller to use the INTOSC oscillator as a clock source until the primary clock source is available It is enabled by setting the IESO Configuration bit TwoSpeed Startup should be enabled only if the primary oscillator mode is LP XT HS or HSPLL CrystalBased modes Other sources do not require an OST startup delay for these TwoSpeed Startup should be disabled When enabled Resets and wakeups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source following the timeout of the Powerup Timer after a Poweron Reset is enabled This allows almost immediate code execution while the primary oscillator starts and the OST is running Once the OST times out the device automatically switches to PRIRUN mode To use a higher clock speed on wakeup the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRCF20 immediately after Reset For wakeups from Sleep the INTOSC or postscaler clock sources can be selected by setting the IRCF20 bits prior to entering Sleep mode In all other powermanaged modes TwoSpeed Start up is not used The device will be clocked by the currently selected clock source until the primary clock source becomes available The setting of the IESO bit is ignored 2331 SPECIAL CONSIDERATIONS FOR USING TWOSPEED STARTUP While using the INTOSC oscillator in TwoSpeed Start up the device still obeys the normal command sequences for entering powermanaged modes including multiple SLEEP instructions refer to Section 314 Multiple Sleep Commands In practice this means that user code can change the SCS10 bit settings or issue SLEEP instructions before the OST times out This would allow an application to briefly wakeup perform routine housekeeping tasks and return to Sleep before the device starts to operate from the primary oscillator User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit OSCCON3 If the bit is set the primary oscillator is providing the clock Otherwise the internal oscillator block is providing the clock during wakeup from Reset or Sleep mode FIGURE 232 TIMING TRANSITION FOR TWOSPEED STARTUP INTOSC TO HSPLL Q1 Q3 Q4 OSC1 Peripheral Program PC PC 2 INTOSC PLL Clock Q1 PC 6 Q2 Output Q3 Q4 Q1 CPU Clock PC 4 Clock Counter Q2 Q2 Q3 Note 1 TOST 1024 TOSC TPLL 2 ms approx These intervals are not shown to scale 2 Clock transition typically occurs within 24 TOSC Wake from Interrupt Event TPLL1 1 2 n1 n Clock OSTS bit Set Transition2 Multiplexer TOST1 2008 Microchip Technology Inc DS39631Epage 261 PIC18F2420252044204520 234 FailSafe Clock Monitor The FailSafe Clock Monitor FSCM allows the micro controller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block The FSCM function is enabled by setting the FCMEN Configuration bit When FSCM is enabled the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure Clock monitoring shown in Figure 233 is accomplished by creating a sample clock signal which is the INTRC out put divided by 64 This allows ample time between FSCM sample clocks for a peripheral clock edge to occur The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch CM The CM is set on the falling edge of the device clock source but cleared on the rising edge of the sample clock FIGURE 233 FSCM BLOCK DIAGRAM Clock failure is tested for on the falling edge of the sample clock If a sample clock falling edge occurs while CM is still set a clock failure has been detected Figure 234 This causes the following the FSCM generates an oscillator fail interrupt by setting bit OSCFIF PIR27 the device clock source is switched to the internal oscillator block OSCCON is not updated to show the current clock source this is the failsafe condition and the WDT is reset During switchover the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications In these cases it may be desirable to select another clock configuration and enter an alternate powermanaged mode This can be done to attempt a partial recovery or execute a controlled shut down See Section 314 Multiple Sleep Commands and Section 2331 Special Considerations for Using TwoSpeed Startup for more details To use a higher clock speed on wakeup the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRCF20 immedi ately after Reset For wakeups from Sleep the INTOSC or postscaler clock sources can be selected by setting the IRCF20 bits prior to entering Sleep mode The FSCM will detect failures of the primary or second ary clock sources only If the internal oscillator block fails no failure would be detected nor would any action be possible 2341 FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator Since the WDT operates with a separate divider and counter disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled As already noted the clock source is switched to the INTOSC clock when a clock failure is detected Depending on the frequency selected by the IRCF20 bits this may mean a substantial change in the speed of code execution If the WDT is enabled with a small prescale value a decrease in clock speed allows a WDT timeout to occur and a subsequent device Reset For this reason failsafe clock events also reset the WDT and postscaler allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous timeout 2342 EXITING FAILSAFE OPERATION The failsafe condition is terminated by either a device Reset or by entering a powermanaged mode On Reset the controller starts the primary clock source specified in Configuration Register 1H with any required startup delays that are required for the oscil lator mode such as the OST or PLL timer The INTOSC multiplexer provides the device clock until the primary clock source becomes ready similar to a Two Speed Startup The clock source is then switched to the primary clock indicated by the OSTS bit in the OSCCON register becoming set The FailSafe Clock Monitor then resumes monitoring the peripheral clock The primary clock source may never become ready dur ing startup In this case operation is clocked by the INTOSC multiplexer The OSCCON register will remain in its Reset state until a powermanaged mode is entered Peripheral INTRC 64 S C Q 32 μs 488 Hz 2048 ms Clock Monitor Latch CM edgetriggered Clock Failure Detected Source Clock Q PIC18F2420252044204520 DS39631Epage 262 2008 Microchip Technology Inc FIGURE 234 FSCM TIMING DIAGRAM 2343 FSCM INTERRUPTS IN POWERMANAGED MODES By entering a powermanaged mode the clock multi plexer selects the clock source selected by the OSCCON register FailSafe Clock Monitoring of the power managed clock source resumes in the powermanaged mode If an oscillator failure occurs during powermanaged operation the subsequent events depend on whether or not the oscillator failure interrupt is enabled If enabled OSCFIF 1 code execution will be clocked by the INTOSC multiplexer An automatic transition back to the failed clock source will not occur If the interrupt is disabled subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source 2344 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Poweron Reset POR or lowpower Sleep mode When the primary device clock is EC RC or INTRC modes monitoring can begin immediately following these events For oscillator modes involving a crystal or resonator HS HSPLL LP or XT the situation is somewhat different Since the oscillator may require a startup time considerably longer than the FCSM sample clock time a false clock failure may be detected To prevent this the internal oscillator block is automatically config ured as the device clock and functions until the primary clock is stable the OST and PLL timers have timed out This is identical to TwoSpeed Startup mode Once the primary clock is stable the INTRC returns to its role as the FSCM source As noted in Section 2331 Special Considerations for Using TwoSpeed Startup it is also possible to select another clock configuration and enter an alternate powermanaged mode while waiting for the primary clock to become stable When the new power managed mode is selected the primary clock is disabled OSCFIF CM Output Device Clock Output Sample Clock Failure Detected Oscillator Failure Note The device clock is normally at a much higher frequency than the sample clock The relative frequencies in this example have been chosen for clarity Q CM Test CM Test CM Test Note The same logic that prevents false oscilla tor failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillators failure to start at all follow ing these events This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start Even so no oscillator failure interrupt will be flagged 2008 Microchip Technology Inc DS39631Epage 263 PIC18F2420252044204520 235 Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC devices The user program memory is divided into five blocks One of these is a boot block of 2 Kbytes The remainder of the memory is divided into four blocks on binary boundaries Each of the five blocks has three code protection bits associated with them They are CodeProtect bit CPn WriteProtect bit WRTn External Block Table Read bit EBTRn Figure 235 shows the program memory organization for 16 and 32Kbyte devices and the specific code pro tection bit associated with each block The actual locations of the bits are summarized in Table 233 FIGURE 235 CODEPROTECTED PROGRAM MEMORY FOR PIC18F2420252044204520 TABLE 233 SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L CP31 CP21 CP1 CP0 300009h CONFIG5H CPD CPB 30000Ah CONFIG6L WRT31 WRT21 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC 30000Ch CONFIG7L EBTR31 EBTR21 EBTR1 EBTR0 30000Dh CONFIG7H EBTRB Legend Shaded cells are unimplemented Note 1 Unimplemented in PIC18F24204420 devices maintain this bit set MEMORY SIZEDEVICE Block Code Protection Controlled By 16 Kbytes PIC18F24204420 32 Kbytes PIC18F25204520 Address Range Boot Block Boot Block 000000h 0007FFh CPB WRTB EBTRB Block 0 Block 0 000800h 001FFFh CP0 WRT0 EBTR0 Block 1 Block 1 002000h 003FFFh CP1 WRT1 EBTR1 Unimplemented Read 0s Block 2 004000h 005FFFh CP2 WRT2 EBTR2 Block 3 006000h 007FFFh CP3 WRT3 EBTR3 Unimplemented Read 0s 1FFFFFh Unimplemented Memory Space PIC18F2420252044204520 DS39631Epage 264 2008 Microchip Technology Inc 2351 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions The Device ID may be read with table reads The Configuration registers may be read and written with the table read and table write instructions In normal execution mode the CPn bits have no direct effect CPn bits inhibit external reads and writes A block of user memory may be protected from table writes if the WRTn Configuration bit is 0 The EBTRn bits control table reads For a block of user memory with the EBTRn bit set to 0 a table read instruction that executes from within that block is allowed to read A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading 0s Figures 236 through 238 illustrate table write and table read protection FIGURE 236 TABLE WRITE WRTn DISALLOWED Note Code protection bits may only be written to a 0 from a 1 state It is not possible to write a 1 to a bit in the 0 state Code pro tection bits are only set to 1 by a full chip erase or block erase function The full chip erase and block erase functions can only be initiated via ICSP or an external programmer 000000h 0007FFh 000800h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh WRTB EBTRB 11 WRT0 EBTR0 01 WRT1 EBTR1 11 WRT2 EBTR2 11 WRT3 EBTR3 11 TBLWT TBLPTR 0008FFh PC 001FFEh TBLWT PC 005FFEh Register Values Program Memory Configuration Bit Settings Results All table writes disabled to Blockn whenever WRTn 0 2008 Microchip Technology Inc DS39631Epage 265 PIC18F2420252044204520 FIGURE 237 EXTERNAL BLOCK TABLE READ EBTRn DISALLOWED FIGURE 238 EXTERNAL BLOCK TABLE READ EBTRn ALLOWED WRTB EBTRB 11 WRT0 EBTR0 10 WRT1 EBTR1 11 WRT2 EBTR2 11 WRT3 EBTR3 11 TBLRD TBLPTR 0008FFh PC 003FFEh Results All table reads from external blocks to Blockn are disabled whenever EBTRn 0 TABLAT register returns a value of 0 Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh WRTB EBTRB 11 WRT0 EBTR0 10 WRT1 EBTR1 11 WRT2 EBTR2 11 WRT3 EBTR3 11 TBLRD TBLPTR 0008FFh PC 001FFEh Register Values Program Memory Configuration Bit Settings Results Table reads permitted within Blockn even when EBTRBn 0 TABLAT register returns the value of the data at the location TBLPTR 000000h 0007FFh 000800h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh PIC18F2420252044204520 DS39631Epage 266 2008 Microchip Technology Inc 2352 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits CPD and WRTD CPD inhibits external reads and writes of data EEPROM WRTD inhibits internal and external writes to data EEPROM The CPU can always read data EEPROM under normal operation regardless of the protection bit settings 2353 CONFIGURATION REGISTER PROTECTION The Configuration registers can be writeprotected The WRTC bit controls protection of the Configuration registers In normal execution mode the WRTC bit is readonly WRTC can only be written via ICSP or an external programmer 236 ID Locations Eight memory locations 200000h200007h are designated as ID locations where the user can store checksum or other code identification numbers These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during programverify The ID locations can be read when the device is codeprotected 237 InCircuit Serial Programming PIC18F2420252044204520 devices can be serially programmed while in the end application circuit This is simply done with two lines for clock and data and three other lines for power ground and the programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product This also allows the most recent firmware or a custom firmware to be programmed 238 InCircuit Debugger When the DEBUG Configuration bit is programmed to a 0 the InCircuit Debugger functionality is enabled This function allows simple debugging functions when used with MPLAB IDE When the microcontroller has this feature enabled some resources are not available for general use Table 234 shows which resources are required by the background debugger TABLE 234 DEBUGGER RESOURCES To use the InCircuit Debugger function of the micro controller the design must implement InCircuit Serial Programming connections to MCLRVPPRE3 VDD VSS RB7 and RB6 This will interface to the InCircuit Debugger module available from Microchip or one of the third party development tool companies 239 SingleSupply ICSP Programming The LVP Configuration bit enables SingleSupply ICSP Programming formerly known as LowVoltage ICSP Programming or LVP When SingleSupply Program ming is enabled the microcontroller can be programmed without requiring high voltage being applied to the MCLRVPPRE3 pin but the RB5KBI1PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose IO pin While programming using SingleSupply Programming mode VDD is applied to the MCLRVPPRE3 pin as in normal execution mode To enter Programming mode VDD is applied to the PGM pin If SingleSupply ICSP Programming mode will not be used the LVP bit can be cleared RB5KBI1PGM then becomes available as the digital IO pin RB5 The LVP bit may be set or cleared only when using standard highvoltage programming VIHH applied to the MCLR VPPRE3 pin Once LVP has been disabled only the standard highvoltage programming is available and must be used to program the device Memory that is not codeprotected can be erased using either a block erase or erased row by row then written at any specified VDD If codeprotected memory is to be erased a block erase is required If a block erase is to be performed when using LowVoltage Programming the device must be supplied with VDD of 45V to 55V IO pins RB6 RB7 Stack 2 levels Program Memory 512 bytes Data Memory 10 bytes Note 1 Highvoltage programming is always available regardless of the state of the LVP bit or the PGM pin by applying VIHH to the MCLR pin 2 By default SingleSupply ICSP is enabled in unprogrammed devices as supplied from Microchip and erased devices 3 When SingleSupply Programming is enabled the RB5 pin can no longer be used as a general purpose IO pin 4 When LVP is enabled externally pull the PGM pin to VSS to allow normal program execution 2008 Microchip Technology Inc DS39631Epage 267 PIC18F2420252044204520 240 INSTRUCTION SET SUMMARY PIC18F2420252044204520 devices incorporate the standard set of 75 PIC18 core instructions as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack The extended set is discussed later in this section 241 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PIC MCU instruction sets while maintaining an easy migration from these PIC MCU instruction sets Most instructions are a single program memory word 16 bits but there are four instructions that require two program memory locations Each singleword instruction is a 16bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction The instruction set is highly orthogonal and is grouped into four basic categories Byteoriented operations Bitoriented operations Literal operations Control operations The PIC18 instruction set summary in Table 242 lists byteoriented bitoriented literal and control operations Table 241 shows the opcode field descriptions Most byteoriented instructions have three operands 1 The file register specified by f 2 The destination of the result specified by d 3 The accessed memory specified by a The file register designator f specifies which file register is to be used by the instruction The destination designator d specifies where the result of the opera tion is to be placed If d is zero the result is placed in the WREG register If d is one the result is placed in the file register specified in the instruction All bitoriented instructions have three operands 1 The file register specified by f 2 The bit in the file register specified by b 3 The accessed memory specified by a The bit field designator b selects the number of the bit affected by the operation while the file register designator f represents the number of the file in which the bit is located The literal instructions may use some of the following operands A literal value to be loaded into a file register specified by k The desired FSR register to load the literal value into specified by f No operand required specified by The control instructions may use some of the following operands A program memory address specified by n The mode of the CALL or RETURN instructions specified by s The mode of the table read and table write instructions specified by m No operand required specified by All instructions are a single word except for four doubleword instructions These instructions were made doubleword to contain the required information in 32 bits In the second word the 4 MSbs are 1s If this second word is executed as an instruction by itself it will execute as a NOP All singleword instructions are executed in a single instruction cycle unless a conditional test is true or the program counter is changed as a result of the instruc tion In these cases the execution takes two instruction cycles with the additional instruction cycles executed as a NOP The doubleword instructions execute in two instruction cycles One instruction cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 μs If a conditional test is true or the program counter is changed as a result of an instruction the instruction execution time is 2 μs Twoword branch instructions if true would take 3 μs Figure 241 shows the general formats that the instruc tions can have All examples use the convention nnh to represent a hexadecimal number The Instruction Set Summary shown in Table 242 lists the standard instructions recognized by the Microchip Assembler MPASMTM Section 2411 Standard Instruction Set provides a description of each instruction PIC18F2420252044204520 DS39631Epage 268 2008 Microchip Technology Inc TABLE 241 OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a 0 RAM location in Access RAM BSR register is ignored a 1 RAM bank is specified by BSR register bbb Bit address within an 8bit file register 0 to 7 BSR Bank Select Register Used to select the current RAM bank C DC Z OV N ALU Status bits Carry Digit Carry Zero Overflow Negative d Destination select bit d 0 store result in WREG d 1 store result in file register f dest Destination either the WREG register or the specified register file location f 8bit Register file address 00h to FFh or 2bit FSR designator 0h to 3h fs 12bit Register file address 000h to FFFh This is the source address fd 12bit Register file address 000h to FFFh This is the destination address GIE Global Interrupt Enable bit k Literal field constant data or label may be either an 8bit 12bit or a 20bit value label Label name mm The mode of the TBLPTR register for the table read and table write instructions Only used with table read and table write instructions No change to register such as TBLPTR with table reads and writes PostIncrement register such as TBLPTR with table reads and writes PostDecrement register such as TBLPTR with table reads and writes PreIncrement register such as TBLPTR with table reads and writes n The relative address 2s complement number for relative branch instructions or the direct address for CallBranch and Return instructions PC Program Counter PCL Program Counter Low Byte PCH Program Counter High Byte PCLATH Program Counter High Byte Latch PCLATU Program Counter Upper Byte Latch PD Powerdown bit PRODH Product of Multiply High Byte PRODL Product of Multiply Low Byte s Fast CallReturn mode select bit s 0 do not update intofrom shadow registers s 1 certain registers loaded intofrom shadow registers Fast mode TBLPTR 21bit Table Pointer points to a Program Memory location TABLAT 8bit Table Latch TO Timeout bit TOS TopofStack u Unused or unchanged WDT Watchdog Timer WREG Working register accumulator x Dont care 0 or 1 The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools zs 7bit offset value for indirect addressing of register files source zd 7bit offset value for indirect addressing of register files destination Optional argument text Indicates an indexed address text The contents of text exprn Specifies bit n of the register indicated by the pointer expr Assigned to Register bit field In the set of italics Userdefined term font is Courier New 2008 Microchip Technology Inc DS39631Epage 269 PIC18F2420252044204520 FIGURE 241 GENERAL FORMAT FOR INSTRUCTIONS Byteoriented file register operations 15 10 9 8 7 0 d 0 for result destination to be WREG register OPCODE d a f FILE d 1 for result destination to be file register f a 0 to force Access Bank Bitoriented file register operations 15 12 11 9 8 7 0 OPCODE b BIT a f FILE b 3bit position of bit in file register f Literal operations 15 8 7 0 OPCODE k literal k 8bit immediate value Byte to Byte move operations 2word 15 12 11 0 OPCODE f Source FILE CALL GOTO and Branch operations 15 8 7 0 OPCODE n70 literal n 20bit immediate value a 1 for BSR to select bank f 8bit file register address a 0 to force Access Bank a 1 for BSR to select bank f 8bit file register address 15 12 11 0 1111 n198 literal 15 12 11 0 1111 f Destination FILE f 12bit file register address Control operations Example Instruction ADDWF MYREG W B MOVFF MYREG1 MYREG2 BSF MYREG bit B MOVLW 7Fh GOTO Label 15 8 7 0 OPCODE n70 literal 15 12 11 0 1111 n198 literal CALL MYFUNC 15 11 10 0 OPCODE n100 literal S Fast bit BRA MYFUNC 15 8 7 0 OPCODE n70 literal BC MYFUNC S PIC18F2420252044204520 DS39631Epage 270 2008 Microchip Technology Inc TABLE 242 PIC18FXXXX INSTRUCTION SET Mnemonic Operands Description Cycles 16Bit Instruction Word Status Affected Notes MSb LSb BYTEORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF f d a f d a f d a f a f d a f a f a f a f d a f d a f d a f d a f d a f d a f d a f d a fs fd f a f a f a f d a f d a f d a f d a f a f d a f d a f d a f d a f a f d a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG Skip Compare f with WREG Skip Compare f with WREG Skip Decrement f Decrement f Skip if 0 Decrement f Skip if Not 0 Increment f Increment f Skip if 0 Increment f Skip if Not 0 Inclusive OR WREG with f Move f Move fs source to 1st word fd destination 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f No Carry Rotate Right f through Carry Rotate Right f No Carry Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap Nibbles in f Test f Skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 2 or 3 1 2 or 3 1 2 or 3 1 1 2 or 3 1 2 or 3 1 1 2 or 3 1 2 or 3 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 or 3 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C DC Z OV N C DC Z OV N Z N Z Z N None None None C DC Z OV N None None C DC Z OV N None None Z N Z N None None None C DC Z OV N C Z N Z N C Z N Z N None C DC Z OV N C DC Z OV N C DC Z OV N None None Z N 1 2 1 2 12 2 1 2 4 4 1 2 1 2 3 4 1 2 3 4 1 2 1 2 3 4 4 1 2 1 2 1 1 2 1 2 1 2 1 2 4 1 2 Note 1 When a PORT register is modified as a function of itself eg MOVF PORTB 1 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 2 If this instruction is executed on the TMR0 register and where applicable d 1 the prescaler will be cleared if assigned 3 If the Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP 4 Some instructions are twoword instructions The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction 2008 Microchip Technology Inc DS39631Epage 271 PIC18F2420252044204520 BITORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f b a f b a f b a f b a f d a Bit Clear f Bit Set f Bit Test f Skip if Clear Bit Test f Skip if Set Bit Toggle f 1 1 1 2 or 3 1 2 or 3 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 2 1 2 3 4 3 4 1 2 CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP n n n n n n n n n n s n n s k s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call Subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to Address 1st word 2nd word No Operation No Operation Pop Top of Return Stack TOS Push Top of Return Stack TOS Relative Call Software Device Reset Return from Interrupt Enable Return with Literal in WREG Return from Subroutine Go into Standby mode 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 None None None None None None None None None None TO PD C None None None None None None All GIEGIEH PEIEGIEL None None TO PD 4 TABLE 242 PIC18FXXXX INSTRUCTION SET CONTINUED Mnemonic Operands Description Cycles 16Bit Instruction Word Status Affected Notes MSb LSb Note 1 When a PORT register is modified as a function of itself eg MOVF PORTB 1 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 2 If this instruction is executed on the TMR0 register and where applicable d 1 the prescaler will be cleared if assigned 3 If the Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP 4 Some instructions are twoword instructions The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction PIC18F2420252044204520 DS39631Epage 272 2008 Microchip Technology Inc LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k f k k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal 12bit2nd word to FSRf 1st word Move Literal to BSR30 Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG from Literal Exclusive OR Literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C DC Z OV N Z N Z N None None None None None C DC Z OV N Z N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD TBLRD TBLRD TBLRD TBLWT TBLWT TBLWT TBLWT Table Read Table Read with PostIncrement Table Read with PostDecrement Table Read with PreIncrement Table Write Table Write with PostIncrement Table Write with PostDecrement Table Write with PreIncrement 2 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None TABLE 242 PIC18FXXXX INSTRUCTION SET CONTINUED Mnemonic Operands Description Cycles 16Bit Instruction Word Status Affected Notes MSb LSb Note 1 When a PORT register is modified as a function of itself eg MOVF PORTB 1 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 2 If this instruction is executed on the TMR0 register and where applicable d 1 the prescaler will be cleared if assigned 3 If the Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP 4 Some instructions are twoword instructions The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction 2008 Microchip Technology Inc DS39631Epage 273 PIC18F2420252044204520 2411 STANDARD INSTRUCTION SET ADDLW ADD Literal to W Syntax ADDLW k Operands 0 k 255 Operation W k W Status Affected N OV C DC Z Encoding 0000 1111 kkkk kkkk Description The contents of W are added to the 8bit literal k and the result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to W Example ADDLW 15h Before Instruction W 10h After Instruction W 25h ADDWF ADD W to f Syntax ADDWF f d a Operands 0 f 255 d 01 a 01 Operation W f dest Status Affected N OV C DC Z Encoding 0010 01da ffff ffff Description Add W to register f If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example ADDWF REG 0 0 Before Instruction W 17h REG 0C2h After Instruction W 0D9h REG 0C2h Note All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing If a label is used the instruction format then becomes label instruction arguments PIC18F2420252044204520 DS39631Epage 274 2008 Microchip Technology Inc ADDWFC ADD W and Carry bit to f Syntax ADDWFC f d a Operands 0 f 255 d 01 a 01 Operation W f C dest Status Affected NOV C DC Z Encoding 0010 00da ffff ffff Description Add W the Carry flag and data memory location f If d is 0 the result is placed in W If d is 1 the result is placed in data memory location f If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example ADDWFC REG 0 1 Before Instruction Carry bit 1 REG 02h W 4Dh After Instruction Carry bit 0 REG 02h W 50h ANDLW AND Literal with W Syntax ANDLW k Operands 0 k 255 Operation W AND k W Status Affected N Z Encoding 0000 1011 kkkk kkkk Description The contents of W are ANDed with the 8bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to W Example ANDLW 05Fh Before Instruction W A3h After Instruction W 03h 2008 Microchip Technology Inc DS39631Epage 275 PIC18F2420252044204520 ANDWF AND W with f Syntax ANDWF f d a Operands 0 f 255 d 01 a 01 Operation W AND f dest Status Affected N Z Encoding 0001 01da ffff ffff Description The contents of W are ANDed with register f If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example ANDWF REG 0 0 Before Instruction W 17h REG C2h After Instruction W 02h REG C2h BC Branch if Carry Syntax BC n Operands 128 n 127 Operation if Carry bit is 1 PC 2 2n PC Status Affected None Encoding 1110 0010 nnnn nnnn Description If the Carry bit is 1 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BC 5 Before Instruction PC address HERE After Instruction If Carry 1 PC address HERE 12 If Carry 0 PC address HERE 2 PIC18F2420252044204520 DS39631Epage 276 2008 Microchip Technology Inc BCF Bit Clear f Syntax BCF f b a Operands 0 f 255 0 b 7 a 01 Operation 0 fb Status Affected None Encoding 1001 bbba ffff ffff Description Bit b in register f is cleared If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write register f Example BCF FLAGREG 7 0 Before Instruction FLAGREG C7h After Instruction FLAGREG 47h BN Branch if Negative Syntax BN n Operands 128 n 127 Operation if Negative bit is 1 PC 2 2n PC Status Affected None Encoding 1110 0110 nnnn nnnn Description If the Negative bit is 1 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BN Jump Before Instruction PC address HERE After Instruction If Negative 1 PC address Jump If Negative 0 PC address HERE 2 2008 Microchip Technology Inc DS39631Epage 277 PIC18F2420252044204520 BNC Branch if Not Carry Syntax BNC n Operands 128 n 127 Operation if Carry bit is 0 PC 2 2n PC Status Affected None Encoding 1110 0011 nnnn nnnn Description If the Carry bit is 0 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BNC Jump Before Instruction PC address HERE After Instruction If Carry 0 PC address Jump If Carry 1 PC address HERE 2 BNN Branch if Not Negative Syntax BNN n Operands 128 n 127 Operation if Negative bit is 0 PC 2 2n PC Status Affected None Encoding 1110 0111 nnnn nnnn Description If the Negative bit is 0 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BNN Jump Before Instruction PC address HERE After Instruction If Negative 0 PC address Jump If Negative 1 PC address HERE 2 PIC18F2420252044204520 DS39631Epage 278 2008 Microchip Technology Inc BNOV Branch if Not Overflow Syntax BNOV n Operands 128 n 127 Operation if Overflow bit is 0 PC 2 2n PC Status Affected None Encoding 1110 0101 nnnn nnnn Description If the Overflow bit is 0 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BNOV Jump Before Instruction PC address HERE After Instruction If Overflow 0 PC address Jump If Overflow 1 PC address HERE 2 BNZ Branch if Not Zero Syntax BNZ n Operands 128 n 127 Operation if Zero bit is 0 PC 2 2n PC Status Affected None Encoding 1110 0001 nnnn nnnn Description If the Zero bit is 0 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BNZ Jump Before Instruction PC address HERE After Instruction If Zero 0 PC address Jump If Zero 1 PC address HERE 2 2008 Microchip Technology Inc DS39631Epage 279 PIC18F2420252044204520 BRA Unconditional Branch Syntax BRA n Operands 1024 n 1023 Operation PC 2 2n PC Status Affected None Encoding 1101 0nnn nnnn nnnn Description Add the 2s complement number 2n to the PC Since the PC will have incre mented to fetch the next instruction the new address will be PC 2 2n This instruction is a twocycle instruction Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation Example HERE BRA Jump Before Instruction PC address HERE After Instruction PC address Jump BSF Bit Set f Syntax BSF f b a Operands 0 f 255 0 b 7 a 01 Operation 1 fb Status Affected None Encoding 1000 bbba ffff ffff Description Bit b in register f is set If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write register f Example BSF FLAGREG 7 1 Before Instruction FLAGREG 0Ah After Instruction FLAGREG 8Ah PIC18F2420252044204520 DS39631Epage 280 2008 Microchip Technology Inc BTFSC Bit Test File Skip if Clear Syntax BTFSC f b a Operands 0 f 255 0 b 7 a 01 Operation skip if fb 0 Status Affected None Encoding 1011 bbba ffff ffff Description If bit b in register f is 0 then the next instruction is skipped If bit b is 0 then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data No operation If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE FALSE TRUE BTFSC FLAG 1 0 Before Instruction PC address HERE After Instruction If FLAG1 0 PC address TRUE If FLAG1 1 PC address FALSE BTFSS Bit Test File Skip if Set Syntax BTFSS f b a Operands 0 f 255 0 b 7 a 01 Operation skip if fb 1 Status Affected None Encoding 1010 bbba ffff ffff Description If bit b in register f is 1 then the next instruction is skipped If bit b is 1 then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data No operation If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE FALSE TRUE BTFSS FLAG 1 0 Before Instruction PC address HERE After Instruction If FLAG1 0 PC address FALSE If FLAG1 1 PC address TRUE 2008 Microchip Technology Inc DS39631Epage 281 PIC18F2420252044204520 BTG Bit Toggle f Syntax BTG f b a Operands 0 f 255 0 b 7 a 01 Operation fb fb Status Affected None Encoding 0111 bbba ffff ffff Description Bit b in data memory location f is inverted If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write register f Example BTG PORTC 4 0 Before Instruction PORTC 0111 0101 75h After Instruction PORTC 0110 0101 65h BOV Branch if Overflow Syntax BOV n Operands 128 n 127 Operation if Overflow bit is 1 PC 2 2n PC Status Affected None Encoding 1110 0100 nnnn nnnn Description If the Overflow bit is 1 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BOV Jump Before Instruction PC address HERE After Instruction If Overflow 1 PC address Jump If Overflow 0 PC address HERE 2 PIC18F2420252044204520 DS39631Epage 282 2008 Microchip Technology Inc BZ Branch if Zero Syntax BZ n Operands 128 n 127 Operation if Zero bit is 1 PC 2 2n PC Status Affected None Encoding 1110 0000 nnnn nnnn Description If the Zero bit is 1 then the program will branch The 2s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a twocycle instruction Words 1 Cycles 12 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data Write to PC No operation No operation No operation No operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal n Process Data No operation Example HERE BZ Jump Before Instruction PC address HERE After Instruction If Zero 1 PC address Jump If Zero 0 PC address HERE 2 CALL Subroutine Call Syntax CALL k s Operands 0 k 1048575 s 01 Operation PC 4 TOS k PC201 if s 1 W WS STATUS STATUSS BSR BSRS Status Affected None Encoding 1st word k70 2nd wordk198 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 Description Subroutine call of entire 2Mbyte memory range First return address PC 4 is pushed onto the return stack If s 1 the W STATUS and BSR registers are also pushed into their respective shadow registers WS STATUSS and BSRS If s 0 no update occurs default Then the 20bit value k is loaded into PC201 CALL is a twocycle instruction Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k70 PUSH PC to stack Read literal k198 Write to PC No operation No operation No operation No operation Example HERE CALL THERE 1 Before Instruction PC address HERE After Instruction PC address THERE TOS address HERE 4 WS W BSRS BSR STATUSS STATUS 2008 Microchip Technology Inc DS39631Epage 283 PIC18F2420252044204520 CLRF Clear f Syntax CLRF f a Operands 0 f 255 a 01 Operation 000h f 1 Z Status Affected Z Encoding 0110 101a ffff ffff Description Clears the contents of the specified register If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write register f Example CLRF FLAGREG 1 Before Instruction FLAGREG 5Ah After Instruction FLAGREG 00h CLRWDT Clear Watchdog Timer Syntax CLRWDT Operands None Operation 000h WDT 000h WDT postscaler 1 TO 1 PD Status Affected TO PD Encoding 0000 0000 0000 0100 Description CLRWDT instruction resets the Watchdog Timer It also resets the post scaler of the WDT Status bits TO and PD are set Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example CLRWDT Before Instruction WDT Counter After Instruction WDT Counter 00h WDT Postscaler 0 TO 1 PD 1 PIC18F2420252044204520 DS39631Epage 284 2008 Microchip Technology Inc COMF Complement f Syntax COMF f d a Operands 0 f 255 d 01 a 01 Operation f dest Status Affected N Z Encoding 0001 11da ffff ffff Description The contents of register f are complemented If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example COMF REG 0 0 Before Instruction REG 13h After Instruction REG 13h W ECh CPFSEQ Compare f with W Skip if f W Syntax CPFSEQ f a Operands 0 f 255 a 01 Operation f W skip if f W unsigned comparison Status Affected None Encoding 0110 001a ffff ffff Description Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction If f W then the fetched instruction is discarded and a NOP is executed instead making this a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data No operation If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE CPFSEQ REG 0 NEQUAL EQUAL Before Instruction PC Address HERE W REG After Instruction If REG W PC Address EQUAL If REG W PC Address NEQUAL 2008 Microchip Technology Inc DS39631Epage 285 PIC18F2420252044204520 CPFSGT Compare f with W Skip if f W Syntax CPFSGT f a Operands 0 f 255 a 01 Operation f W skip if f W unsigned comparison Status Affected None Encoding 0110 010a ffff ffff Description Compares the contents of data memory location f to the contents of the W by performing an unsigned subtraction If the contents of f are greater than the contents of WREG then the fetched instruction is discarded and a NOP is executed instead making this a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data No operation If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE CPFSGT REG 0 NGREATER GREATER Before Instruction PC Address HERE W After Instruction If REG W PC Address GREATER If REG W PC Address NGREATER CPFSLT Compare f with W Skip if f W Syntax CPFSLT f a Operands 0 f 255 a 01 Operation f W skip if f W unsigned comparison Status Affected None Encoding 0110 000a ffff ffff Description Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction If the contents of f are less than the contents of W then the fetched instruction is discarded and a NOP is executed instead making this a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data No operation If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE CPFSLT REG 1 NLESS LESS Before Instruction PC Address HERE W After Instruction If REG W PC Address LESS If REG W PC Address NLESS PIC18F2420252044204520 DS39631Epage 286 2008 Microchip Technology Inc DAW Decimal Adjust W Register Syntax DAW Operands None Operation If W30 9 or DC 1 then W30 6 W30 else W30 W30 If W74 DC 9 or C 1 then W74 6 DC W74 else W74 DC W74 Status Affected C Encoding 0000 0000 0000 0111 Description DAW adjusts the 8bit value in W resulting from the earlier addition of two variables each in packed BCD format and produces a correct packed BCD result Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example 1 DAW Before Instruction W A5h C 0 DC 0 After Instruction W 05h C 1 DC 0 Example 2 Before Instruction W CEh C 0 DC 0 After Instruction W 34h C 1 DC 0 DECF Decrement f Syntax DECF f d a Operands 0 f 255 d 01 a 01 Operation f 1 dest Status Affected C DC N OV Z Encoding 0000 01da ffff ffff Description Decrement register f If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example DECF CNT 1 0 Before Instruction CNT 01h Z 0 After Instruction CNT 00h Z 1 2008 Microchip Technology Inc DS39631Epage 287 PIC18F2420252044204520 DECFSZ Decrement f Skip if 0 Syntax DECFSZ f d a Operands 0 f 255 d 01 a 01 Operation f 1 dest skip if result 0 Status Affected None Encoding 0010 11da ffff ffff Description The contents of register f are decremented If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If the result is 0 the next instruction which is already fetched is discarded and a NOP is executed instead making it a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE DECFSZ CNT 1 1 GOTO LOOP CONTINUE Before Instruction PC Address HERE After Instruction CNT CNT 1 If CNT 0 PC Address CONTINUE If CNT 0 PC Address HERE 2 DCFSNZ Decrement f Skip if Not 0 Syntax DCFSNZ f d a Operands 0 f 255 d 01 a 01 Operation f 1 dest skip if result 0 Status Affected None Encoding 0100 11da ffff ffff Description The contents of register f are decremented If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If the result is not 0 the next instruction which is already fetched is discarded and a NOP is executed instead making it a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE DCFSNZ TEMP 1 0 ZERO NZERO Before Instruction TEMP After Instruction TEMP TEMP 1 If TEMP 0 PC Address ZERO If TEMP 0 PC Address NZERO PIC18F2420252044204520 DS39631Epage 288 2008 Microchip Technology Inc GOTO Unconditional Branch Syntax GOTO k Operands 0 k 1048575 Operation k PC201 Status Affected None Encoding 1st word k70 2nd wordk198 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description GOTO allows an unconditional branch anywhere within entire 2Mbyte memory range The 20bit value k is loaded into PC201 GOTO is always a twocycle instruction Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k70 No operation Read literal k198 Write to PC No operation No operation No operation No operation Example GOTO THERE After Instruction PC Address THERE INCF Increment f Syntax INCF f d a Operands 0 f 255 d 01 a 01 Operation f 1 dest Status Affected C DC N OV Z Encoding 0010 10da ffff ffff Description The contents of register f are incremented If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example INCF CNT 1 0 Before Instruction CNT FFh Z 0 C DC After Instruction CNT 00h Z 1 C 1 DC 1 2008 Microchip Technology Inc DS39631Epage 289 PIC18F2420252044204520 INCFSZ Increment f Skip if 0 Syntax INCFSZ f d a Operands 0 f 255 d 01 a 01 Operation f 1 dest skip if result 0 Status Affected None Encoding 0011 11da ffff ffff Description The contents of register f are incremented If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If the result is 0 the next instruction which is already fetched is discarded and a NOP is executed instead making it a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE INCFSZ CNT 1 0 NZERO ZERO Before Instruction PC Address HERE After Instruction CNT CNT 1 If CNT 0 PC Address ZERO If CNT 0 PC Address NZERO INFSNZ Increment f Skip if Not 0 Syntax INFSNZ f d a Operands 0 f 255 d 01 a 01 Operation f 1 dest skip if result 0 Status Affected None Encoding 0100 10da ffff ffff Description The contents of register f are incremented If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If the result is not 0 the next instruction which is already fetched is discarded and a NOP is executed instead making it a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE INFSNZ REG 1 0 ZERO NZERO Before Instruction PC Address HERE After Instruction REG REG 1 If REG 0 PC Address NZERO If REG 0 PC Address ZERO PIC18F2420252044204520 DS39631Epage 290 2008 Microchip Technology Inc IORLW Inclusive OR Literal with W Syntax IORLW k Operands 0 k 255 Operation W OR k W Status Affected N Z Encoding 0000 1001 kkkk kkkk Description The contents of W are ORed with the 8bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to W Example IORLW 35h Before Instruction W 9Ah After Instruction W BFh IORWF Inclusive OR W with f Syntax IORWF f d a Operands 0 f 255 d 01 a 01 Operation W OR f dest Status Affected N Z Encoding 0001 00da ffff ffff Description Inclusive OR W with register f If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example IORWF RESULT 0 1 Before Instruction RESULT 13h W 91h After Instruction RESULT 13h W 93h 2008 Microchip Technology Inc DS39631Epage 291 PIC18F2420252044204520 LFSR Load FSR Syntax LFSR f k Operands 0 f 2 0 k 4095 Operation k FSRf Status Affected None Encoding 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description The 12bit literal k is loaded into the File Select Register pointed to by f Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k MSB Process Data Write literal k MSB to FSRfH Decode Read literal k LSB Process Data Write literal k to FSRfL Example LFSR 2 3ABh After Instruction FSR2H 03h FSR2L ABh MOVF Move f Syntax MOVF f d a Operands 0 f 255 d 01 a 01 Operation f dest Status Affected N Z Encoding 0101 00da ffff ffff Description The contents of register f are moved to a destination dependent upon the status of d If d is 0 the result is placed in W If d is 1 the result is placed back in register f default Location f can be anywhere in the 256byte bank If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write W Example MOVF REG 0 0 Before Instruction REG 22h W FFh After Instruction REG 22h W 22h PIC18F2420252044204520 DS39631Epage 292 2008 Microchip Technology Inc MOVFF Move f to f Syntax MOVFF fsfd Operands 0 fs 4095 0 fd 4095 Operation fs fd Status Affected None Encoding 1st word source 2nd word destin 1100 1111 ffff ffff ffff ffff ffffs ffffd Description The contents of source register fs are moved to destination register fd Location of source fs can be anywhere in the 4096byte data space 000h to FFFh and location of destination fd can also be anywhere from 000h to FFFh Either source or destination can be W a useful special situation MOVFF is particularly useful for transferring a data memory location to a peripheral register such as the transmit buffer or an IO port The MOVFF instruction cannot use the PCL TOSU TOSH or TOSL as the destination register Words 2 Cycles 2 3 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f src Process Data No operation Decode No operation No dummy read No operation Write register f dest Example MOVFF REG1 REG2 Before Instruction REG1 33h REG2 11h After Instruction REG1 33h REG2 33h MOVLB Move Literal to Low Nibble in BSR Syntax MOVLW k Operands 0 k 255 Operation k BSR Status Affected None Encoding 0000 0001 kkkk kkkk Description The 8bit literal k is loaded into the Bank Select Register BSR The value of BSR74 always remains 0 regardless of the value of k7k4 Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write literal k to BSR Example MOVLB 5 Before Instruction BSR Register 02h After Instruction BSR Register 05h 2008 Microchip Technology Inc DS39631Epage 293 PIC18F2420252044204520 MOVLW Move Literal to W Syntax MOVLW k Operands 0 k 255 Operation k W Status Affected None Encoding 0000 1110 kkkk kkkk Description The 8bit literal k is loaded into W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to W Example MOVLW 5Ah After Instruction W 5Ah MOVWF Move W to f Syntax MOVWF f a Operands 0 f 255 a 01 Operation W f Status Affected None Encoding 0110 111a ffff ffff Description Move data from W to register f Location f can be anywhere in the 256byte bank If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write register f Example MOVWF REG 0 Before Instruction W 4Fh REG FFh After Instruction W 4Fh REG 4Fh PIC18F2420252044204520 DS39631Epage 294 2008 Microchip Technology Inc MULLW Multiply Literal with W Syntax MULLW k Operands 0 k 255 Operation W x k PRODHPRODL Status Affected None Encoding 0000 1101 kkkk kkkk Description An unsigned multiplication is carried out between the contents of W and the 8bit literal k The 16bit result is placed in the PRODHPRODL register pair PRODH contains the high byte W is unchanged None of the Status flags are affected Note that neither Overflow nor Carry is possible in this operation A zero result is possible but not detected Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write registers PRODH PRODL Example MULLW 0C4h Before Instruction W E2h PRODH PRODL After Instruction W E2h PRODH ADh PRODL 08h MULWF Multiply W with f Syntax MULWF f a Operands 0 f 255 a 01 Operation W x f PRODHPRODL Status Affected None Encoding 0000 001a ffff ffff Description An unsigned multiplication is carried out between the contents of W and the register file location f The 16bit result is stored in the PRODHPRODL register pair PRODH contains the high byte Both W and f are unchanged None of the Status flags are affected Note that neither Overflow nor Carry is possible in this operation A zero result is possible but not detected If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write registers PRODH PRODL Example MULWF REG 1 Before Instruction W C4h REG B5h PRODH PRODL After Instruction W C4h REG B5h PRODH 8Ah PRODL 94h 2008 Microchip Technology Inc DS39631Epage 295 PIC18F2420252044204520 NEGF Negate f Syntax NEGF f a Operands 0 f 255 a 01 Operation f 1 f Status Affected N OV C DC Z Encoding 0110 110a ffff ffff Description Location f is negated using twos complement The result is placed in the data memory location f If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write register f Example NEGF REG 1 Before Instruction REG 0011 1010 3Ah After Instruction REG 1100 0110 C6h NOP No Operation Syntax NOP Operands None Operation No operation Status Affected None Encoding 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx Description No operation Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example None PIC18F2420252044204520 DS39631Epage 296 2008 Microchip Technology Inc POP Pop Top of Return Stack Syntax POP Operands None Operation TOS bit bucket Status Affected None Encoding 0000 0000 0000 0110 Description The TOS value is pulled off the return stack and is discarded The TOS value then becomes the previous value that was pushed onto the return stack This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation POP TOS value No operation Example POP GOTO NEW Before Instruction TOS 0031A2h Stack 1 level down 014332h After Instruction TOS 014332h PC NEW PUSH Push Top of Return Stack Syntax PUSH Operands None Operation PC 2 TOS Status Affected None Encoding 0000 0000 0000 0101 Description The PC 2 is pushed onto the top of the return stack The previous TOS value is pushed down on the stack This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode PUSH PC 2 onto return stack No operation No operation Example PUSH Before Instruction TOS 345Ah PC 0124h After Instruction PC 0126h TOS 0126h Stack 1 level down 345Ah 2008 Microchip Technology Inc DS39631Epage 297 PIC18F2420252044204520 RCALL Relative Call Syntax RCALL n Operands 1024 n 1023 Operation PC 2 TOS PC 2 2n PC Status Affected None Encoding 1101 1nnn nnnn nnnn Description Subroutine call with a jump up to 1K from the current location First return address PC 2 is pushed onto the stack Then add the 2s complement number 2n to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is a twocycle instruction Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal n PUSH PC to stack Process Data Write to PC No operation No operation No operation No operation Example HERE RCALL Jump Before Instruction PC Address HERE After Instruction PC Address Jump TOS Address HERE 2 RESET Reset Syntax RESET Operands None Operation Reset all registers and flags that are affected by a MCLR Reset Status Affected All Encoding 0000 0000 1111 1111 Description This instruction provides a way to execute a MCLR Reset in software Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example RESET After Instruction Registers Reset Value Flags Reset Value PIC18F2420252044204520 DS39631Epage 298 2008 Microchip Technology Inc RETFIE Return from Interrupt Syntax RETFIE s Operands s 01 Operation TOS PC 1 GIEGIEH or PEIEGIEL if s 1 WS W STATUSS STATUS BSRS BSR PCLATU PCLATH are unchanged Status Affected GIEGIEH PEIEGIEL Encoding 0000 0000 0001 000s Description Return from interrupt Stack is popped and TopofStack TOS is loaded into the PC Interrupts are enabled by setting either the high or lowpriority global interrupt enable bit If s 1 the contents of the shadow registers WS STATUSS and BSRS are loaded into their corresponding registers W STATUS and BSR If s 0 no update of these registers occurs default Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL No operation No operation No operation No operation Example RETFIE 1 After Interrupt PC TOS W WS BSR BSRS STATUS STATUSS GIEGIEH PEIEGIEL 1 RETLW Return Literal to W Syntax RETLW k Operands 0 k 255 Operation k W TOS PC PCLATU PCLATH are unchanged Status Affected None Encoding 0000 1100 kkkk kkkk Description W is loaded with the 8bit literal k The program counter is loaded from the top of the stack the return address The high address latch PCLATH remains unchanged Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data POP PC from stack Write to W No operation No operation No operation No operation Example CALL TABLE W contains table offset value W now has table value TABLE ADDWF PCL W offset RETLW k0 Begin table RETLW k1 RETLW kn End of table Before Instruction W 07h After Instruction W value of kn 2008 Microchip Technology Inc DS39631Epage 299 PIC18F2420252044204520 RETURN Return from Subroutine Syntax RETURN s Operands s 01 Operation TOS PC if s 1 WS W STATUSS STATUS BSRS BSR PCLATU PCLATH are unchanged Status Affected None Encoding 0000 0000 0001 001s Description Return from subroutine The stack is popped and the top of the stack TOS is loaded into the program counter If s 1 the contents of the shadow registers WS STATUSS and BSRS are loaded into their corresponding registers W STATUS and BSR If s 0 no update of these registers occurs default Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation Process Data POP PC from stack No operation No operation No operation No operation Example RETURN After Instruction PC TOS RLCF Rotate Left f through Carry Syntax RLCF f d a Operands 0 f 255 d 01 a 01 Operation fn destn 1 f7 C C dest0 Status Affected C N Z Encoding 0011 01da ffff ffff Description The contents of register f are rotated one bit to the left through the Carry flag If d is 0 the result is placed in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example RLCF REG 0 0 Before Instruction REG 1110 0110 C 0 After Instruction REG 1110 0110 W 1100 1100 C 1 C register f PIC18F2420252044204520 DS39631Epage 300 2008 Microchip Technology Inc RLNCF Rotate Left f No Carry Syntax RLNCF f d a Operands 0 f 255 d 01 a 01 Operation fn destn 1 f7 dest0 Status Affected N Z Encoding 0100 01da ffff ffff Description The contents of register f are rotated one bit to the left If d is 0 the result is placed in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example RLNCF REG 1 0 Before Instruction REG 1010 1011 After Instruction REG 0101 0111 register f RRCF Rotate Right f through Carry Syntax RRCF f d a Operands 0 f 255 d 01 a 01 Operation fn destn 1 f0 C C dest7 Status Affected C N Z Encoding 0011 00da ffff ffff Description The contents of register f are rotated one bit to the right through the Carry flag If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example RRCF REG 0 0 Before Instruction REG 1110 0110 C 0 After Instruction REG 1110 0110 W 0111 0011 C 0 C register f 2008 Microchip Technology Inc DS39631Epage 301 PIC18F2420252044204520 RRNCF Rotate Right f No Carry Syntax RRNCF f d a Operands 0 f 255 d 01 a 01 Operation fn destn 1 f0 dest7 Status Affected N Z Encoding 0100 00da ffff ffff Description The contents of register f are rotated one bit to the right If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example 1 RRNCF REG 1 0 Before Instruction REG 1101 0111 After Instruction REG 1110 1011 Example 2 RRNCF REG 0 0 Before Instruction W REG 1101 0111 After Instruction W 1110 1011 REG 1101 0111 register f SETF Set f Syntax SETF f a Operands 0 f 255 a 01 Operation FFh f Status Affected None Encoding 0110 100a ffff ffff Description The contents of the specified register are set to FFh If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write register f Example SETF REG 1 Before Instruction REG 5Ah After Instruction REG FFh PIC18F2420252044204520 DS39631Epage 302 2008 Microchip Technology Inc SLEEP Enter Sleep mode Syntax SLEEP Operands None Operation 00h WDT 0 WDT postscaler 1 TO 0 PD Status Affected TO PD Encoding 0000 0000 0000 0011 Description The PowerDown status bit PD is cleared The Timeout status bit TO is set Watchdog Timer and its post scaler are cleared The processor is put into Sleep mode with the oscillator stopped Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep Example SLEEP Before Instruction TO PD After Instruction TO 1 PD 0 If WDT causes wakeup this bit is cleared SUBFWB Subtract f from W with Borrow Syntax SUBFWB f d a Operands 0 f 255 d 01 a 01 Operation W f C dest Status Affected N OV C DC Z Encoding 0101 01da ffff ffff Description Subtract register f and Carry flag borrow from W 2s complement method If d is 0 the result is stored in W If d is 1 the result is stored in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example 1 SUBFWB REG 1 0 Before Instruction REG 3 W 2 C 1 After Instruction REG FF W 2 C 0 Z 0 N 1 result is negative Example 2 SUBFWB REG 0 0 Before Instruction REG 2 W 5 C 1 After Instruction REG 2 W 3 C 1 Z 0 N 0 result is positive Example 3 SUBFWB REG 1 0 Before Instruction REG 1 W 2 C 0 After Instruction REG 0 W 2 C 1 Z 1 result is zero N 0 2008 Microchip Technology Inc DS39631Epage 303 PIC18F2420252044204520 SUBLW Subtract W from Literal Syntax SUBLW k Operands 0 k 255 Operation k W W Status Affected N OV C DC Z Encoding 0000 1000 kkkk kkkk Description W is subtracted from the 8bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to W Example 1 SUBLW 02h Before Instruction W 01h C After Instruction W 01h C 1 result is positive Z 0 N 0 Example 2 SUBLW 02h Before Instruction W 02h C After Instruction W 00h C 1 result is zero Z 1 N 0 Example 3 SUBLW 02h Before Instruction W 03h C After Instruction W FFh 2s complement C 0 result is negative Z 0 N 1 SUBWF Subtract W from f Syntax SUBWF f d a Operands 0 f 255 d 01 a 01 Operation f W dest Status Affected N OV C DC Z Encoding 0101 11da ffff ffff Description Subtract W from register f 2s complement method If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example 1 SUBWF REG 1 0 Before Instruction REG 3 W 2 C After Instruction REG 1 W 2 C 1 result is positive Z 0 N 0 Example 2 SUBWF REG 0 0 Before Instruction REG 2 W 2 C After Instruction REG 2 W 0 C 1 result is zero Z 1 N 0 Example 3 SUBWF REG 1 0 Before Instruction REG 1 W 2 C After Instruction REG FFh 2s complement W 2 C 0 result is negative Z 0 N 1 PIC18F2420252044204520 DS39631Epage 304 2008 Microchip Technology Inc SUBWFB Subtract W from f with Borrow Syntax SUBWFB f d a Operands 0 f 255 d 01 a 01 Operation f W C dest Status Affected N OV C DC Z Encoding 0101 10da ffff ffff Description Subtract W and the Carry flag borrow from register f 2s complement method If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example 1 SUBWFB REG 1 0 Before Instruction REG 19h 0001 1001 W 0Dh 0000 1101 C 1 After Instruction REG 0Ch 0000 1011 W 0Dh 0000 1101 C 1 Z 0 N 0 result is positive Example 2 SUBWFB REG 0 0 Before Instruction REG 1Bh 0001 1011 W 1Ah 0001 1010 C 0 After Instruction REG 1Bh 0001 1011 W 00h C 1 Z 1 result is zero N 0 Example 3 SUBWFB REG 1 0 Before Instruction REG 03h 0000 0011 W 0Eh 0000 1101 C 1 After Instruction REG F5h 1111 0100 2s comp W 0Eh 0000 1101 C 0 Z 0 N 1 result is negative SWAPF Swap f Syntax SWAPF f d a Operands 0 f 255 d 01 a 01 Operation f30 dest74 f74 dest30 Status Affected None Encoding 0011 10da ffff ffff Description The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in W If d is 1 the result is placed in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example SWAPF REG 1 0 Before Instruction REG 53h After Instruction REG 35h 2008 Microchip Technology Inc DS39631Epage 305 PIC18F2420252044204520 TBLRD Table Read Syntax TBLRD Operands None Operation if TBLRD Prog Mem TBLPTR TABLAT TBLPTR No Change if TBLRD Prog Mem TBLPTR TABLAT TBLPTR 1 TBLPTR if TBLRD Prog Mem TBLPTR TABLAT TBLPTR 1 TBLPTR if TBLRD TBLPTR 1 TBLPTR Prog Mem TBLPTR TABLAT Status Affected None Encoding 0000 0000 0000 10nn nn0 1 2 3 Description This instruction is used to read the contents of Program Memory PM To address the program memory a pointer called Table Pointer TBLPTR is used The TBLPTR a 21bit pointer points to each byte in the program memory TBLPTR has a 2Mbyte address range TBLPTR0 0Least Significant Byte of Program Memory Word TBLPTR0 1Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows no change postincrement postdecrement preincrement Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation Read Program Memory No operation No operation Write TABLAT TBLRD Table Read Continued Example1 TBLRD Before Instruction TABLAT 55h TBLPTR 00A356h MEMORY 00A356h 34h After Instruction TABLAT 34h TBLPTR 00A357h Example2 TBLRD Before Instruction TABLAT AAh TBLPTR 01A357h MEMORY 01A357h 12h MEMORY 01A358h 34h After Instruction TABLAT 34h TBLPTR 01A358h PIC18F2420252044204520 DS39631Epage 306 2008 Microchip Technology Inc TBLWT Table Write Syntax TBLWT Operands None Operation if TBLWT TABLAT Holding Register TBLPTR No Change if TBLWT TABLAT Holding Register TBLPTR 1 TBLPTR if TBLWT TABLAT Holding Register TBLPTR 1 TBLPTR if TBLWT TBLPTR 1 TBLPTR TABLAT Holding Register Status Affected None Encoding 0000 0000 0000 11nn nn0 1 2 3 Description This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to The holding registers are used to program the contents of Program Memory PM Refer to Section 60 Flash Program Memory for additional details on programming Flash memory The TBLPTR a 21bit pointer points to each byte in the program memory TBLPTR has a 2MByte address range The LSb of the TBLPTR selects which byte of the program memory location to access TBLPTR0 0Least Significant Byte of Program Memory Word TBLPTR0 1Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows no change postincrement postdecrement preincrement Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation Read TABLAT No operation No operation Write to Holding Register TBLWT Table Write Continued Example1 TBLWT Before Instruction TABLAT 55h TBLPTR 00A356h HOLDING REGISTER 00A356h FFh After Instructions table write completion TABLAT 55h TBLPTR 00A357h HOLDING REGISTER 00A356h 55h Example 2 TBLWT Before Instruction TABLAT 34h TBLPTR 01389Ah HOLDING REGISTER 01389Ah FFh HOLDING REGISTER 01389Bh FFh After Instruction table write completion TABLAT 34h TBLPTR 01389Bh HOLDING REGISTER 01389Ah FFh HOLDING REGISTER 01389Bh 34h 2008 Microchip Technology Inc DS39631Epage 307 PIC18F2420252044204520 TSTFSZ Test f Skip if 0 Syntax TSTFSZ f a Operands 0 f 255 a 01 Operation skip if f 0 Status Affected None Encoding 0110 011a ffff ffff Description If f 0 the next instruction fetched during the current instruction execution is discarded and a NOP is executed making this a twocycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 12 Note 3 cycles if skip and followed by a 2word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data No operation If skip Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2word instruction Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example HERE TSTFSZ CNT 1 NZERO ZERO Before Instruction PC Address HERE After Instruction If CNT 00h PC Address ZERO If CNT 00h PC Address NZERO XORLW Exclusive OR Literal with W Syntax XORLW k Operands 0 k 255 Operation W XOR k W Status Affected N Z Encoding 0000 1010 kkkk kkkk Description The contents of W are XORed with the 8bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to W Example XORLW 0AFh Before Instruction W B5h After Instruction W 1Ah PIC18F2420252044204520 DS39631Epage 308 2008 Microchip Technology Inc XORWF Exclusive OR W with f Syntax XORWF f d a Operands 0 f 255 d 01 a 01 Operation W XOR f dest Status Affected N Z Encoding 0001 10da ffff ffff Description Exclusive OR the contents of W with register f If d is 0 the result is stored in W If d is 1 the result is stored back in the register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 5Fh See Section 2423 ByteOriented and BitOriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example XORWF REG 1 0 Before Instruction REG AFh W B5h After Instruction REG 1Ah W B5h 2008 Microchip Technology Inc DS39631Epage 309 PIC18F2420252044204520 242 Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set PIC18F2420252044204520 devices also provide an optional extension to the core CPU functionality The added features include eight addi tional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions The additional features of the extended instruction set are disabled by default To enable them users must set the XINST Configuration bit The instructions in the extended set can all be classified as literal operations which either manipulate the File Select Registers or use them for indexed addressing Two of the instructions ADDFSR and SUBFSR each have an additional special instantiation for using FSR2 These versions ADDULNK and SUBULNK allow for automatic return after execution The extended instructions are specifically implemented to optimize reentrant program code that is code that is recursive or that uses a software stack written in highlevel languages particularly C Among other things they allow users working in highlevel languages to perform certain operations on data structures more efficiently These include Dynamic allocation and deallocation of software stack space when entering and leaving subroutines Function Pointer invocation Software Stack Pointer manipulation Manipulation of variables located in a software stack A summary of the instructions in the extended instruc tion set is provided in Table 243 Detailed descriptions are provided in Section 2422 Extended Instruction Set The opcode field descriptions in Table 241 page 268 apply to both the standard and extended PIC18 instruction sets 2421 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed argu ments using one of the File Select Registers and some offset to specify a source or destination register When an argument for an instruction serves as part of indexed addressing it is enclosed in square brackets This is done to indicate that the argument is used as an index or offset MPASM Assembler will flag an error if it determines that an index or offset value is not bracketed When the extended instruction set is enabled brackets are also used to indicate index arguments in byte oriented and bitoriented instructions This is in addition to other changes in their syntax For more details see Section 24231 Extended Instruction Syntax with Standard PIC18 Commands TABLE 243 EXTENSIONS TO THE PIC18 INSTRUCTION SET Note The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C the user may likely never use these instructions directly in assembler The syntax for these commands is pro vided as a reference for users who may be reviewing code that has been generated by a compiler Note In the past square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets In this text and going forward optional arguments are denoted by braces Mnemonic Operands Description Cycles 16Bit Instruction Word Status Affected MSb LSb ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f k k zs fd zs zd k f k k Add Literal to FSR Add Literal to FSR2 and Return Call Subroutine using WREG Move zs source to 1st word fd destination 2nd word Move zs source to 1st word zd destination 2nd word Store Literal at FSR2 Decrement FSR2 Subtract Literal from FSR Subtract Literal from FSR2 and Return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk None None None None None None None None PIC18F2420252044204520 DS39631Epage 310 2008 Microchip Technology Inc 2422 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR Syntax ADDFSR f k Operands 0 k 63 f 0 1 2 Operation FSRf k FSRf Status Affected None Encoding 1110 1000 ffkk kkkk Description The 6bit literal k is added to the contents of the FSR specified by f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to FSR Example ADDFSR 2 23h Before Instruction FSR2 03FFh After Instruction FSR2 0422h ADDULNK Add Literal to FSR2 and Return Syntax ADDULNK k Operands 0 k 63 Operation FSR2 k FSR2 TOS PC Status Affected None Encoding 1110 1000 11kk kkkk Description The 6bit literal k is added to the contents of FSR2 A RETURN is then executed by loading the PC with the TOS The instruction takes two cycles to execute a NOP is performed during the second cycle This may be thought of as a special case of the ADDFSR instruction where f 3 binary 11 it operates only on FSR2 Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal k Process Data Write to FSR No Operation No Operation No Operation No Operation Example ADDULNK 23h Before Instruction FSR2 03FFh PC 0100h After Instruction FSR2 0422h PC TOS Note All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing If a label is used the instruction syntax then becomes label instruction arguments 2008 Microchip Technology Inc DS39631Epage 311 PIC18F2420252044204520 CALLW Subroutine Call Using WREG Syntax CALLW Operands None Operation PC 2 TOS W PCL PCLATH PCH PCLATU PCU Status Affected None Encoding 0000 0000 0001 0100 Description First the return address PC 2 is pushed onto the return stack Next the contents of W are written to PCL the existing value is discarded Then the contents of PCLATH and PCLATU are latched into PCH and PCU respectively The second cycle is executed as a NOP instruction while the new next instruction is fetched Unlike CALL there is no option to update W STATUS or BSR Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read WREG PUSH PC to stack No operation No operation No operation No operation No operation Example HERE CALLW Before Instruction PC address HERE PCLATH 10h PCLATU 00h W 06h After Instruction PC 001006h TOS address HERE 2 PCLATH 10h PCLATU 00h W 06h MOVSF Move Indexed to f Syntax MOVSF zs fd Operands 0 zs 127 0 fd 4095 Operation FSR2 zs fd Status Affected None Encoding 1st word source 2nd word destin 1110 1111 1011 ffff 0zzz ffff zzzzs ffffd Description The contents of the source register are moved to destination register fd The actual address of the source register is determined by adding the 7bit literal offset zs in the first word to the value of FSR2 The address of the destination register is specified by the 12bit literal fd in the second word Both addresses can be anywhere in the 4096byte data space 000h to FFFh The MOVSF instruction cannot use the PCL TOSU TOSH or TOSL as the destination register If the resultant source address points to an indirect addressing register the value returned will be 00h Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Determine source addr Determine source addr Read source reg Decode No operation No dummy read No operation Write register f dest Example MOVSF 05h REG2 Before Instruction FSR2 80h Contents of 85h 33h REG2 11h After Instruction FSR2 80h Contents of 85h 33h REG2 33h PIC18F2420252044204520 DS39631Epage 312 2008 Microchip Technology Inc MOVSS Move Indexed to Indexed Syntax MOVSS zs zd Operands 0 zs 127 0 zd 127 Operation FSR2 zs FSR2 zd Status Affected None Encoding 1st word source 2nd word dest 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd Description The contents of the source register are moved to the destination register The addresses of the source and destination registers are determined by adding the 7bit literal offsets zs or zd respectively to the value of FSR2 Both registers can be located anywhere in the 4096byte data memory space 000h to FFFh The MOVSS instruction cannot use the PCL TOSU TOSH or TOSL as the destination register If the resultant source address points to an indirect addressing register the value returned will be 00h If the resultant destination address points to an indirect addressing register the instruction will execute as a NOP Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Determine source addr Determine source addr Read source reg Decode Determine dest addr Determine dest addr Write to dest reg Example MOVSS 05h 06h Before Instruction FSR2 80h Contents of 85h 33h Contents of 86h 11h After Instruction FSR2 80h Contents of 85h 33h Contents of 86h 33h PUSHL Store Literal at FSR2 Decrement FSR2 Syntax PUSHL k Operands 0 k 255 Operation k FSR2 FSR2 1 FSR2 Status Affected None Encoding 1111 1010 kkkk kkkk Description The 8bit literal k is written to the data memory address specified by FSR2 FSR2 is decremented by 1 after the operation This instruction allows users to push values onto a software stack Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read k Process data Write to destination Example PUSHL 08h Before Instruction FSR2HFSR2L 01ECh Memory 01ECh 00h After Instruction FSR2HFSR2L 01EBh Memory 01ECh 08h 2008 Microchip Technology Inc DS39631Epage 313 PIC18F2420252044204520 SUBFSR Subtract Literal from FSR Syntax SUBFSR f k Operands 0 k 63 f 0 1 2 Operation FSRf k FSRf Status Affected None Encoding 1110 1001 ffkk kkkk Description The 6bit literal k is subtracted from the contents of the FSR specified by f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example SUBFSR 2 23h Before Instruction FSR2 03FFh After Instruction FSR2 03DCh SUBULNK Subtract Literal from FSR2 and Return Syntax SUBULNK k Operands 0 k 63 Operation FSR2 k FSR2 TOS PC Status Affected None Encoding 1110 1001 11kk kkkk Description The 6bit literal k is subtracted from the contents of the FSR2 A RETURN is then executed by loading the PC with the TOS The instruction takes two cycles to execute a NOP is performed during the second cycle This may be thought of as a special case of the SUBFSR instruction where f 3 binary 11 it operates only on FSR2 Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination No Operation No Operation No Operation No Operation Example SUBULNK 23h Before Instruction FSR2 03FFh PC 0100h After Instruction FSR2 03DCh PC TOS PIC18F2420252044204520 DS39631Epage 314 2008 Microchip Technology Inc 2423 BYTEORIENTED AND BITORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE In addition to eight new commands in the extended set enabling the extended instruction set also enables Indexed Literal Offset Addressing mode Section 551 Indexed Addressing with Literal Offset This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted When the extended set is disabled addresses embed ded in opcodes are treated as literal memory locations either as a location in the Access Bank a 0 or in a GPR bank designated by the BSR a 1 When the extended instruction set is enabled and a 0 how ever a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address For practical purposes this means that all instructions that use the Access RAM bit as an argument that is all byteoriented and bit oriented instructions or almost half of the core PIC18 instructions may behave differently when the extended instruction set is enabled When the content of FSR2 is 00h the boundaries of the Access RAM are essentially remapped to their original values This may be useful in creating backward compatible code If this technique is used it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer Users must also keep in mind the syntax requirements of the extended instruction set see Section 24231 Extended Instruction Syntax with Standard PIC18 Commands Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation it can also be very annoying if a simple arithmetic operation is carried out on the wrong register Users who are accustomed to the PIC18 pro gramming must keep in mind that when the extended instruction set is enabled register addresses of 5Fh or less are used for Indexed Literal Offset Addressing Representative examples of typical byteoriented and bitoriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected The operand condi tions shown in the examples are applicable to all instructions of these types 24231 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled the file register argument f in the standard byteoriented and bitoriented commands is replaced with the literal offset value k As already noted this occurs only when f is less than or equal to 5Fh When an offset value is used it must be indicated by square brackets As with the extended instructions the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset Omitting the brackets or using a value greater than 5Fh within brackets will generate an error in the MPASM Assembler If the index argument is properly bracketed for Indexed Literal Offset Addressing the Access RAM argument is never specified it will automatically be assumed to be 0 This is in contrast to standard operation extended instruction set disabled when a is set on the basis of the target address Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler The destination argument d functions as before In the latest versions of the MPASM assembler language support for the extended instruction set must be explicitly invoked This is done with either the command line option y or the PE directive in the source listing 2424 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruc tion set may not be beneficial to all users In particular users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set Additionally the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled the application may read or write to the wrong data addresses When porting an application to the PIC18F24202520 44204520 it is very important to consider the type of code A large reentrant application that is written in C and would benefit from efficient compilation will do well when using the instruction set extensions Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set Note Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely 2008 Microchip Technology Inc DS39631Epage 315 PIC18F2420252044204520 ADDWF ADD W to Indexed Indexed Literal Offset mode Syntax ADDWF k d Operands 0 k 95 d 01 Operation W FSR2 k dest Status Affected N OV C DC Z Encoding 0010 01d0 kkkk kkkk Description The contents of W are added to the contents of the register indicated by FSR2 offset by the value k If d is 0 the result is stored in W If d is 1 the result is stored back in register f default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read k Process Data Write to destination Example ADDWF OFST 0 Before Instruction W 17h OFST 2Ch FSR2 0A00h Contents of 0A2Ch 20h After Instruction W 37h Contents of 0A2Ch 20h BSF Bit Set Indexed Indexed Literal Offset mode Syntax BSF k b Operands 0 f 95 0 b 7 Operation 1 FSR2 kb Status Affected None Encoding 1000 bbb0 kkkk kkkk Description Bit b of the register indicated by FSR2 offset by the value k is set Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read register f Process Data Write to destination Example BSF FLAGOFST 7 Before Instruction FLAGOFST 0Ah FSR2 0A00h Contents of 0A0Ah 55h After Instruction Contents of 0A0Ah D5h SETF Set Indexed Indexed Literal Offset mode Syntax SETF k Operands 0 k 95 Operation FFh FSR2 k Status Affected None Encoding 0110 1000 kkkk kkkk Description The contents of the register indicated by FSR2 offset by k are set to FFh Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read k Process Data Write register Example SETF OFST Before Instruction OFST 2Ch FSR2 0A00h Contents of 0A2Ch 00h After Instruction Contents of 0A2Ch FFh PIC18F2420252044204520 DS39631Epage 316 2008 Microchip Technology Inc 2425 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB IDE TOOLS The latest versions of Microchips software tools have been designed to fully support the extended instruction set of the PIC18F2420252044204520 family of devices This includes the MPLAB C18 C compiler MPASM assembly language and MPLAB Integrated Development Environment IDE When selecting a target device for software development MPLAB IDE will automatically set default Configuration bits for that device The default setting for the XINST Configuration bit is 0 disabling the extended instruction set and Indexed Literal Offset Addressing mode For proper execution of applications developed to take advantage of the extended instruction set XINST must be set during programming To develop software for the extended instruction set the user must enable support for the instructions and the Indexed Addressing mode in their language tools Depending on the environment being used this may be done in several ways A menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project A command line option A directive in the source code These options vary between different compilers assemblers and development environments Users are encouraged to review the documentation accompany ing their development systems for the appropriate information 2008 Microchip Technology Inc DS39631Epage 317 PIC18F2420252044204520 250 DEVELOPMENT SUPPORT The PIC microcontrollers are supported with a full range of hardware and software development tools Integrated Development Environment MPLAB IDE Software AssemblersCompilersLinkers MPASMTM Assembler MPLAB C18 and MPLAB C30 C Compilers MPLINKTM Object Linker MPLIBTM Object Librarian MPLAB ASM30 AssemblerLinkerLibrary Simulators MPLAB SIM Software Simulator Emulators MPLAB ICE 2000 InCircuit Emulator MPLAB REAL ICE InCircuit Emulator InCircuit Debugger MPLAB ICD 2 Device Programmers PICSTART Plus Development Programmer MPLAB PM3 Device Programmer PICkit 2 Development Programmer LowCost Demonstration and Development Boards and Evaluation Kits 251 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 816bit micro controller market The MPLAB IDE is a Windows operating systembased application that contains A single graphical interface to all debugging tools Simulator Programmer sold separately Emulator sold separately InCircuit Debugger sold separately A fullfeatured editor with colorcoded context A multiple project manager Customizable data windows with direct edit of contents Highlevel source code debugging Visual device initializer for easy register initialization Mouse over variable inspection Drag and drop variables from source to watch windows Extensive online help Integration of select third party tools such as HITECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to Edit your source files either assembly or C One touch assemble or compile and download to PIC MCU emulator and simulator tools automatically updates all project information Debug using Source files assembly or C Mixed assembly and C Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm from the costeffective simulators through lowcost incircuit debuggers to fullfeatured emulators This eliminates the learning curve when upgrading to tools with increased flexibility and power PIC18F2420252044204520 DS39631Epage 318 2008 Microchip Technology Inc 252 MPASM Assembler The MPASM Assembler is a fullfeatured universal macro assembler for all PIC MCUs The MPASM Assembler generates relocatable object files for the MPLINK Object Linker Intel standard HEX files MAP files to detail memory usage and symbol reference absolute LST files that contain source lines and generated machine code and COFF files for debugging The MPASM Assembler features include Integration into MPLAB IDE projects Userdefined macros to streamline assembly code Conditional assembly for multipurpose source files Directives that allow complete control over the assembly process 253 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchips PIC18 and PIC24 families of microcon trollers and the dsPIC30 and dsPIC33 family of digital signal controllers These compilers provide powerful integration capabilities superior code optimization and ease of use not found with other compilers For easy source level debugging the compilers provide symbol information that is optimized to the MPLAB IDE debugger 254 MPLINK Object Linker MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler It can link relocatable objects from precompiled libraries using directives from a linker script The MPLIB Object Librarian manages the creation and modification of library files of precompiled code When a routine from a library is called from a source file only the modules that contain that routine will be linked in with the application This allows large libraries to be used efficiently in many different applications The object linkerlibrary features include Efficient linking of single libraries instead of many smaller files Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing replacement deletion and extraction 255 MPLAB ASM30 Assembler Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices MPLAB C30 C Compiler uses the assembler to produce its object file The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file Notable features of the assembler include Support for the entire dsPIC30F instruction set Support for fixedpoint and floatingpoint data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 256 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PChosted environment by simulat ing the PIC MCUs and dsPIC DSCs on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller Registers can be logged to files for further runtime analysis The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution actions on IO most peripherals and internal registers The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers and the MPASM and MPLAB ASM30 Assemblers The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment making it an excellent economical software development tool 2008 Microchip Technology Inc DS39631Epage 319 PIC18F2420252044204520 257 MPLAB ICE 2000 HighPerformance InCircuit Emulator The MPLAB ICE 2000 InCircuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers Software control of the MPLAB ICE 2000 InCircuit Emulator is advanced by the MPLAB Integrated Development Environment which allows editing building downloading and source debugging from a single environment The MPLAB ICE 2000 is a fullfeatured emulator system with enhanced trace trigger and data monitor ing features Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors The architecture of the MPLAB ICE 2000 InCircuit Emulator allows expansion to support new PIC microcontrollers The MPLAB ICE 2000 InCircuit Emulator system has been designed as a realtime emulation system with advanced features that are typically found on more expensive development tools The PC platform and Microsoft Windows 32bit operating system were chosen to best make these features available in a simple unified application 258 MPLAB REAL ICE InCircuit Emulator System MPLAB REAL ICE InCircuit Emulator System is Microchips next generation highspeed emulator for Microchip Flash DSC and MCU devices It debugs and programs PIC Flash MCUs and dsPIC Flash DSCs with the easytouse powerful graphical user interface of the MPLAB Integrated Development Environment IDE included with each kit The MPLAB REAL ICE probe is connected to the design engineers PC using a highspeed USB 20 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system RJ11 or with the new highspeed noise tolerant Low Voltage Differential Signal LVDS interconnection CAT5 MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE In upcoming releases of MPLAB IDE new devices will be supported and new features will be added such as software break points and assembly code trace MPLAB REAL ICE offers significant advantages over competitive emulators including lowcost fullspeed emulation realtime variable watches trace analysis complex breakpoints a ruggedized probe interface and long up to three meters interconnection cables 259 MPLAB ICD 2 InCircuit Debugger Microchips InCircuit Debugger MPLAB ICD 2 is a powerful lowcost runtime development tool connecting to the host PC via an RS232 or highspeed USB interface This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs The MPLAB ICD 2 utilizes the incircuit debugging capability built into the Flash devices This feature along with Microchips InCircuit Serial ProgrammingTM ICSPTM protocol offers cost effective incircuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment This enables a designer to develop and debug source code by setting breakpoints single step ping and watching variables and CPU status and peripheral registers Running at full speed enables testing hardware and applications in real time MPLAB ICD 2 also serves as a development programmer for selected PIC devices 2510 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability It features a large LCD display 128 x 64 for menus and error messages and a modu lar detachable socket assembly to support various package types The ICSP cable assembly is included as a standard item In StandAlone mode the MPLAB PM3 Device Programmer can read verify and program PIC devices without a PC connection It can also set code protection in this mode The MPLAB PM3 connects to the host PC via an RS232 or USB cable The MPLAB PM3 has highspeed communications and optimized algorithms for quick programming of large memory devices and incorporates an SDMMC card for file storage and secure data applications PIC18F2420252044204520 DS39631Epage 320 2008 Microchip Technology Inc 2511 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easytouse lowcost prototype programmer It connects to the PC via a COM RS232 port MPLAB Integrated Development Environment software makes using the programmer simple and efficient The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins Larger pin count devices such as the PIC16C92X and PIC17C76X may be supported with an adapter socket The PICSTART Plus Development Programmer is CE compliant 2512 PICkit 2 Development Programmer The PICkit 2 Development Programmer is a lowcost programmer and selected Flash device debugger with an easytouse interface for programming many of Microchips baseline midrange and PIC18F families of Flash memory microcontrollers The PICkit 2 Starter Kit includes a prototyping development board twelve sequential lessons software and HITECHs PICC Lite C compiler and is designed to help get up to speed quickly using PIC microcontrollers The kit provides everything needed to program evaluate and develop applications using Microchips powerful midrange Flash memory family of microcontrollers 2513 Demonstration Development and Evaluation Boards A wide variety of demonstration development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully func tional systems Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification The boards support a variety of features including LEDs temperature sensors switches speakers RS232 interfaces LCD displays potentiometers and additional EEPROM memory The demonstration and development boards can be used in teaching environments for prototyping custom circuits and for learning about various microcontroller applications In addition to the PICDEM and dsPICDEM demon strationdevelopment board series of circuits Microchip has a line of evaluation kits and demonstration software for analog filter design KEELOQ security ICs CAN IrDA PowerSmart battery management SEEVAL evaluation system SigmaDelta ADC flow rate sensing plus many more Check the Microchip web page wwwmicrochipcom for the complete list of demonstration development and evaluation kits 2008 Microchip Technology Inc DS39631Epage 321 PIC18F2420252044204520 260 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias40C to 125C Storage temperature 65C to 150C Voltage on any pin with respect to VSS except VDD and MCLR 03V to VDD 03V Voltage on VDD with respect to VSS 03V to 75V Voltage on MCLR with respect to VSS Note 2 0V to 1325V Total power dissipation Note 1 10W Maximum current out of VSS pin 300 mA Maximum current into VDD pin 250 mA Input clamp current IIK VI 0 or VI VDD 20 mA Output clamp current IOK VO 0 or VO VDD 20 mA Maximum output current sunk by any IO pin25 mA Maximum output current sourced by any IO pin 25 mA Maximum current sunk by all ports 200 mA Maximum current sourced by all ports 200 mA Note 1 Power dissipation is calculated as follows Pdis VDD x IDD IOH VDD VOH x IOH VOL x IOL 2 Voltage spikes below VSS at the MCLRVPPRE3 pin inducing currents greater than 80 mA may cause latchup Thus a series resistor of 50100Ω should be used when applying a low level to the MCLRVPP RE3 pin rather than pulling this pin directly to VSS NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability PIC18F2420252044204520 DS39631Epage 322 2008 Microchip Technology Inc FIGURE 261 PIC18F2420252044204520 VOLTAGEFREQUENCY GRAPH INDUSTRIAL FIGURE 262 PIC18F2420252044204520 VOLTAGEFREQUENCY GRAPH EXTENDED Frequency Voltage 60V 55V 45V 40V 20V 40 MHz 50V 35V 30V 25V 42V PIC18F2420252044204520 Frequency Voltage 60V 55V 45V 40V 20V 25 MHz 50V 35V 30V 25V 42V PIC18F2420252044204520 2008 Microchip Technology Inc DS39631Epage 323 PIC18F2420252044204520 FIGURE 263 PIC18LF2420252044204520 VOLTAGEFREQUENCY GRAPH INDUSTRIAL Frequency Voltage 60V 55V 45V 40V 20V 40 MHz 50V 35V 30V 25V FMAX 1636 MHzV VDDAPPMIN 20V 4 MHz Note VDDAPPMIN is the minimum voltage of the PIC device in the application 4 MHz 42V PIC18LF2420252044204520 PIC18F2420252044204520 DS39631Epage 324 2008 Microchip Technology Inc 261 DC Characteristics Supply Voltage PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Symbol Characteristic Min Typ Max Units Conditions D001 VDD Supply Voltage PIC18LF2X2X4X20 20 55 V HS XT RC and LP Oscillator mode PIC18F2X204X20 42 55 V D002 VDR RAM Data Retention Voltage1 15 V D003 VPOR VDD Start Voltage to Ensure Internal Poweron Reset Signal 07 V See section on Poweron Reset for details D004 SVDD VDD Rise Rate to Ensure Internal Poweron Reset Signal 005 Vms See section on Poweron Reset for details VBOR Brownout Reset Voltage D005 PIC18LF2X2X4X20 BORV10 11 200 211 222 V BORV10 10 265 279 293 V D005 All Devices BORV10 012 411 433 455 V BORV10 00 436 459 482 V Legend Shading of rows is to assist in readability of the table Note 1 This is the limit to which VDD can be lowered in Sleep mode or during a device Reset without losing RAM data 2 With BOR enabled fullspeed operation FOSC 40 MHz is supported until a BOR occurs This is valid although VDD may be below the minimum voltage for this frequency 2008 Microchip Technology Inc DS39631Epage 325 PIC18F2420252044204520 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions PowerDown Current IPD1 PIC18LF2X2X4X20 01 05 μA 40C VDD 20V Sleep mode 01 05 μA 25C 02 25 μA 85C PIC18LF2X2X4X20 01 07 μA 40C VDD 30V Sleep mode 01 07 μA 25C 03 35 μA 85C All devices 01 10 μA 40C VDD 50V Sleep mode 02 10 μA 25C 07 10 μA 85C Extended devices only 10 100 μA 125C Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications PIC18F2420252044204520 DS39631Epage 326 2008 Microchip Technology Inc Supply Current IDD2 PIC18LF2X2X4X20 13 25 μA 40C VDD 20V FOSC 31 kHz RCRUN mode INTRC source 13 22 μA 25C 14 25 μA 85C PIC18LF2X2X4X20 42 61 μA 40C VDD 30V 34 46 μA 25C 28 45 μA 85C All devices 103 160 μA 40C VDD 50V 82 130 μA 25C 67 120 μA 85C Extended devices only 71 230 μA 125C PIC18LF2X2X4X20 320 440 μA 40C VDD 20V FOSC 1 MHz RCRUN mode INTOSC source 330 440 μA 25C 330 440 μA 85C PIC18LF2X2X4X20 630 800 μA 40C VDD 30V 590 720 μA 25C 570 700 μA 85C All devices 12 16 mA 40C VDD 50V 10 15 mA 25C 10 15 mA 85C Extended devices only 10 15 mA 125C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications 2008 Microchip Technology Inc DS39631Epage 327 PIC18F2420252044204520 Supply Current IDD2 PIC18LF2X2X4X20 08 11 mA 40C VDD 20V FOSC 4 MHz RCRUN mode INTOSC source 08 11 mA 25C 08 11 mA 85C PIC18LF2X2X4X20 13 17 mA 40C VDD 30V 13 17 mA 25C 13 17 mA 85C All devices 25 35 mA 40C VDD 50V 25 35 mA 25C 25 35 mA 85C Extended devices only 25 35 mA 125C PIC18LF2X2X4X20 29 5 μA 40C VDD 20V FOSC 31 kHz RCIDLE mode INTRC source 31 5 μA 25C 36 95 μA 85C PIC18LF2X2X4X20 45 8 μA 40C VDD 30V 48 8 μA 25C 58 15 μA 85C All devices 92 16 μA 40C VDD 50V 98 16 μA 25C 110 35 μA 85C Extended devices only 21 160 μA 125C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications PIC18F2420252044204520 DS39631Epage 328 2008 Microchip Technology Inc Supply Current IDD2 PIC18LF2X2X4X20 165 250 μA 40C VDD 20V FOSC 1 MHz RCIDLE mode INTOSC source 175 250 μA 25C 190 270 μA 85C PIC18LF2X2X4X20 250 360 μA 40C VDD 30V 270 360 μA 25C 290 380 μA 85C All devices 500 700 μA 40C VDD 50V 520 700 μA 25C 550 700 μA 85C Extended devices only 06 1 mA 125C PIC18LF2X2X4X20 340 500 μA 40C VDD 20V FOSC 4 MHz RCIDLE mode INTOSC source 350 500 μA 25C 360 500 μA 85C PIC18LF2X2X4X20 520 800 μA 40C VDD 30V 540 800 μA 25C 580 850 μA 85C All devices 10 16 mA 40C VDD 50V 11 14 mA 25C 11 14 mA 85C Extended devices only 11 20 mA 125C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications 2008 Microchip Technology Inc DS39631Epage 329 PIC18F2420252044204520 Supply Current IDD2 PIC18LF2X2X4X20 250 350 μA 40C VDD 20V FOSC 1 MHZ PRIRUN EC oscillator 260 350 μA 25C 250 350 μA 85C PIC18LF2X2X4X20 550 650 μA 40C VDD 30V 480 640 μA 25C 460 600 μA 85C All devices 12 15 mA 40C VDD 50V 11 14 mA 25C 10 13 mA 85C Extended devices only 10 30 mA 125C PIC18LF2X2X4X20 072 10 mA 40C VDD 20V FOSC 4 MHz PRIRUN EC oscillator 074 10 mA 25C 074 10 mA 85C PIC18LF2X2X4X20 13 18 mA 40C VDD 30V 13 18 mA 25C 13 18 mA 85C All devices 27 40 mA 40C VDD 50V 26 40 mA 25C 25 40 mA 85C Extended devices only 26 50 mA 125C Extended devices only 84 13 mA 125C VDD 42V FOSC 25 MHz PRIRUN EC oscillator 11 16 mA 125C VDD 50V All devices 15 20 mA 40C VDD 42V FOSC 40 MHZ PRIRUN EC oscillator 15 20 mA 25C 15 20 mA 85C All devices 20 25 mA 40C VDD 50V 20 25 mA 25C 20 25 mA 85C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications PIC18F2420252044204520 DS39631Epage 330 2008 Microchip Technology Inc Supply Current IDD2 All devices 75 10 mA 40C VDD 42V FOSC 4 MHZ 16 MHz internal PRIRUN HSPLL 74 10 mA 25C 73 10 mA 85C Extended devices only 80 12 mA 125C All devices 10 12 mA 40C VDD 50V FOSC 4 MHZ 16 MHz internal PRIRUN HSPLL 10 12 mA 25C 97 12 mA 85C Extended devices only 10 14 mA 125C All devices 15 20 mA 40C VDD 42V FOSC 10 MHZ 40 MHz internal PRIRUN HSPLL 15 20 mA 25C 15 20 mA 85C All devices 20 25 mA 40C VDD 50V FOSC 10 MHZ 40 MHz internal PRIRUN HSPLL 20 25 mA 25C 20 25 mA 85C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications 2008 Microchip Technology Inc DS39631Epage 331 PIC18F2420252044204520 Supply Current IDD2 PIC18LF2X2X4X20 65 100 μA 40C VDD 20V FOSC 1 MHz PRIIDLE mode EC oscillator 65 100 μA 25C 70 110 μA 85C PIC18LF2X2X4X20 120 140 μA 40C VDD 30V 120 140 μA 25C 130 160 μA 85C All devices 230 300 μA 40C VDD 50V 235 300 μA 25C 240 300 μA 85C Extended devices only 260 500 μA 125C PIC18LF2X2X4X20 260 360 μA 40C VDD 20V FOSC 4 MHz PRIIDLE mode EC oscillator 255 360 μA 25C 270 360 μA 85C PIC18LF2X2X4X20 420 620 μA 40C VDD 30V 430 620 μA 25C 450 650 μA 85C All devices 09 12 mA 40C VDD 50V 09 12 mA 25C 09 12 mA 85C Extended devices only 1 13 mA 125C Extended devices only 28 60 mA 125C VDD 42V FOSC 25 MHz PRIIDLE mode EC oscillator 43 80 mA 125C VDD 50V All devices 60 10 mA 40C VDD 42V FOSC 40 MHz PRIIDLE mode EC oscillator 62 10 mA 25C 66 10 mA 85C All devices 81 13 mA 40C VDD 50V 91 12 mA 25C 83 12 mA 85C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications PIC18F2420252044204520 DS39631Epage 332 2008 Microchip Technology Inc Supply Current IDD2 PIC18LF2X2X4X20 10 25 μA 40C3 VDD 20V FOSC 32 kHz3 SECRUN mode Timer1 as clock 11 21 μA 25C 12 25 μA 85C PIC18LF2X2X4X20 42 57 μA 40C3 VDD 30V 33 45 μA 25C 29 45 μA 85C All devices 105 150 μA 40C3 VDD 50V 81 130 μA 25C 67 130 μA 85C PIC18LF2X2X4X20 30 12 μA 40C3 VDD 20V FOSC 32 kHz3 SECIDLE mode Timer1 as clock 30 6 μA 25C 37 10 μA 85C PIC18LF2X2X4X20 50 15 μA 40C3 VDD 30V 54 10 μA 25C 63 15 μA 85C All devices 85 25 μA 40C3 VDD 50V 90 20 μA 25C 105 30 μA 85C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications 2008 Microchip Technology Inc DS39631Epage 333 PIC18F2420252044204520 Module Differential Currents ΔIWDT ΔIBOR ΔILVD ΔIOSCB ΔIAD D026 ΔIAD AD Converter 02 10 μA 40C to 85C VDD 20V AD on not converting 02 10 μA 40C to 85C VDD 30V 02 10 μA 40C to 85C VDD 50V 05 40 μA 40C to 125C D022 ΔIWDT Watchdog Timer 13 22 μA 40C VDD 20V 14 22 μA 25C 16 23 μA 85C 19 35 μA 40C VDD 30V 20 35 μA 25C 22 35 μA 85C 30 75 μA 40C VDD 50V 35 75 μA 25C 35 78 μA 85C 40 10 μA 125C D022A ΔIBOR Brownout Reset4 35 50 μA 40C to 85C VDD 30V 40 55 μA 40C to 85C VDD 50V 55 65 μA 40C to 125C 0 2 μA 40C to 85C Sleep mode BOREN10 10 0 5 μA 40C to 125C D022B ΔILVD HighLowVoltage Detect4 22 38 μA 40C to 85C VDD 20V 25 40 μA 40C to 85C VDD 30V 29 45 μA 40C to 85C VDD 50V 30 45 μA 40C to 125C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications PIC18F2420252044204520 DS39631Epage 334 2008 Microchip Technology Inc D025L ΔIOSCB Timer1 Oscillator 45 90 μA 40C3 VDD 20V 32 kHz on Timer1 09 16 μA 10C 09 16 μA 25C 09 18 μA 85C 48 10 μA 40C3 VDD 30V 32 kHz on Timer1 10 20 μA 10C 10 20 μA 25C 10 26 μA 85C 60 11 μA 40C3 VDD 50V 32 kHz on Timer1 16 40 μA 10C 16 40 μA 25C 16 40 μA 85C 262 DC Characteristics PowerDown and Supply Current PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial 40C TA 125C for extended Param No Device Typ Max Units Conditions Legend Shading of rows is to assist in readability of the table Note 1 The powerdown current in Sleep mode does not depend on the oscillator type Powerdown current is measured with the part in Sleep mode with all IO pins in highimpedance state and tied to VDD or VSS and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as IO pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from railtorail all IO pins tristated pulled to VDD or VSS MCLR VDD WDT enableddisabled as specified 3 When operation below 10C is expected use T1OSC HighPower mode where LPT1OSC CONFIG3H2 0 When operation will always be above 10C then the lowpower Timer1 oscillator may be selected 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications 2008 Microchip Technology Inc DS39631Epage 335 PIC18F2420252044204520 263 DC Characteristics PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial Param No Symbol Characteristic Min Max Units Conditions VIL Input Low Voltage IO Ports D030 with TTL Buffer VSS 015 VDD V VDD 45V D030A 08 V 45V VDD 55V D031 with Schmitt Trigger Buffer VSS 02 VDD V D031A RC3 and RC4 VSS 03 VDD V I2C enabled D031B VSS 08 V SMBus enabled D032 MCLR VSS 02 VDD V D033 OSC1 VSS 03 VDD V HS HSPLL modes D033A D033B D034 OSC1 OSC1 T13CKI VSS VSS VSS 02 VDD 03 03 V V V RC EC modes1 XT LP modes VIH Input High Voltage IO Ports D040 with TTL Buffer 025 VDD 08V VDD V VDD 45V D040A 20 VDD V 45V VDD 55V D041 with Schmitt Trigger Buffer 08 VDD VDD V D041A RC3 and RC4 07 VDD VDD V I2C enabled D041B 21 VDD V SMBus enabled D042 MCLR 08 VDD VDD V D043 OSC1 07 VDD VDD V HS HSPLL modes D043A D043B D043C D044 OSC1 OSC1 OSC1 T13CKI 08 VDD 09 VDD 16 16 VDD VDD VDD VDD V V V V EC mode RC mode1 XT LP modes IIL Input Leakage Current23 D060 IO Ports 200 50 nA nA VDD 55V VSS VPIN VDD Pin at highimpedance VDD 3V VSS VPIN VDD Pin at highimpedance D061 MCLR 1 μA Vss VPIN VDD D063 OSC1 1 μA Vss VPIN VDD IPU Weak Pullup Current D070 IPURB PORTB Weak Pullup Current 50 400 μA VDD 5V VPIN VSS Note 1 In RC oscillator configuration the OSC1CLKI pin is a Schmitt Trigger input It is not recommended that the PIC device be driven with an external clock while in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin PIC18F2420252044204520 DS39631Epage 336 2008 Microchip Technology Inc VOL Output Low Voltage D080 IO Ports 06 V IOL 85 mA VDD 45V 40C to 85C D083 OSC2CLKO RC RCIO EC ECIO modes 06 V IOL 16 mA VDD 45V 40C to 85C VOH Output High Voltage3 D090 IO Ports VDD 07 V IOH 30 mA VDD 45V 40C to 85C D092 OSC2CLKO RC RCIO EC ECIO modes VDD 07 V IOH 13 mA VDD 45V 40C to 85C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin 15 pF In XT HS and LP modes when external clock is used to drive OSC1 D101 CIO All IO pins and OSC2 in RC mode 50 pF To meet the AC Timing Specifications D102 CB SCL SDA 400 pF I2C Specification 263 DC Characteristics PIC18F2420252044204520 Industrial PIC18LF2420252044204520 Industrial Continued DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial Param No Symbol Characteristic Min Max Units Conditions Note 1 In RC oscillator configuration the OSC1CLKI pin is a Schmitt Trigger input It is not recommended that the PIC device be driven with an external clock while in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin 2008 Microchip Technology Inc DS39631Epage 337 PIC18F2420252044204520 TABLE 261 MEMORY PROGRAMMING REQUIREMENTS DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial Param No Sym Characteristic Min Typ Max Units Conditions Data EEPROM Memory D120 ED Byte Endurance 100K 1M EW 40C to 85C D121 VDRW VDD for ReadWrite VMIN 55 V Using EECON to readwrite VMIN Minimum operating voltage D122 TDEW EraseWrite Cycle Time 4 ms D123 TRETD Characteristic Retention 40 Year Provided no other specifications are violated D124 TREF Number of Total EraseWrite Cycles before Refresh1 1M 10M EW 40C to 85C D125 IDDP Supply Current during Programming 10 mA Program Flash Memory D130 EP Cell Endurance 10K 100K EW 40C to 85C D131 VPR VDD for Read VMIN 55 V VMIN Minimum operating voltage D132 VIE VDD for Block Erase 30 55 V Using ICSP port 25C D132A VIW VDD for Externally Timed Erase or Write 45 55 V Using ICSP port 25C D132B VPEW VDD for SelfTimed Write VMIN 55 V VMIN Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time 4 ms VDD 45V D133A TIW ICSP Erase or Write Cycle Time externally timed 1 ms VDD 45V 25C D133A TIW SelfTimed Write Cycle Time 2 ms D134 TRETD Characteristic Retention 40 100 Year Provided no other specifications are violated D135 IDDP Supply Current during Programming 10 mA Data in Typ column is at 50V 25C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Refer to Section 78 Using the Data EEPROM for a more detailed discussion on data EEPROM endurance PIC18F2420252044204520 DS39631Epage 338 2008 Microchip Technology Inc TABLE 262 COMPARATOR SPECIFICATIONS TABLE 263 VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions 30V VDD 55V 40C TA 85C unless otherwise stated Param No Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage 50 10 mV D301 VICM Input Common Mode Voltage 0 VDD 15 V D302 CMRR Common Mode Rejection Ratio 55 dB 300 TRESP Response Time1 150 400 ns PIC18FXXXX 300A 150 600 ns PIC18LFXXXX VDD 20V 301 TMC2OV Comparator Mode Change to Output Valid 10 μs Note 1 Response time measured with one comparator input at VDD 152 while the other input transitions from VSS to VDD Operating Conditions 30V VDD 55V 40C TA 85C unless otherwise stated Param No Sym Characteristics Min Typ Max Units Comments D310 VRES Resolution VDD24 VDD32 LSb D311 VRAA Absolute Accuracy 12 LSb D312 VRUR Unit Resistor Value R 2k Ω 310 TSET Settling Time1 10 μs Note 1 Settling time measured while CVRR 1 and CVR3CVR0 transitions from 0000 to 1111 2008 Microchip Technology Inc DS39631Epage 339 PIC18F2420252044204520 FIGURE 264 HIGHLOWVOLTAGE DETECT CHARACTERISTICS TABLE 264 HIGHLOWVOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial Param No Sym Characteristic Min Typ Max Units Conditions D420 HLVD Voltage on VDD Transition HightoLow HLVDL30 0000 206 217 228 V HLVDL30 0001 212 223 234 V HLVDL30 0010 224 236 248 V HLVDL30 0011 232 244 256 V HLVDL30 0100 247 260 273 V HLVDL30 0101 265 279 293 V HLVDL30 0110 274 289 304 V HLVDL30 0111 296 312 328 V HLVDL30 1000 322 339 356 V HLVDL30 1001 337 355 373 V HLVDL30 1010 352 371 390 V HLVDL30 1011 370 390 410 V HLVDL30 1100 390 411 432 V HLVDL30 1101 411 433 455 V HLVDL30 1110 436 459 482 V VLVD HLVDIF1 VDD HLVDIF set by hardware HLVDIF can be cleared in software Note 1 VDIRMAG 0 PIC18F2420252044204520 DS39631Epage 340 2008 Microchip Technology Inc 264 AC Timing Characteristics 2641 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats 1 TppS2ppS 3 TCCST I2C specifications only 2 TppS 4 Ts I2C specifications only T F Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io IO port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings S F Fall P Period H High R Rise I Invalid Highimpedance V Valid L Low Z Highimpedance I2C only AA output access High High BUF Bus free Low Low TCCST I2C specifications only CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition 2008 Microchip Technology Inc DS39631Epage 341 PIC18F2420252044204520 2642 TIMING CONDITIONS The temperature and voltages specified in Table 265 apply to all timing specifications unless otherwise noted Figure 265 specifies the load conditions for the timing specifications TABLE 265 TEMPERATURE AND VOLTAGE SPECIFICATIONS AC FIGURE 265 LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Note Because of space limitations the generic terms PIC18FXXXX and PIC18LFXXXX are used throughout this section to refer to the PIC18F2420252044204520 and PIC18LF2420252044204520 families of devices specifically and only those devices AC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial Operating voltage VDD range as described in DC specification Section 261 and Section 263 LF parts operate for industrial temperatures only VDD2 CL RL Pin Pin VSS VSS CL RL 464Ω CL 50 pF for all pins except OSC2CLKO and including D and E outputs as ports Load Condition 1 Load Condition 2 PIC18F2420252044204520 DS39631Epage 342 2008 Microchip Technology Inc 2643 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 266 EXTERNAL CLOCK TIMING ALL MODES EXCEPT PLL TABLE 266 EXTERNAL CLOCK TIMING REQUIREMENTS Param No Symbol Characteristic Min Max Units Conditions 1A FOSC External CLKI Frequency1 DC 1 MHz XT RC Oscillator mode DC 25 MHz HS Oscillator mode DC 3125 kHz LP Oscillator mode DC 40 MHz EC Oscillator mode Oscillator Frequency1 DC 4 MHz RC Oscillator mode 01 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HS PLL Oscillator mode 5 200 kHz LP Oscillator mode 1 TOSC External CLKI Period1 1000 ns XT RC Oscillator mode 40 ns HS Oscillator mode 32 μs LP Oscillator mode 25 ns EC Oscillator mode Oscillator Period1 250 ns RC Oscillator mode 025 10 μs XT Oscillator mode 40 250 ns HS Oscillator mode 100 250 ns HS PLL Oscillator mode 5 200 μs LP Oscillator mode 2 TCY Instruction Cycle Time1 100 ns TCY 4FOSC Industrial 160 ns TCY 4FOSC Extended 3 TOSL TOSH External Clock in OSC1 High or Low Time 30 ns XT Oscillator mode 25 μs LP Oscillator mode 10 ns HS Oscillator mode 4 TOSR TOSF External Clock in OSC1 Rise or Fall Time 20 ns XT Oscillator mode 50 ns LP Oscillator mode 75 ns HS Oscillator mode Note 1 Instruction cycle period TCY equals four times the input oscillator time base period for all configurations except PLL All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation andor higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSC1CLKI pin When an external clock input is used the max cycle time limit is DC no clock for all devices OSC1 CLKO Q4 Q1 Q2 Q3 Q4 Q1 1 2 3 3 4 4 2008 Microchip Technology Inc DS39631Epage 343 PIC18F2420252044204520 TABLE 267 PLL CLOCK TIMING SPECIFICATIONS VDD 42V TO 55V TABLE 268 AC CHARACTERISTICS INTERNAL RC ACCURACY PIC18F2420252044204520 INDUSTRIAL PIC18LF2420252044204520 INDUSTRIAL Param No Sym Characteristic Min Typ Max Units Conditions F10 FOSC Oscillator Frequency Range 4 10 MHz HS mode only F11 FSYS OnChip VCO System Frequency 16 40 MHz HS mode only F12 trc PLL Startup Time Lock Time 2 ms F13 ΔCLK CLKO Stability Jitter 2 2 Data in Typ column is at 5V 25C unless otherwise stated These parameters are for design guidance only and are not tested PIC18LF2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial PIC18F2420252044204520 Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C TA 85C for industrial Param No Device Min Typ Max Units Conditions INTOSC Accuracy Freq 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz1 PIC18LF2420252044204520 2 1 2 25C VDD 2733V 5 1 5 40C to 85C VDD 2733V PIC18F2420252044204520 2 1 2 25C VDD 4555V 5 1 5 40C to 85C VDD 4555V INTRC Accuracy Freq 31 kHz PIC18LF2420252044204520 26562 35938 kHz 40C to 85C VDD 2733V PIC18F2420252044204520 26562 35938 kHz 40C to 85C VDD 4555V Legend Shading of rows is to assist in readability of the table Note 1 Frequency calibrated at 25C OSCTUNE register can be used to compensate for temperature drift PIC18F2420252044204520 DS39631Epage 344 2008 Microchip Technology Inc FIGURE 267 CLKO AND IO TIMING TABLE 269 CLKO AND IO TIMING REQUIREMENTS Param No Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 to CLKO 75 200 ns Note 1 11 TosH2ckH OSC1 to CLKO 75 200 ns Note 1 12 TckR CLKO Rise Time 35 100 ns Note 1 13 TckF CLKO Fall Time 35 100 ns Note 1 14 TckL2ioV CLKO to Port Out Valid 05 TCY 20 ns Note 1 15 TioV2ckH Port In Valid before CLKO 025 TCY 25 ns Note 1 16 TckH2ioI Port In Hold after CLKO 0 ns Note 1 17 TosH2ioV OSC1 Q1 cycle to Port Out Valid 50 150 ns 18 TosH2ioI OSC1 Q2 cycle to Port Input Invalid IO in hold time PIC18FXXXX 100 ns 18A PIC18LFXXXX 200 ns VDD 20V 19 TioV2osH Port Input Valid to OSC1 IO in setup time 0 ns 20 TioR Port Output Rise Time PIC18FXXXX 10 25 ns 20A PIC18LFXXXX 60 ns VDD 20V 21 TioF Port Output Fall Time PIC18FXXXX 10 25 ns 21A PIC18LFXXXX 60 ns VDD 20V 22 TINP INTx pin High or Low Time TCY ns 23 TRBP RB74 Change INTx High or Low Time TCY ns These parameters are asynchronous events not related to any internal clock edges Note 1 Measurements are taken in RC mode where CLKO output is 4 x TOSC Note Refer to Figure 265 for load conditions OSC1 CLKO IO pin Input IO pin Output Q4 Q1 Q2 Q3 10 13 14 17 20 21 19 18 15 11 12 16 Old Value New Value 2008 Microchip Technology Inc DS39631Epage 345 PIC18F2420252044204520 FIGURE 268 RESET WATCHDOG TIMER OSCILLATOR STARTUP TIMER AND POWERUP TIMER TIMING FIGURE 269 BROWNOUT RESET TIMING TABLE 2610 RESET WATCHDOG TIMER OSCILLATOR STARTUP TIMER POWERUP TIMER AND BROWNOUT RESET REQUIREMENTS Param No Symbol Characteristic Min Typ Max Units Conditions 30 TmcL MCLR Pulse Width low 2 μs 31 TWDT Watchdog Timer Timeout Period no postscaler 34 41 471 ms 32 TOST Oscillation Startup Timer Period 1024 TOSC 1024 TOSC TOSC OSC1 period 33 TPWRT Powerup Timer Period 556 655 754 ms 34 TIOZ IO HighImpedance from MCLR Low or Watchdog Timer Reset 2 μs 35 TBOR Brownout Reset Pulse Width 200 μs VDD BVDD see D005 36 TIRVST Time for Internal Reference Voltage to become Stable 20 50 μs 37 TLVD HighLowVoltage Detect Pulse Width 200 μs VDD VLVD 38 TCSD CPU Startup Time 10 μs 39 TIOBST Time for INTOSC to Stabilize 1 μs VDD MCLR Internal POR PWRT Timeout OSC Timeout Internal Reset Watchdog Timer Reset 33 32 30 31 34 IO pins 34 Note Refer to Figure 265 for load conditions VDD BVDD 35 VIRVST Enable Internal Internal Reference 36 Reference Voltage Voltage Stable PIC18F2420252044204520 DS39631Epage 346 2008 Microchip Technology Inc FIGURE 2610 TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TABLE 2611 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No Symbol Characteristic Min Max Units Conditions 40 Tt0H T0CKI High Pulse Width No prescaler 05 TCY 20 ns With prescaler 10 ns 41 Tt0L T0CKI Low Pulse Width No prescaler 05 TCY 20 ns With prescaler 10 ns 42 Tt0P T0CKI Period No prescaler TCY 10 ns With prescaler Greater of 20 ns or TCY 40N ns N prescale value 1 2 4 256 45 Tt1H T13CKI High Time Synchronous no prescaler 05 TCY 20 ns Synchronous with prescaler PIC18FXXXX 10 ns PIC18LFXXXX 25 ns VDD 20V Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns VDD 20V 46 Tt1L T13CKI Low Time Synchronous no prescaler 05 TCY 5 ns Synchronous with prescaler PIC18FXXXX 10 ns PIC18LFXXXX 25 ns VDD 20V Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns VDD 20V 47 Tt1P T13CKI Input Period Synchronous Greater of 20 ns or TCY 40N ns N prescale value 1 2 4 8 Asynchronous 60 ns Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External T13CKI Clock Edge to Timer Increment 2 TOSC 7 TOSC Note Refer to Figure 265 for load conditions 46 47 45 48 41 42 40 T0CKI T1OSOT13CKI TMR0 or TMR1 2008 Microchip Technology Inc DS39631Epage 347 PIC18F2420252044204520 FIGURE 2611 CAPTURECOMPAREPWM TIMINGS ALL CCP MODULES TABLE 2612 CAPTURECOMPAREPWM REQUIREMENTS ALL CCP MODULES Param No Symbol Characteristic Min Max Units Conditions 50 TccL CCPx Input Low Time No prescaler 05 TCY 20 ns With prescaler PIC18FXXXX 10 ns PIC18LFXXXX 20 ns VDD 20V 51 TccH CCPx Input High Time No prescaler 05 TCY 20 ns With prescaler PIC18FXXXX 10 ns PIC18LFXXXX 20 ns VDD 20V 52 TccP CCPx Input Period 3 TCY 40 N ns N prescale value 1 4 or 16 53 TccR CCPx Output Fall Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V 54 TccF CCPx Output Fall Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V Note Refer to Figure 265 for load conditions CCPx Capture Mode 50 51 52 CCPx 53 54 Compare or PWM Mode PIC18F2420252044204520 DS39631Epage 348 2008 Microchip Technology Inc FIGURE 2612 PARALLEL SLAVE PORT TIMING PIC18F44204520 TABLE 2613 PARALLEL SLAVE PORT REQUIREMENTS PIC18F4420 PIC18F4520 Param No Symbol Characteristic Min Max Units Conditions 62 TdtV2wrH Data In Valid before WR or CS setup time 20 ns 63 TwrH2dtI WR or CS to DataIn Invalid hold time PIC18FXXXX 20 ns PIC18LFXXXX 35 ns VDD 20V 64 TrdL2dtV RD and CS to DataOut Valid 80 ns 65 TrdH2dtI RD or CS to DataOut Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from WR or CS 3 TCY Note Refer to Figure 265 for load conditions RE2CS RE0RD RE1WR RD70 62 63 64 65 2008 Microchip Technology Inc DS39631Epage 349 PIC18F2420252044204520 FIGURE 2613 EXAMPLE SPI MASTER MODE TIMING CKE 0 TABLE 2614 EXAMPLE SPI MODE REQUIREMENTS MASTER MODE CKE 0 Param No Symbol Characteristic Min Max Units Conditions 70 TssL2scH TssL2scL SS to SCK or SCK Input TCY ns 73 TdiV2scH TdiV2scL Setup Time of SDI Data Input to SCK Edge 20 ns 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 15 TCY 40 ns Note 2 74 TscH2diL TscL2diL Hold Time of SDI Data Input to SCK Edge 40 ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V 76 TdoF SDO Data Output Fall Time 25 ns 78 TscR SCK Output Rise Time Master mode PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V 79 TscF SCK Output Fall Time Master mode 25 ns 80 TscH2doV TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX 50 ns PIC18LFXXXX 100 ns VDD 20V Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used SS SCK CKP 0 SCK CKP 1 SDO SDI 70 71 72 73 74 75 76 78 79 80 79 78 MSb LSb bit 6 1 MSb In LSb In bit 6 1 Note Refer to Figure 265 for load conditions PIC18F2420252044204520 DS39631Epage 350 2008 Microchip Technology Inc FIGURE 2614 EXAMPLE SPI MASTER MODE TIMING CKE 1 TABLE 2615 EXAMPLE SPI MODE REQUIREMENTS MASTER MODE CKE 1 Param No Symbol Characteristic Min Max Units Conditions 73 TdiV2scH TdiV2scL Setup Time of SDI Data Input to SCK Edge 20 ns 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 15 TCY 40 ns Note 2 74 TscH2diL TscL2diL Hold Time of SDI Data Input to SCK Edge 40 ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V 76 TdoF SDO Data Output Fall Time 25 ns 78 TscR SCK Output Rise Time Master mode PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V 79 TscF SCK Output Fall Time Master mode 25 ns 80 TscH2doV TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX 50 ns PIC18LFXXXX 100 ns VDD 20V 81 TdoV2scH TdoV2scL SDO Data Output Setup to SCK Edge TCY ns Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used SS SCK CKP 0 SCK CKP 1 SDO SDI 81 71 72 74 75 76 78 80 MSb 79 73 MSb In bit 6 1 LSb In bit 6 1 LSb Note Refer to Figure 265 for load conditions 2008 Microchip Technology Inc DS39631Epage 351 PIC18F2420252044204520 FIGURE 2615 EXAMPLE SPI SLAVE MODE TIMING CKE 0 TABLE 2616 EXAMPLE SPI MODE REQUIREMENTS SLAVE MODE TIMING CKE 0 Param No Symbol Characteristic Min Max Units Conditions 70 TssL2scH TssL2scL SS to SCK or SCK Input 3 TCY ns 71 TscH SCK Input High Time Slave mode Continuous 125 TCY 30 ns 71A Single Byte 40 ns Note 1 72 TscL SCK Input Low Time Slave mode Continuous 125 TCY 30 ns 72A Single Byte 40 ns Note 1 73 TdiV2scH TdiV2scL Setup Time of SDI Data Input to SCK Edge 20 ns 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 15 TCY 40 ns Note 2 74 TscH2diL TscL2diL Hold Time of SDI Data Input to SCK Edge 40 ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V 76 TdoF SDO Data Output Fall Time 25 ns 77 TssH2doZ SS to SDO Output HighImpedance 10 50 ns 80 TscH2doV TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX 50 ns PIC18LFXXXX 100 ns VDD 20V 83 TscH2ssH TscL2ssH SS after SCK edge 15 TCY 40 ns Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used SS SCK CKP 0 SCK CKP 1 SDO SDI 70 71 72 73 74 75 76 77 78 79 80 79 78 SDI MSb LSb bit 6 1 bit 6 1 LSb In 83 Note Refer to Figure 265 for load conditions MSb In PIC18F2420252044204520 DS39631Epage 352 2008 Microchip Technology Inc FIGURE 2616 EXAMPLE SPI SLAVE MODE TIMING CKE 1 TABLE 2617 EXAMPLE SPI SLAVE MODE REQUIREMENTS CKE 1 Param No Symbol Characteristic Min Max Units Conditions 70 TssL2scH TssL2scL SS to SCK or SCK Input 3 TCY ns 71 TscH SCK Input High Time Slave mode Continuous 125 TCY 30 ns 71A Single Byte 40 ns Note 1 72 TscL SCK Input Low Time Slave mode Continuous 125 TCY 30 ns 72A Single Byte 40 ns Note 1 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 15 TCY 40 ns Note 2 74 TscH2diL TscL2diL Hold Time of SDI Data Input to SCK Edge 40 ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 20V 76 TdoF SDO Data Output Fall Time 25 ns 77 TssH2doZ SS to SDO Output HighImpedance 10 50 ns 80 TscH2doV TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX 50 ns PIC18LFXXXX 100 ns VDD 20V 82 TssL2doV SDO Data Output Valid after SS Edge PIC18FXXXX 50 ns PIC18LFXXXX 100 ns VDD 20V 83 TscH2ssH TscL2ssH SS after SCK Edge 15 TCY 40 ns Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used SS SCK CKP 0 SCK CKP 1 SDO SDI 70 71 72 82 SDI 74 75 76 MSb bit 6 1 LSb 77 MSb In bit 6 1 LSb In 80 83 Note Refer to Figure 265 for load conditions 2008 Microchip Technology Inc DS39631Epage 353 PIC18F2420252044204520 FIGURE 2617 I2C BUS STARTSTOP BITS TIMING TABLE 2618 I2C BUS STARTSTOP BITS REQUIREMENTS SLAVE MODE FIGURE 2618 I2C BUS DATA TIMING Param No Symbol Characteristic Min Max Units Conditions 90 TSUSTA Start Condition 100 kHz mode 4700 ns Only relevant for Repeated Start condition Setup Time 400 kHz mode 600 91 THDSTA Start Condition 100 kHz mode 4000 ns After this period the first clock pulse is generated Hold Time 400 kHz mode 600 92 TSUSTO Stop Condition 100 kHz mode 4700 ns Setup Time 400 kHz mode 600 93 THDSTO Stop Condition 100 kHz mode 4000 ns Hold Time 400 kHz mode 600 Note Refer to Figure 265 for load conditions 91 92 93 SCL SDA Start Condition Stop Condition 90 Note Refer to Figure 265 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 SCL SDA In SDA Out PIC18F2420252044204520 DS39631Epage 354 2008 Microchip Technology Inc TABLE 2619 I2C BUS DATA REQUIREMENTS SLAVE MODE Param No Symbol Characteristic Min Max Units Conditions 100 THIGH Clock High Time 100 kHz mode 40 μs 400 kHz mode 06 μs MSSP module 15 TCY 101 TLOW Clock Low Time 100 kHz mode 47 μs 400 kHz mode 13 μs MSSP module 15 TCY 102 TR SDA and SCL Rise Time 100 kHz mode 1000 ns 400 kHz mode 20 01 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall Time 100 kHz mode 300 ns 400 kHz mode 20 01 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSUSTA Start Condition Setup Time 100 kHz mode 47 μs Only relevant for Repeated Start condition 400 kHz mode 06 μs 91 THDSTA Start Condition Hold Time 100 kHz mode 40 μs After this period the first clock pulse is generated 400 kHz mode 06 μs 106 THDDAT Data Input Hold Time 100 kHz mode 0 ns 400 kHz mode 0 09 μs 107 TSUDAT Data Input Setup Time 100 kHz mode 250 ns Note 2 400 kHz mode 100 ns 92 TSUSTO Stop Condition Setup Time 100 kHz mode 47 μs 400 kHz mode 06 μs 109 TAA Output Valid from Clock 100 kHz mode 3500 ns Note 1 400 kHz mode ns 110 TBUF Bus Free Time 100 kHz mode 47 μs Time the bus must be free before a new transmission can start 400 kHz mode 13 μs D102 CB Bus Capacitive Loading 400 pF Note 1 As a transmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of Start or Stop conditions 2 A Fast mode I2C bus device can be used in a Standard mode I2C bus system but the requirement TSUDAT 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line TR max TSUDAT 1000 250 1250 ns according to the Standard mode I2C bus specification before the SCL line is released 2008 Microchip Technology Inc DS39631Epage 355 PIC18F2420252044204520 FIGURE 2619 MASTER SSP I2C BUS STARTSTOP BITS TIMING WAVEFORMS TABLE 2620 MASTER SSP I2C BUS STARTSTOP BITS REQUIREMENTS FIGURE 2620 MASTER SSP I2C BUS DATA TIMING Param No Symbol Characteristic Min Max Units Conditions 90 TSUSTA Start Condition 100 kHz mode 2TOSCBRG 1 ns Only relevant for Repeated Start condition Setup Time 400 kHz mode 2TOSCBRG 1 1 MHz mode1 2TOSCBRG 1 91 THDSTA Start Condition 100 kHz mode 2TOSCBRG 1 ns After this period the first clock pulse is generated Hold Time 400 kHz mode 2TOSCBRG 1 1 MHz mode1 2TOSCBRG 1 92 TSUSTO Stop Condition 100 kHz mode 2TOSCBRG 1 ns Setup Time 400 kHz mode 2TOSCBRG 1 1 MHz mode1 2TOSCBRG 1 93 THDSTO Stop Condition 100 kHz mode 2TOSCBRG 1 ns Hold Time 400 kHz mode 2TOSCBRG 1 1 MHz mode1 2TOSCBRG 1 Note 1 Maximum pin capacitance 10 pF for all I2C pins Note Refer to Figure 265 for load conditions 91 93 SCL SDA Start Condition Stop Condition 90 92 Note Refer to Figure 265 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 SCL SDA In SDA Out PIC18F2420252044204520 DS39631Epage 356 2008 Microchip Technology Inc TABLE 2621 MASTER SSP I2C BUS DATA REQUIREMENTS Param No Symbol Characteristic Min Max Units Conditions 100 THIGH Clock High Time 100 kHz mode 2TOSCBRG 1 ms 400 kHz mode 2TOSCBRG 1 ms 1 MHz mode1 2TOSCBRG 1 ms 101 TLOW Clock Low Time 100 kHz mode 2TOSCBRG 1 ms 400 kHz mode 2TOSCBRG 1 ms 1 MHz mode1 2TOSCBRG 1 ms 102 TR SDA and SCL Rise Time 100 kHz mode 1000 ns CB is specified to be from 10 to 400 pF 400 kHz mode 20 01 CB 300 ns 1 MHz mode1 300 ns 103 TF SDA and SCL Fall Time 100 kHz mode 300 ns CB is specified to be from 10 to 400 pF 400 kHz mode 20 01 CB 300 ns 1 MHz mode1 100 ns 90 TSUSTA Start Condition Setup Time 100 kHz mode 2TOSCBRG 1 ms Only relevant for Repeated Start condition 400 kHz mode 2TOSCBRG 1 ms 1 MHz mode1 2TOSCBRG 1 ms 91 THDSTA Start Condition Hold Time 100 kHz mode 2TOSCBRG 1 ms After this period the first clock pulse is generated 400 kHz mode 2TOSCBRG 1 ms 1 MHz mode1 2TOSCBRG 1 ms 106 THDDAT Data Input Hold Time 100 kHz mode 0 ns 400 kHz mode 0 09 ms 107 TSUDAT Data Input Setup Time 100 kHz mode 250 ns Note 2 400 kHz mode 100 ns 92 TSUSTO Stop Condition Setup Time 100 kHz mode 2TOSCBRG 1 ms 400 kHz mode 2TOSCBRG 1 ms 1 MHz mode1 2TOSCBRG 1 ms 109 TAA Output Valid from Clock 100 kHz mode 3500 ns 400 kHz mode 1000 ns 1 MHz mode1 ns 110 TBUF Bus Free Time 100 kHz mode 47 ms Time the bus must be free before a new transmission can start 400 kHz mode 13 ms D102 CB Bus Capacitive Loading 400 pF Note 1 Maximum pin capacitance 10 pF for all I2C pins 2 A Fast mode I2C bus device can be used in a Standard mode I2C bus system but parameter 107 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line parameter 102 parameter 107 1000 250 1250 ns for 100 kHz mode before the SCL line is released 2008 Microchip Technology Inc DS39631Epage 357 PIC18F2420252044204520 FIGURE 2621 EUSART SYNCHRONOUS TRANSMISSION MASTERSLAVE TIMING TABLE 2622 EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No Symbol Characteristic Min Max Units Conditions 120 TckH2dtV SYNC XMIT MASTER SLAVE Clock High to Data Out Valid PIC18FXXXX 40 ns PIC18LFXXXX 100 ns VDD 20V 121 Tckrf Clock Out Rise Time and Fall Time Master mode PIC18FXXXX 20 ns PIC18LFXXXX 50 ns VDD 20V 122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX 20 ns PIC18LFXXXX 50 ns VDD 20V 121 121 120 122 RC6TXCK RC7RXDT pin pin Note Refer to Figure 265 for load conditions PIC18F2420252044204520 DS39631Epage 358 2008 Microchip Technology Inc FIGURE 2622 EUSART SYNCHRONOUS RECEIVE MASTERSLAVE TIMING TABLE 2623 EUSART SYNCHRONOUS RECEIVE REQUIREMENTS TABLE 2624 AD CONVERTER CHARACTERISTICS PIC18F2420252044204520 INDUSTRIAL PIC18LF2420252044204520 INDUSTRIAL Param No Symbol Characteristic Min Max Units Conditions 125 TdtV2ckl SYNC RCV MASTER SLAVE Data Hold before CK DT hold time 10 ns 126 TckL2dtl Data Hold after CK DT hold time 15 ns Param No Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution 10 bit ΔVREF 30V A03 EIL Integral Linearity Error 1 LSb ΔVREF 30V A04 EDL Differential Linearity Error 1 LSb ΔVREF 30V A06 EOFF Offset Error 20 LSb ΔVREF 30V A07 EGN Gain Error 1 LSb ΔVREF 30V A10 Monotonicity Guaranteed1 VSS VAIN VREF A20 ΔVREF Reference Voltage Range VREFH VREFL 18 3 V V VDD 30V VDD 30V A21 VREFH Reference Voltage High VSS VREFH V A22 VREFL Reference Voltage Low VSS 03V VDD 30V V A25 VAIN Analog Input Voltage VREFL VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source 25 kΩ A40 IAD AD Current from VDD PIC18FXXXX 180 μA Average current during conversion PIC18LFXX20 90 μA A50 IREF VREF Input Current2 5 150 μA μA During VAIN acquisition During AD conversion cycle Note 1 The AD conversion result never decreases with an increase in the input voltage and has no missing codes 2 VREFH current is from RA3AN3VREF pin or VDD whichever is selected as the VREFH source VREFL current is from RA2AN2VREFCVREF pin or VSS whichever is selected as the VREFL source 125 126 RC6TXCK RC7RXDT pin pin Note Refer to Figure 265 for load conditions 2008 Microchip Technology Inc DS39631Epage 359 PIC18F2420252044204520 FIGURE 2623 AD CONVERSION TIMING TABLE 2625 AD CONVERSION REQUIREMENTS Param No Symbol Characteristic Min Max Units Conditions 130 TAD AD Clock Period PIC18FXXXX 07 2501 μs TOSC based VREF 30V PIC18LFXXXX 14 2501 μs VDD 20V TOSC based VREF full range PIC18FXXXX 1 μs AD RC mode PIC18LFXXXX 3 μs VDD 20V AD RC mode 131 TCNV Conversion Time not including acquisition time Note 2 11 12 TAD 132 TACQ Acquisition Time Note 3 14 μs 40C to 85C 135 TSWC Switching Time from Convert Sample Note 4 TBD TDIS Discharge Time 02 μs Note 1 The time of the AD clock period is dependent on the device frequency and the TAD clock divider 2 ADRES register may be read on the following TCY cycle 3 The time for the holding capacitor to acquire the New input voltage when the voltage changes full scale after the conversion VDD to VSS or VSS to VDD The source impedance RS on the input channels is 50Ω 4 On the following cycle of the device clock 131 130 132 BSF ADCON0 GO Q4 AD CLK1 AD DATA ADRES ADIF GO SAMPLE OLDDATA SAMPLING STOPPED DONE NEWDATA Note 2 9 8 7 2 1 0 Note 1 If the AD clock source is selected as RC a time of TCY is added before the AD clock starts This allows the SLEEP instruction to be executed 2 This is a minimal RC delay typically 100 ns which also disconnects the holding capacitor from the analog input TCY PIC18F2420252044204520 DS39631Epage 360 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 361 PIC18F2420252044204520 270 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Typical represents the mean of the distribution at 25C Maximum or minimum represents mean 3σ or mean 3σ respectively where σ is a standard deviation over the whole temperature range FIGURE 271 SLEEP MODE Note The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only The performance characteristics listed herein are not tested or guaranteed In some graphs or tables the data presented may be outside the specified operating range eg outside specified power supply range and therefore outside the warranted range 001 01 1 10 100 50 25 0 25 50 75 100 125 Temp C Ipd uA 55 50 45 40 35 30 25 20 Test instrument results are compressed to about 005 μA for actual values below 005 mA Measurements below 001 mA are suspect and considered unmeasurable This is supported by the instrument specifications PIC18F2420252044204520 DS39631Epage 362 2008 Microchip Technology Inc FIGURE 272 TYPICAL IPD vs VDD ACROSS TEMPERATURE SLEEP MODE FIGURE 273 MAXIMUM IPD vs VDD ACROSS TEMPERATURE SLEEP MODE 001 01 1 10 100 20 25 30 35 40 45 50 55 VDD V IPD uA 125C 85C 25C 40C 001 01 1 10 100 20 25 30 35 40 45 50 55 VDD V IPD uA 125C 85C 25C 40C 2008 Microchip Technology Inc DS39631Epage 363 PIC18F2420252044204520 FIGURE 274 TYPICAL T1OSC DELTA CURRENT vs VDD ACROSS TEMP DEVICE IN SLEEP T1OSC IN LOWPOWER MODE FIGURE 275 MAXIMUM T1OSC DELTA CURRENT vs VDD ACROSS TEMP DEVICE IN SLEEP TIOSC IN LOWPOWER MODE 00 05 10 15 20 25 30 20 25 30 35 40 45 50 55 VDD V IPD uA 85C 25C 10C 0 1 2 3 4 20 25 30 35 40 45 50 55 VDD V IPD uA 85C 25C 10C PIC18F2420252044204520 DS39631Epage 364 2008 Microchip Technology Inc FIGURE 276 TYPICAL T1OSC DELTA CURRENT vs VDD ACROSS TEMP DEVICE IN SLEEP T1OSC IN HIGHPOWER MODE FIGURE 277 MAXIMUM T1OSC DELTA CURRENT vs VDD ACROSS TEMP DEVICE IN SLEEP T1OSC IN HIGHPOWER MODE 0 2 4 6 8 10 12 14 16 20 25 30 35 40 45 50 55 DD IPD uA 85C 25C 40C 0 5 10 15 20 25 30 20 25 30 35 40 45 50 55 V DD V IPD uA 85C 25C 40C 2008 Microchip Technology Inc DS39631Epage 365 PIC18F2420252044204520 FIGURE 278 TYPICAL BOR DELTA CURRENT vs VDD ACROSS TEMP BORV 27V SLEEP MODE 2000 2500 3000 3500 4000 4500 5000 5500 2 25 3 35 4 45 5 55 VDD V IPD uA MAX 85C MAX TYP 25C MIN 40C Device in SLEEP Device Held in RESET PIC18F2420252044204520 DS39631Epage 366 2008 Microchip Technology Inc FIGURE 279 TYPICAL WDT CURRENT vs VDD ACROSS TEMPERATURE WDT DELTA CURRENT IN SLEEP MODE FIGURE 2710 MAXIMUM WDT CURRENT vs VDD ACROSS TEMPERATURE WDT DELTA CURRENT IN SLEEP MODE 000 100 200 300 400 500 600 20 25 30 35 40 45 50 55 VDD V IPD uA 125C 85C 25C 40C 00 20 40 60 80 100 120 20 25 30 35 40 45 50 55 VDD V IPD uA 125C 85C 25C 40C 2008 Microchip Technology Inc DS39631Epage 367 PIC18F2420252044204520 FIGURE 2711 TYPICAL IDD ACROSS VDD RCRUN MODE 25C FIGURE 2712 MAXIMUM IDD ACROSS VDD RCRUN MODE 85C 01 1 10 20 25 30 35 40 45 50 55 VDD V IDD mA 8 MHz 4 MHz 2 MHz 1 MHz 250 kHz 500 kHz 125 kHz 42V 01 1 10 20 25 30 35 40 45 50 55 VDD V IDD mA 8 MHz 42V 4 MHz 2 MHz 1 MHz 250 kHz 500 kHz 125 kHz PIC18F2420252044204520 DS39631Epage 368 2008 Microchip Technology Inc FIGURE 2713 TYPICAL AND MAXIMUM IDD ACROSS VDD RCRUN MODE 31 kHz FIGURE 2714 TYPICAL IDD ACROSS VDD RCIDLE MODE 25C 10 100 1000 20 25 30 35 40 45 50 55 VDD V IDD uA Maximum 40C Typical 25C 001 01 1 10 20 25 30 35 40 45 50 55 VDD V IDD mA 8 MHz 42V 4 MHz 2 MHz 1 MHz 250 kHz 500 kHz 125 kHz 2008 Microchip Technology Inc DS39631Epage 369 PIC18F2420252044204520 FIGURE 2715 MAXIMUM IDD ACROSS VDD RCIDLE MODE 40C TO 85C FIGURE 2716 TYPICAL AND MAXIMUM IDD ACROSS VDD RCIDLE MODE 31 kHz 01 1 10 20 25 30 35 40 45 50 55 VDD V IDD mA 8 MHz 42V 4 MHz 2 MHz 1 MHz 250 kHz 500 kHz 125 kHz 0 5 10 15 20 25 20 25 30 35 40 45 50 55 VDD V IDD uA Maximum 85C Typical 25C PIC18F2420252044204520 DS39631Epage 370 2008 Microchip Technology Inc FIGURE 2717 TYPICAL AND MAXIMUM SECRUN CURRENT vs VDD ACROSS TEMPERATURE T1OSC IN LOWPOWER MODE FIGURE 2718 TYPICAL AND MAXIMUM SECIDLE CURRENT vs VDD ACROSS TEMPERATURE T1OSC IN LOWPOWER MODE 00 200 400 600 800 1000 1200 1400 20 25 30 35 40 45 50 55 VDD V IDD uA Max 10C Typ 25C Typ 85C Typ 10C 00 20 40 60 80 100 120 20 25 30 35 40 45 50 55 VDD V IDD uA Max 85C 140 Typ 85C Typ 10C Typ 25C 2008 Microchip Technology Inc DS39631Epage 371 PIC18F2420252044204520 FIGURE 2719 TYPICAL IDD vs FOSC 500 kHz TO 4 MHz PRIRUN MODE EC CLOCK 25C FIGURE 2720 MAXIMUM IDD vs FOSC 500 kHz TO 4 MHz PRIRUN MODE EC CLOCK 40C TO 125C 00 05 10 15 20 25 30 05 10 15 20 25 30 35 40 Fosc MHz IDD mA 55V 50V 45V 40V 35V 30V 25V 20V 00 05 10 15 20 25 30 35 40 45 05 10 15 20 25 30 35 40 Fosc MHz IDD mA 55V 50V 45V 40V 35V 30V 25V 20V PIC18F2420252044204520 DS39631Epage 372 2008 Microchip Technology Inc FIGURE 2721 TYPICAL IDD vs FOSC 4 MHz TO 40 MHz PRIRUN MODE EC CLOCK 25C FIGURE 2722 MAXIMUM IDD vs FOSC 4 MHz TO 40 MHz PRIRUN MODE EC CLOCK 40C TO 125C 0 2 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 55V 50V 45V 40V 35V 30V 25V 20V 0 2 4 6 8 10 12 14 16 18 20 22 24 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 55V 50V 45V 40V 35V 30V 25V 20V 2008 Microchip Technology Inc DS39631Epage 373 PIC18F2420252044204520 FIGURE 2723 TYPICAL IDD vs FOSC HSPLL PRIRUN MODE 25C FIGURE 2724 MAXIMUM IDD vs FOSC HSPLL PRIRUN MODE 40C 4 6 8 10 12 14 16 18 20 22 24 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 55V 50V 45V 42V 4 6 8 10 12 14 16 18 20 22 24 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 55V 50V 45V 42V PIC18F2420252044204520 DS39631Epage 374 2008 Microchip Technology Inc FIGURE 2725 TYPICAL IDD vs FOSC 500 kHz TO 4 MHz PRIIDLE MODE 25C FIGURE 2726 MAXIMUM IDD vs FOSC 500 kHz TO 4 MHz PRIIDLE MODE 40C TO 125C 00 01 02 03 04 05 06 07 08 09 10 11 05 10 15 20 25 30 35 40 Fosc MHz IDD mA 50V 55V 40V 45V 30V 35V 20V 25V 00 01 02 03 04 05 06 07 08 09 10 11 12 05 10 15 20 25 30 35 40 Fosc MHz IDD mA 50V 55V 40V 45V 30V 35V 20V 25V 2008 Microchip Technology Inc DS39631Epage 375 PIC18F2420252044204520 FIGURE 2727 TYPICAL IDD vs FOSC 4 MHz TO 40 MHz PRIIDLE MODE 25C FIGURE 2728 MAXIMUM IDD vs FOSC 4 MHz TO 40 MHz PRIIDLE MODE 40C TO 125C 0 1 2 3 4 5 6 7 8 9 10 11 12 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 50V 55V 40V 45V 30V 35V 20V 25V 0 1 2 3 4 5 6 7 8 9 10 11 12 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 50V 55V 40V 45V 30V 35V 20V 25V PIC18F2420252044204520 DS39631Epage 376 2008 Microchip Technology Inc FIGURE 2729 TYPICAL IDD vs FOSC HSPLL PRIIDLE MODE 25C FIGURE 2730 MAXIMUM IDD vs FOSC HSPLL PRIIDLE MODE 40C 0 1 2 3 4 5 6 7 8 9 10 11 12 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 55V 50V 45V 42V 0 1 2 3 4 5 6 7 8 9 10 11 12 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc MHz IDD mA 55V 50V 45V 42V 2008 Microchip Technology Inc DS39631Epage 377 PIC18F2420252044204520 FIGURE 2731 VIN ST vs VDD 25C 40C TO 125C FIGURE 2732 VIN TTL vs VDD 25C 40C TO 125C 00 05 10 15 20 25 30 35 40 20 25 30 35 40 45 50 55 VDD V VIN V VIH Max 125C VIH Typ 25C VIH Min 40C VIL Min 125C VIL Typ 25C VIL Max 40C 00 02 04 06 08 10 12 14 16 20 25 30 35 40 45 50 55 VDD V VIN V VIH Min 125C VIH Typ 25C VIH Max 40C PIC18F2420252044204520 DS39631Epage 378 2008 Microchip Technology Inc FIGURE 2733 VOL vs IOL VDD 30V 40C TO 85C FIGURE 2734 VOL vs IOL VDD 50V 40C TO 125C 00 02 04 06 08 10 12 14 16 18 20 0 5 10 15 20 25 IOL ma VOL V Typ 25C Min 40C Max 85C 00 02 04 06 08 10 12 14 16 18 20 0 5 10 15 20 25 IOL ma VOL V Min 40C Max 85C Typ 25C 2008 Microchip Technology Inc DS39631Epage 379 PIC18F2420252044204520 FIGURE 2735 VOH vs IOH VDD 30V 40C TO 85C FIGURE 2736 VOH vs IOH VDD 50V 40C TO 125C 00 05 10 15 20 25 30 0 5 10 15 20 25 IOH ma VOH V Max 40C Typ 25C Min 85C 00 05 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 IOH ma VOH V Max 40C Typ 25C Min 125C PIC18F2420252044204520 DS39631Epage 380 2008 Microchip Technology Inc FIGURE 2737 INTOSC FREQUENCY vs VDD TEMPERATURE 40C 25C 85C 125C FIGURE 2738 INTRC vs VDD ACROSS TEMPERATURE 40C TO 125C 76 77 78 79 80 81 82 83 84 20 25 30 35 40 45 50 55 VDD V Freq MHz Max Freq 125C Typ 85C Typ 25C Typ 40C Typ Min Freq 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 20 25 30 35 40 45 50 55 VDD V Freq kHz Max 125C Max 40C Typ 25C Min 85C Min 125C 2008 Microchip Technology Inc DS39631Epage 381 PIC18F2420252044204520 FIGURE 2739 WDT PERIOD vs VDD ACROSS TEMPERATURE 11 POSTSCALER 40C TO 125C 30 32 34 36 38 40 42 44 46 20 25 30 35 40 45 50 55 VDD V Period ms Longest Typical 25C Shortest 85C Shortest 125C PIC18F2420252044204520 DS39631Epage 382 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 383 PIC18F2420252044204520 280 PACKAGING INFORMATION 281 Package Marking Information 28Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F2520ISP 0810017 28Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F2520ESO 0810017 Legend XXX Customerspecific information Y Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code Pbfree JEDEC designator for Matte Tin Sn This package is Pbfree The Pbfree JEDEC designator can be found on the outer packaging for this package Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customerspecific information 3 e 3 e 3 e 3 e 28Lead QFN XXXXXXXX XXXXXXXX YYWWNNN Example 18F2420 IML 0810017 e3 PIC18F2420252044204520 DS39631Epage 384 2008 Microchip Technology Inc Package Marking Information Continued 44Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Example PIC18F4420 IPT 0810017 XXXXXXXXXX 44Lead QFN XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F4520 Example IML 0810017 3 e 3 e 40Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F4420IP 0810017 e3 PIC18F2420252044204520 28Lead Skinny Plastic Dual InLine SP 300 mil Body SPDIP Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 100 BSC Top to Seating Plane A 200 Molded Package Thickness A2 120 135 150 Base to Seating Plane A1 015 Shoulder to Shoulder Width E 290 310 335 Molded Package Width E1 240 285 295 Overall Length D 1345 1365 1400 Tip to Seating Plane L 110 130 150 Lead Thickness c 008 010 015 Upper Lead Width b1 040 050 070 Lower Lead Width b 014 018 022 Overall Row Spacing eB 430 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Significant Characteristic 3 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 per side 4 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing C04070B PIC18F2420252044204520 28Lead Plastic Small Outline SO Wide 750 mm Body SOIC Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 127 BSC Overall Height A 265 Molded Package Thickness A2 205 Standoff A1 010 030 Overall Width E 1030 BSC Molded Package Width E1 750 BSC Overall Length D 1790 BSC Chamfer optional h 025 075 Foot Length L 040 127 Footprint L1 140 REF Foot Angle Top φ 0 8 Lead Thickness c 018 033 Lead Width b 031 051 Mold Draft Angle Top α 5 15 Mold Draft Angle Bottom β 5 15 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Significant Characteristic 3 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 015 mm per side 4 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04052B PIC18F2420252044204520 28Lead Plastic Quad Flat No Lead Package ML 6x6 mm Body QFN with 055 mm Contact Length Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 065 BSC Overall Height A 080 090 100 Standoff A1 000 002 005 Contact Thickness A3 020 REF Overall Width E 600 BSC Exposed Pad Width E2 365 370 420 Overall Length D 600 BSC Exposed Pad Length D2 365 370 420 Contact Width b 023 030 035 Contact Length L 050 055 070 ContacttoExposed Pad K 020 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Package is saw singulated 3 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04105B PIC18F2420252044204520 28Lead Plastic Quad Flat No Lead Package ML 6x6 mm Body QFN with 055 mm Contact Length Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging RECOMMENDED LAND PATTERN SILK SCREEN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 065 BSC Optional Center Pad Width W2 425 Optional Center Pad Length T2 425 Contact Pad Spacing C1 570 Contact Pad Spacing C2 570 Contact Pad Width X28 X1 037 Contact Pad Length X28 Y1 100 Distance Between Pads G 020 Notes 1 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing No C042105A PIC18F2420252044204520 40Lead Plastic Dual InLine P 600 mil Body PDIP Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 40 Pitch e 100 BSC Top to Seating Plane A 250 Molded Package Thickness A2 125 195 Base to Seating Plane A1 015 Shoulder to Shoulder Width E 590 625 Molded Package Width E1 485 580 Overall Length D 1980 2095 Tip to Seating Plane L 115 200 Lead Thickness c 008 015 Upper Lead Width b1 030 070 Lower Lead Width b 014 023 Overall Row Spacing eB 700 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Significant Characteristic 3 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 per side 4 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing C04016B PIC18F2420252044204520 44Lead Plastic Quad Flat No Lead Package ML 8x8 mm Body QFN Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 44 Pitch e 065 BSC Overall Height A 080 090 100 Standoff A1 000 002 005 Contact Thickness A3 020 REF Overall Width E 800 BSC Exposed Pad Width E2 630 645 680 Overall Length D 800 BSC Exposed Pad Length D2 630 645 680 Contact Width b 025 030 038 Contact Length L 030 040 050 ContacttoExposed Pad K 020 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Package is saw singulated 3 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04103B PIC18F2420252044204520 44Lead Plastic Quad Flat No Lead Package ML 8x8 mm Body QFN Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 065 BSC Optional Center Pad Width W2 680 Optional Center Pad Length T2 680 Contact Pad Spacing C1 800 Contact Pad Spacing C2 800 Contact Pad Width X44 X1 035 Contact Pad Length X44 Y1 080 Distance Between Pads G 025 Notes 1 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing No C042103A 2008 Microchip Technology Inc DS39631Epage 391 PIC18F2420252044204520 44Lead Plastic Thin Quad Flatpack PT 10x10x1 mm Body 200 mm TQFP Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 080 BSC Overall Height A 120 Molded Package Thickness A2 095 100 105 Standoff A1 005 015 Foot Length L 045 060 075 Footprint L1 100 REF Foot Angle φ 0 35 7 Overall Width E 1200 BSC Overall Length D 1200 BSC Molded Package Width E1 1000 BSC Molded Package Length D1 1000 BSC Lead Thickness c 009 020 Lead Width b 030 037 045 Mold Draft Angle Top α 11 12 13 Mold Draft Angle Bottom β 11 12 13 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Chamfers at corners are optional size may vary 3 Dimensions D1 and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 025 mm per side 4 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04076B 2008 Microchip Technology Inc DS39631Epage 392 PIC18F2420252044204520 44Lead Plastic Thin Quad Flatpack PT 10x10x1 mm Body 200 mm TQFP Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 080 BSC Contact Pad Spacing C1 1140 Contact Pad Spacing C2 1140 Contact Pad Width X44 X1 055 Contact Pad Length X44 Y1 150 Distance Between Pads G 025 Notes 1 Dimensioning and tolerancing per ASME Y145M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing No C042076A 2008 Microchip Technology Inc DS39631Epage 393 PIC18F2420252044204520 DS39631Epage 394 2008 Microchip Technology Inc NOTES 2008 Microchip Technology Inc DS39631Epage 395 PIC18F2420252044204520 APPENDIX A REVISION HISTORY Revision A June 2004 Original data sheet for PIC18F2420252044204520 devices Revision B January 2007 This revision includes updates to the packaging diagrams Revision C June 2007 This revision includes updates to Section 60 Flash Program Memory Section 230 Special Features of the CPU Section 260 Electrical Characteris tics and minor corrections applicable to Timer1 EUSART and the packaging diagrams Also added the 125C specifications Revision D July 2007 This revision updated the extended temperature information in Section 260 Electrical Characteris tics Revision E October 2008 This revision updated Section 260 Electrical Charac teristics Section 270 DC and AC Characteristics Graphs and Tables and Section 280 Packaging Information APPENDIX B DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B1 TABLE B1 DEVICE DIFFERENCES Features PIC18F2420 PIC18F2520 PIC18F4420 PIC18F4520 Program Memory Bytes 16384 32768 16384 32768 Program Memory Instructions 8192 16384 8192 16384 Interrupt Sources 19 19 20 20 IO Ports Ports A B C E Ports A B C E Ports A B C D E Ports A B C D E CaptureComparePWM Modules 2 2 1 1 Enhanced CaptureComparePWM Modules 0 0 1 1 Parallel Communications PSP No No Yes Yes 10Bit AnalogtoDigital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Packages 28Pin SPDIP 28Pin SOIC 28Pin QFN 28Pin SPDIP 28Pin SOIC 28Pin QFN 40Pin PDIP 44Pin TQFP 44Pin QFN 40Pin PDIP 44Pin TQFP 44Pin QFN PIC18F2420252044204520 DS39631Epage 396 2008 Microchip Technology Inc APPENDIX C MIGRATION FROM MIDRANGE TO ENHANCED DEVICES A detailed discussion of the differences between the midrange MCU devices ie PIC16CXXX and the enhanced devices ie PIC18FXXX is provided in AN716 Migrating Designs from PIC16C74A74B to PIC18C442 The changes discussed while device specific are generally applicable to all midrange to enhanced device migrations This Application Note is available as Literature Number DS00716 APPENDIX D MIGRATION FROM HIGHEND TO ENHANCED DEVICES A detailed discussion of the migration pathway and dif ferences between the highend MCU devices ie PIC17CXXX and the enhanced devices ie PIC18FXXX is provided in AN726 PIC17CXXX to PIC18CXXX Migration This Application Note is available as Literature Number DS00726 DS39631Epage 397 2008 Microchip Technology Inc PIC18F2420252044204520 INDEX A AD 223 Acquisition Requirements 228 ADCON0 Register223 ADCON1 Register223 ADCON2 Register223 ADRESH Register223 226 ADRESL Register 223 Analog Port Pins Configuring230 Associated Registers 232 Configuring the Module 227 Conversion Clock TAD 229 Conversion Status GODONE Bit 226 Conversions 231 Converter Characteristics359 Converter Interrupt Configuring227 Discharge231 Operation in PowerManaged Modes 230 Selecting and Configuring Acquisition Time229 Special Event Trigger CCP232 Special Event Trigger ECCP 148 Use of the CCP2 Trigger232 Absolute Maximum Ratings321 AC Timing Characteristics 340 Load Conditions for Device Timing Specifications 341 Parameter Symbology340 Temperature and Voltage Specifications 341 Timing Conditions 341 AC Characteristics Internal RC Accuracy 343 Access Bank Mapping with Indexed Literal Offset Mode72 ACKSTAT191 ACKSTAT Status Flag191 ADCON0 Register223 GODONE Bit 226 ADCON1 Register223 ADCON2 Register223 ADDFSR310 ADDLW 273 ADDULNK 310 ADDWF 273 ADDWFC274 ADRESH Register223 ADRESL Register223 226 AnalogtoDigital Converter See AD ANDLW 274 ANDWF 275 Assembler MPASM Assembler 318 AutoWakeup on Sync Break Character 214 B Bank Select Register BSR59 Baud Rate Generator 187 BC 275 BCF 276 BF191 BF Status Flag191 Block Diagrams AD 226 Analog Input Model 227 Baud Rate Generator 187 Capture Mode Operation 141 Comparator Analog Input Model 237 Comparator IO Operating Modes 234 Comparator Output 236 Comparator Voltage Reference 240 Comparator Voltage Reference Output Buffer Example 241 Compare Mode Operation 142 Device Clock 28 Enhanced PWM 149 EUSART Receive 213 EUSART Transmit 211 External Poweron Reset Circuit Slow VDD Powerup 43 FailSafe Clock Monitor FSCM 261 Generic IO Port 105 HighLowVoltage Detect with External Input 244 Interrupt Logic 92 MSSP I2C Master Mode 185 MSSP I2C Mode 170 MSSP SPI Mode 161 OnChip Reset Circuit 41 PIC18F24202520 10 PIC18F44204520 11 PLL HS Mode 25 PORTD and PORTE Parallel Slave Port 120 PWM Operation Simplified 144 Reads from Flash Program Memory 77 Single Comparator 235 Table Read Operation 73 Table Write Operation 74 Table Writes to Flash Program Memory 79 Timer0 in 16Bit Mode 124 Timer0 in 8Bit Mode 124 Timer1 128 Timer1 16Bit ReadWrite Mode 128 Timer2 134 Timer3 136 Timer3 16Bit ReadWrite Mode 136 Watchdog Timer 258 BN 276 BNC 277 BNN 277 BNOV 278 BNZ 278 BOR See Brownout Reset BOV 281 BRA 279 Break Character 12Bit Transmit and Receive 216 BRG See Baud Rate Generator Brownout Reset BOR 44 Detecting 44 Disabling in Sleep Mode 44 Software Enabled 44 BSF 279 BTFSC 280 BTFSS 280 BTG 281 BZ 282 PIC18F2420252044204520 DS39631Epage 398 2008 Microchip Technology Inc C C Compilers MPLAB C18 318 MPLAB C30 318 CALL 282 CALLW311 Capture CCP Module141 Associated Registers 143 CCP Pin Configuration141 CCPRxHCCPRxL Registers 141 Prescaler141 Software Interrupt 141 Timer1Timer3 Mode Selection141 Capture ECCP Module 148 CaptureComparePWM CCP139 Capture Mode See Capture CCP Mode and Timer Resources 140 CCPRxH Register 140 CCPRxL Register140 Compare Mode See Compare Interaction of Two CCP Modules 140 Module Configuration140 Clock Sources28 Selecting the 31 kHz Source29 Selection Using OSCCON Register29 CLRF283 CLRWDT283 Code Examples 16 x 16 Signed Multiply Routine 90 16 x 16 Unsigned Multiply Routine 90 8 x 8 Signed Multiply Routine 89 8 x 8 Unsigned Multiply Routine 89 Changing Between Capture Prescalers141 Computed GOTO Using an Offset Value56 Data EEPROM Read 85 Data EEPROM Refresh Routine86 Data EEPROM Write 85 Erasing a Flash Program Memory Row 78 Fast Register Stack56 How to Clear RAM Bank 1 Using Indirect Addressing 68 Implementing a RealTime Clock Using a Timer1 Interrupt Service 131 Initializing PORTA105 Initializing PORTB108 Initializing PORTC111 Initializing PORTD114 Initializing PORTE117 Loading the SSPBUF SSPSR Register164 Reading a Flash Program Memory Word 77 Saving STATUS WREG and BSR Registers in RAM103 Writing to Flash Program Memory 8081 Code Protection 249 COMF284 Comparator 233 Analog Input Connection Considerations237 Associated Registers 237 Configuration234 Effects of a Reset236 Interrupts236 Operation 235 Operation During Sleep 236 Outputs 235 Reference 235 External Signal 235 Internal Signal 235 Response Time 235 Comparator Specifications 338 Comparator Voltage Reference 239 Accuracy and Error 240 Associated Registers 241 Configuring 239 Connection Considerations 240 Effects of a Reset 240 Operation During Sleep 240 Compare CCP Module 142 Associated Registers 143 CCPRx Register 142 Pin Configuration 142 Software Interrupt 142 Special Event Trigger 137 142 232 Timer1Timer3 Mode Selection 142 Compare ECCP Module 148 Special Event Trigger 148 Computed GOTO 56 Configuration Bits 249 Configuration Register Protection 266 Context Saving During Interrupts 103 CPFSEQ 284 CPFSGT 285 CPFSLT 285 Crystal OscillatorCeramic Resonator 23 Customer Change Notification Service 407 Customer Notification Service 407 Customer Support 407 D Data Addressing Modes 68 Comparing Addressing Modes with the Extended Instruction Set Enabled 71 Direct 68 Indexed Literal Offset 70 Instructions Affected 70 Indirect 68 Inherent and Literal 68 Data EEPROM Code Protection 266 Data EEPROM Memory 83 Associated Registers 87 EEADR Register 83 EECON1 and EECON2 Registers 83 Operation During CodeProtect 86 Protection Against Spurious Write 86 Reading 85 Using 86 Write Verify 85 Writing 85 Data Memory 59 Access Bank 62 and the Extended Instruction Set 70 Bank Select Register BSR 59 General Purpose Registers 62 Map for PIC18F24204420 60 Map for PIC18F25204520 61 Special Function Registers 63 DAW 286 DC and AC Characteristics Graphs and Tables 361 DS39631Epage 399 2008 Microchip Technology Inc PIC18F2420252044204520 DC Characteristics 335 PowerDown and Supply Current325 Supply Voltage324 DCFSNZ287 DECF286 DECFSZ287 Development Support317 Device Differences 395 Device Overview 7 Details on Individual Family Members 8 Features table9 New Core Features 7 Other Special Features 8 Device Reset Timers45 Oscillator Startup Timer OST 45 PLL Lock Timeout 45 Powerup Timer PWRT45 Timeout Sequence45 Direct Addressing69 E Effect on Standard PIC MCU Instructions314 Effects of PowerManaged Modes on Various Clock Sources31 Electrical Characteristics321 Enhanced CaptureComparePWM ECCP 147 Associated Registers 160 Capture and Compare Modes148 Capture Mode See Capture ECCP Module Outputs and Configuration 148 Pin Configurations for ECCP148 PWM Mode See PWM ECCP Module Standard PWM Mode148 Timer Resources148 Enhanced PWM Mode See PWM ECCP Module Enhanced Universal Synchronous Asynchronous Receiver Transmitter EUSART See EUSART Equations AD Acquisition Time228 AD Minimum Charging Time228 Calculating the Minimum Required Acquisition Time228 Errata6 EUSART Asynchronous Mode 211 12Bit Break Transmit and Receive 216 Associated Registers Receive 214 Associated Registers Transmit 212 AutoWakeup on Sync Break214 Receiver213 Setting up 9Bit Mode with Address Detect 213 Transmitter211 Baud Rate Generator Operation in PowerManaged Mode 205 Baud Rate Generator BRG205 Associated Registers 206 AutoBaud Rate Detect 209 Baud Rate Error Calculating 206 Baud Rates Asynchronous Modes207 High Baud Rate Select BRGH Bit205 Sampling 205 Synchronous Master Mode 217 Associated Registers Receive 219 Associated Registers Transmit 218 Reception 219 Transmission 217 Synchronous Slave Mode 220 Associated Registers Receive 221 Associated Registers Transmit 220 Reception 221 Transmission 220 Extended Instruction Set ADDFSR 310 ADDULNK 310 and Using MPLAB IDE Tools 316 CALLW 311 Considerations for Use 314 MOVSF 311 MOVSS 312 PUSHL 312 SUBFSR 313 SUBULNK 313 Syntax 309 External Clock Input 24 F FailSafe Clock Monitor 249 261 Exiting Operation 261 Interrupts in PowerManaged Modes 262 POR or Wake from Sleep 262 WDT During Oscillator Failure 261 Fast Register Stack 56 Firmware Instructions 267 Flash Program Memory 73 Associated Registers 81 Control Registers 74 EECON1 and EECON2 74 TABLAT Table Latch Register 76 TBLPTR Table Pointer Register 76 Erase Sequence 78 Erasing 78 Operation During CodeProtect 81 Reading 77 Table Pointer Boundaries Based on Operation 76 Table Pointer Boundaries 76 Table Reads and Table Writes 73 Write Sequence 79 Writing To 79 Protection Against Spurious Writes 81 Unexpected Termination 81 Write Verify 81 FSCM See FailSafe Clock Monitor G General Call Address Support 184 GOTO 288 H Hardware Multiplier 89 Introduction 89 Operation 89 Performance Comparison 89 PIC18F2420252044204520 DS39631Epage 400 2008 Microchip Technology Inc HighLowVoltage Detect Applications246 Associated Registers 247 Characteristics 339 Current Consumption245 Effects of a Reset247 Operation 244 During Sleep 247 Setup245 Startup Time 245 Typical Application 246 HLVD See HighLowVoltage Detect I IO Ports105 I2C Mode MSSP Acknowledge Sequence Timing194 Baud Rate Generator187 Bus Collision During a Repeated Start Condition198 During a Stop Condition199 Clock Arbitration188 Clock Stretching180 10Bit Slave Receive Mode SEN 1180 10Bit Slave Transmit Mode180 7Bit Slave Receive Mode SEN 1180 7Bit Slave Transmit Mode180 Clock Synchronization and the CKP bit SEN 1181 Effects of a Reset195 General Call Address Support 184 I2C Clock Rate wBRG187 Master Mode185 Operation 186 Reception191 Repeated Start Condition Timing190 Start Condition Timing 189 Transmission191 MultiMaster Communication Bus Collision and Arbitration195 MultiMaster Mode 195 Operation 174 ReadWrite Bit Information RW Bit 174 175 Registers170 Serial Clock RC3SCKSCL175 Slave Mode174 Addressing174 Reception175 Transmission175 Sleep Operation 195 Stop Condition Timing194 ID Locations 249 266 INCF288 INCFSZ 289 InCircuit Debugger266 InCircuit Serial Programming ICSP 249 266 Indexed Literal Offset Addressing and Standard PIC18 Instructions 314 Indexed Literal Offset Mode314 Indirect Addressing 69 INFSNZ 289 Initialization Conditions for all Registers 4952 Instruction Cycle57 Clocking Scheme 57 Instruction FlowPipelining 57 Instruction Set 267 ADDLW 273 ADDWF 273 ADDWF Indexed Literal Offset Mode 315 ADDWFC 274 ANDLW 274 ANDWF 275 BC 275 BCF 276 BN 276 BNC 277 BNN 277 BNOV 278 BNZ 278 BOV 281 BRA 279 BSF 279 BSF Indexed Literal Offset Mode 315 BTFSC 280 BTFSS 280 BTG 281 BZ 282 CALL 282 CLRF 283 CLRWDT 283 COMF 284 CPFSEQ 284 CPFSGT 285 CPFSLT 285 DAW 286 DCFSNZ 287 DECF 286 DECFSZ 287 Extended Instruction Set 309 General Format 269 GOTO 288 INCF 288 INCFSZ 289 INFSNZ 289 IORLW 290 IORWF 290 LFSR 291 MOVF 291 MOVFF 292 MOVLB 292 MOVLW 293 MOVWF 293 MULLW 294 MULWF 294 NEGF 295 NOP 295 Opcode Field Descriptions 268 POP 296 PUSH 296 RCALL 297 RESET 297 RETFIE 298 RETLW 298 RETURN 299 RLCF 299 RLNCF 300 RRCF 300 RRNCF 301 SETF 301 SETF Indexed Literal Offset Mode 315 SLEEP 302 DS39631Epage 401 2008 Microchip Technology Inc PIC18F2420252044204520 Standard Instructions 267 SUBFWB302 SUBLW 303 SUBWF 303 SUBWFB304 SWAPF 304 TBLRD 305 TBLWT 306 TSTFSZ307 XORLW307 XORWF308 INTCON Registers 9395 InterIntegrated Circuit See I2C Internal Oscillator Block26 Adjustment 26 INTIO Modes26 INTOSC Frequency Drift 26 INTOSC Output Frequency26 OSCTUNE Register 26 PLL in INTOSC Modes26 Internal RC Oscillator Use with WDT 258 Internet Address407 Interrupt Sources249 AD Conversion Complete227 Capture Complete CCP141 Compare Complete CCP142 InterruptonChange RB7RB4 108 INTx Pin 103 PORTB InterruptonChange 103 TMR0 103 TMR0 Overflow 125 TMR1 Overflow 127 TMR2 to PR2 Match PWM 144 149 TMR3 Overflow 135 137 Interrupts 91 Interrupts Flag Bits InterruptonChange RB7RB4 Flag RBIF Bit 108 INTOSC INTRC See Internal Oscillator Block IORLW290 IORWF 290 IPR Registers 100101 L LFSR 291 LowVoltage ICSP Programming See SingleSupply ICSP Programming M Master Clear MCLR 43 Master Synchronous Serial Port MSSP See MSSP Memory Organization53 Data Memory59 Program Memory 53 Memory Programming Requirements 337 Microchip Internet Web Site 407 Migration from HighEnd to Enhanced Devices 396 Migration from MidRange to Enhanced Devices396 MOVF291 MOVFF292 MOVLB292 MOVLW293 MOVSF311 MOVSS 312 MOVWF293 MPLAB ASM30 Assembler Linker Librarian 318 MPLAB ICD 2 InCircuit Debugger 319 MPLAB ICE 2000 HighPerformance Universal InCircuit Emulator 319 MPLAB Integrated Development Environment Software 317 MPLAB PM3 Device Programmer 319 MPLAB REAL ICE InCircuit Emulator System 319 MPLINK Object LinkerMPLIB Object Librarian 318 MSSP ACK Pulse 174 175 Control Registers general 161 I2C Mode See I2C Mode Module Overview 161 SPI MasterSlave Connection 165 SPI Mode See SPI Mode SSPBUF Register 166 SSPSR Register 166 MULLW 294 MULWF 294 N NEGF 295 NOP 295 O Oscillator Configuration 23 EC 23 ECIO 23 HS 23 HSPLL 23 Internal Oscillator Block 26 INTIO1 23 INTIO2 23 LP 23 RC 23 RCIO 23 XT 23 Oscillator Selection 249 Oscillator Startup Timer OST 31 45 Oscillator Switching 28 Oscillator Transitions 29 Oscillator Timer1 127 137 Oscillator Timer3 135 P Packaging Information 383 Details 385 Marking 383 Parallel Slave Port PSP 114 120 Associated Registers 121 CS Chip Select 120 PORTD 120 RD Read Input 120 Select PSPMODE Bit 114 120 WR Write Input 120 PICSTART Plus Development Programmer 320 PIE Registers 9899 Pin Functions MCLRVPPRE3 12 16 OSC1CLKIRA7 12 16 OSC2CLKORA6 12 16 RA0AN0 13 17 RA1AN1 13 17 RA2AN2VREFCVREF 13 17 RA3AN3VREF 13 17 PIC18F2420252044204520 DS39631Epage 402 2008 Microchip Technology Inc RA4T0CKIC1OUT13 17 RA5AN4SSHLVDINC2OUT 13 17 RB0INT0FLT0AN1214 18 RB1INT1AN10 14 18 RB2INT2AN8 14 18 RB3AN9CCP2 14 18 RB4KBI0AN11 14 18 RB5KBI1PGM 14 18 RB6KBI2PGC 14 18 RB7KBI3PGD 14 18 RC0T1OSOT13CKI 15 19 RC1T1OSICCP2 15 19 RC2CCP1 15 RC2CCP1P1A 19 RC3SCKSCL 15 19 RC4SDISDA 15 19 RC5SDO 15 19 RC6TXCK 15 19 RC7RXDT 15 19 RD0PSP020 RD1PSP120 RD2PSP220 RD3PSP320 RD4PSP420 RD5PSP5P1B20 RD6PSP6P1C20 RD7PSP7P1D20 RE0RDAN521 RE1WRAN6 21 RE2CSAN721 VDD 15 21 VSS 15 21 Pinout IO Descriptions PIC18F2420252012 PIC18F4420452016 PIR Registers9697 PLL Frequency Multiplier 25 HSPLL Oscillator Mode25 Use with INTOSC25 POP296 POR See Poweron Reset PORTA Associated Registers 107 LATA Register105 PORTA Register 105 TRISA Register 105 PORTB Associated Registers 110 LATB Register108 PORTB Register 108 RB7RB4 InterruptonChange Flag RBIF Bit 108 TRISB Register 108 PORTC Associated Registers 113 LATC Register 111 PORTC Register 111 RC3SCKSCL Pin 175 TRISC Register111 PORTD Associated Registers 116 LATD Register 114 Parallel Slave Port PSP Function 114 PORTD Register 114 TRISD Register114 PORTE Associated Registers 119 LATE Register 117 PORTE Register 117 PSP Mode Select PSPMODE Bit 114 TRISE Register 117 PowerManaged Modes 33 and AD Operation 230 and EUSART Operation 205 and Multiple Sleep Commands 34 and PWM Operation 159 and SPI Operation 169 Clock Transitions and Status Indicators 34 Effects on Clock Sources 31 Entering 33 Exiting Idle and Sleep Modes 39 by Interrupt 39 by Reset 39 by WDT Timeout 39 Without a Startup Delay 40 Idle Modes 37 PRIIDLE 38 RCIDLE 39 SECIDLE 38 Run Modes 34 PRIRUN 34 RCRUN 35 SECRUN 34 Selecting 33 Sleep Mode 37 Summary table 33 Poweron Reset POR 43 Powerup Timer PWRT 45 Timeout Sequence 45 Powerup Delays 31 Powerup Timer PWRT 31 Prescaler Timer2 150 Prescaler Timer0 125 Prescaler Timer2 145 PRIIDLE Mode 38 PRIRUN Mode 34 Program Counter 54 PCL PCH and PCU Registers 54 PCLATH and PCLATU Registers 54 Program Memory and Extended Instruction Set 72 Code Protection 264 Instructions 58 TwoWord 58 Interrupt Vector 53 Lookup Tables 56 Map and Stack diagram 53 Reset Vector 53 Program Verification and Code Protection 263 Associated Registers 263 Programming Device Instructions 267 PSP See Parallel Slave Port PulseWidth Modulation See PWM CCP Module and PWM ECCP Module PUSH 296 PUSH and POP Instructions 55 PUSHL 312 DS39631Epage 403 2008 Microchip Technology Inc PIC18F2420252044204520 PWM CCP Module Associated Registers 146 AutoShutdown CCP1 Only 145 Duty Cycle144 Example FrequenciesResolutions145 Period144 Setup for PWM Operation 145 TMR2 to PR2 Match144 PWM ECCP Module 149 CCPR1HCCPR1L Registers149 Direction Change in FullBridge Output Mode 154 Duty Cycle150 Effects of a Reset159 Enhanced PWM AutoShutdown156 Example FrequenciesResolutions150 FullBridge Mode153 FullBridge Output Mode Application Example 154 HalfBridge Mode 152 HalfBridge Output Mode Applications Example 152 Operation in PowerManaged Modes 159 Operation with FailSafe Clock Monitor159 Output Configurations 150 Output Relationships ActiveHigh 151 Output Relationships ActiveLow151 Period149 Programmable DeadBand Delay 156 Setup for PWM Operation 159 Startup Considerations 158 TMR2 to PR2 Match149 Q Q Clock145 150 R RAM See Data Memory RBIF Bit108 RC Oscillator 25 RCIO Oscillator Mode 25 RCIDLE Mode 39 RCRUN Mode 35 RCALL297 RCON Register Bit Status During Initialization 48 Reader Response 408 Register File 62 Register File Summary6466 Registers ADCON0 AD Control 0 223 ADCON1 AD Control 1 224 ADCON2 AD Control 2 225 BAUDCON Baud Rate Control 204 CCP1CON ECCP Control 4044Pin Devices147 CCPxCON CCPx Control 28Pin Devices 139 CMCON Comparator Control233 CONFIG1H Configuration 1 High 250 CONFIG2H Configuration 2 High 252 CONFIG2L Configuration 2 Low251 CONFIG3H Configuration 3 High 253 CONFIG4L Configuration 4 Low253 CONFIG5H Configuration 5 High 254 CONFIG5L Configuration 5 Low254 CONFIG6H Configuration 6 High 255 CONFIG6L Configuration 6 Low255 CONFIG7H Configuration 7 High 256 CONFIG7L Configuration 7 Low 256 CVRCON Comparator Voltage Reference Control 239 DEVID1 Device ID 1 257 DEVID2 Device ID 2 257 ECCP1AS ECCP AutoShutdown Control 157 EECON1 EEPROM Control 1 75 84 HLVDCON HighLowVoltage Detect Control 243 INTCON Interrupt Control 93 INTCON2 Interrupt Control 2 94 INTCON3 Interrupt Control 3 95 IPR1 Peripheral Interrupt Priority 1 100 IPR2 Peripheral Interrupt Priority 2 101 OSCCON Oscillator Control 30 OSCTUNE Oscillator Tuning 27 PIE1 Peripheral Interrupt Enable 1 98 PIE2 Peripheral Interrupt Enable 2 99 PIR1 Peripheral Interrupt Request Flag 1 96 PIR2 Peripheral Interrupt Request Flag 2 97 PWM1CON PWM DeadBand Delay 156 RCON Reset Control 42 102 RCSTA Receive Status and Control 203 SSPCON1 MSSP Control 1 I2C Mode 172 SSPCON1 MSSP Control 1 SPI Mode 163 SSPCON2 MSSP Control 2 I2C Mode 173 SSPSTAT MSSP Status I2C Mode 171 SSPSTAT MSSP Status SPI Mode 162 STATUS 67 STKPTR Stack Pointer 55 T0CON Timer0 Control 123 T1CON Timer1 Control 127 T2CON Timer2 Control 133 T3CON Timer3 Control 135 TRISE PORTEPSP Control 118 TXSTA Transmit Status and Control 202 WDTCON Watchdog Timer Control 259 RESET 297 Reset State of Registers 48 Resets 41 249 Brownout Reset BOR 249 Oscillator Startup Timer OST 249 Poweron Reset POR 249 Powerup Timer PWRT 249 RETFIE 298 RETLW 298 RETURN 299 Return Address Stack 54 Return Stack Pointer STKPTR 55 Revision History 395 RLCF 299 RLNCF 300 RRCF 300 RRNCF 301 S SCK 161 SDI 161 SDO 161 SECIDLE Mode 38 SECRUN Mode 34 Serial Clock SCK 161 Serial Data In SDI 161 Serial Data Out SDO 161 Serial Peripheral Interface See SPI Mode SETF 301 Slave Select SS 161 PIC18F2420252044204520 DS39631Epage 404 2008 Microchip Technology Inc Slave Select Synchronization167 SLEEP302 Sleep OSC1 and OSC2 Pin States 31 Software Simulator MPLAB SIM318 Special Event Trigger See Compare ECCP Mode Special Event Trigger See Compare ECCP Module Special Features of the CPU249 Special Function Registers Map 63 SPI Mode MSSP Associated Registers 169 Bus Mode Compatibility 169 Effects of a Reset169 Enabling SPI IO 165 Master Mode166 MasterSlave Connection165 Operation 164 Operation in PowerManaged Modes 169 Serial Clock161 Serial Data In 161 Serial Data Out 161 Slave Mode167 Slave Select 161 Slave Select Synchronization 167 SPI Clock 166 Typical Connection 165 SS 161 SSPOV191 SSPOV Status Flag191 SSPSTAT Register RW Bit174 175 Stack FullUnderflow Resets56 STATUS Register67 SUBFSR313 SUBFWB302 SUBLW 303 SUBULNK 313 SUBWF 303 SUBWFB304 SWAPF 304 T Table Pointer Operations with TBLRD and TBLWT 76 Table ReadsTable Writes56 TBLRD 305 TBLWT306 Timeout in Various Situations table45 Timer0123 Associated Registers 125 Operation 124 Overflow Interrupt 125 Prescaler125 Prescaler Assignment PSA Bit 125 Prescaler Select T0PS2T0PS0 Bits 125 Prescaler See Prescaler Timer0 Reads and Writes in 16Bit Mode 124 Source Edge Select T0SE Bit124 Source Select T0CS Bit124 Switching Prescaler Assignment125 Timer1 127 16Bit ReadWrite Mode 129 Associated Registers 132 Considerations in Asynchronous Counter Mode 131 Interrupt 130 Operation 128 Oscillator 127 129 Oscillator Layout Considerations 130 Overflow Interrupt 127 Resetting Using the CCP Special Event Trigger 130 Special Event Trigger ECCP 148 TMR1H Register 127 TMR1L Register 127 Use as a RealTime Clock 130 Timer2 133 Associated Registers 134 Interrupt 134 Operation 133 Output 134 PR2 Register 144 149 TMR2 to PR2 Match Interrupt 144 149 Timer3 135 16Bit ReadWrite Mode 137 Associated Registers 137 Operation 136 Oscillator 135 137 Overflow Interrupt 135 137 Special Event Trigger CCP 137 TMR3H Register 135 TMR3L Register 135 Timing Diagrams AD Conversion 360 Acknowledge Sequence 194 Asynchronous Reception 214 Asynchronous Transmission 212 Asynchronous Transmission Back to Back 212 Automatic Baud Rate Calculation 210 AutoWakeup Bit WUE During Normal Operation 215 AutoWakeup Bit WUE During Sleep 215 Baud Rate Generator with Clock Arbitration 188 BRG Overflow Sequence 210 BRG Reset Due to SDA Arbitration During Start Condition 197 Brownout Reset BOR 345 Bus Collision During a Repeated Start Condition Case 1 198 Bus Collision During a Repeated Start Condition Case 2 198 Bus Collision During a Start Condition SCL 0 197 Bus Collision During a Stop Condition Case 1 199 Bus Collision During a Stop Condition Case 2 199 Bus Collision During Start Condition SDA only 196 Bus Collision for Transmit and Acknowledge 195 CaptureComparePWM All CCP Modules 347 DS39631Epage 405 2008 Microchip Technology Inc PIC18F2420252044204520 CLKO and IO344 Clock Synchronization181 ClockInstruction Cycle57 EUSART Synchronous Receive MasterSlave359 EUSART Synchronous Transmission MasterSlave358 Example SPI Master Mode CKE 0349 Example SPI Master Mode CKE 1350 Example SPI Slave Mode CKE 0351 Example SPI Slave Mode CKE 1353 External Clock All Modes Except PLL 342 FailSafe Clock Monitor FSCM 262 First Start Bit Timing189 FullBridge PWM Output 153 HalfBridge PWM Output152 HighLowVoltage Detect Characteristics339 HighVoltage Detect Operation VDIRMAG 1246 I2C Bus Data 354 I2C Bus StartStop Bits354 I2C Master Mode 7 or 10Bit Transmission192 I2C Master Mode 7Bit Reception 193 I2C Slave Mode 10Bit Reception SEN 0178 I2C Slave Mode 10Bit Reception SEN 1183 I2C Slave Mode 10Bit Transmission179 I2C Slave Mode 7Bit Reception SEN 0176 I2C Slave Mode 7Bit Reception SEN 1182 I2C Slave Mode 7Bit Transmission177 I2C Slave Mode General Call Address Sequence 7 or 10Bit Addressing Mode184 I2C Stop Condition Receive or Transmit Mode 194 LowVoltage Detect Operation VDIRMAG 0245 Master SSP I2C Bus Data 356 Master SSP I2C Bus StartStop Bits356 Parallel Slave Port PIC18F44204520 348 Parallel Slave Port PSP Read 121 Parallel Slave Port PSP Write121 PWM AutoShutdown PRSEN 0 AutoRestart Disabled158 PWM AutoShutdown PRSEN 1 AutoRestart Enabled158 PWM Direction Change155 PWM Direction Change at Near 100 Duty Cycle155 PWM Output144 Repeated Start Condition190 Reset Watchdog Timer Oscillator Startup Timer Powerup Timer 345 Send Break Character Sequence 216 Slave Synchronization167 Slow Rise Time MCLR Tied to VDD VDD Rise TPWRT 47 SPI Mode Master Mode166 SPI Mode Slave Mode CKE 0168 SPI Mode Slave Mode CKE 1168 Synchronous Reception Master Mode SREN219 Synchronous Transmission217 Synchronous Transmission Through TXEN 218 Timeout Sequence on POR wPLL Enabled MCLR Tied to VDD47 Timeout Sequence on Powerup MCLR Not Tied to VDD Case 146 Timeout Sequence on Powerup MCLR Not Tied to VDD Case 246 Timeout Sequence on Powerup MCLR Tied to VDD VDD Rise TPWRT 46 Timer0 and Timer1 External Clock 346 Transition for Entry to Idle Mode 38 Transition for Entry to SECRUN Mode 35 Transition for Entry to Sleep Mode 37 Transition for TwoSpeed Startup INTOSC to HSPLL 260 Transition for Wake from Idle to Run Mode 38 Transition for Wake from Sleep HSPLL 37 Transition from RCRUN Mode to PRIRUN Mode 36 Transition from SECRUN Mode to PRIRUN Mode HSPLL 35 Transition to RCRUN Mode 36 Timing Diagrams and Specifications 342 AD Conversion Requirements 360 CaptureComparePWM CCP Requirements 347 CLKO and IO Requirements 344 EUSART Synchronous Receive Requirements 359 EUSART Synchronous Transmission Requirements 358 Example SPI Mode Requirements Master Mode CKE 0 349 Example SPI Mode Requirements Master Mode CKE 1 350 Example SPI Mode Requirements Slave Mode CKE 0 352 Example SPI Mode Requirements Slave Mode CKE 1 353 External Clock Requirements 342 I2C Bus Data Requirements Slave Mode 355 Master SSP I2C Bus Data Requirements 357 Master SSP I2C Bus StartStop Bits Requirements 356 Parallel Slave Port Requirements PIC18F44204520 348 PLL Clock 343 Reset Watchdog Timer Oscillator Startup Timer Powerup Timer and Brownout Reset Requirements 345 Timer0 and Timer1 External Clock Requirements 346 TopofStack Access 54 TRISE Register PSPMODE Bit 114 TSTFSZ 307 TwoSpeed Startup 249 260 TwoWord Instructions Example Cases 58 TXSTA Register BRGH Bit 205 V Voltage Reference Specifications 338 PIC18F2420252044204520 DS39631Epage 406 2008 Microchip Technology Inc W Watchdog Timer WDT 249 258 Associated Registers 259 Control Register 258 During Oscillator Failure 261 Programming Considerations 258 WCOL 189 190 191 194 WCOL Status Flag 189 190 191 194 WWW Address407 WWW OnLine Support6 X XORLW 307 XORWF 308 2008 Microchip Technology Inc DS39631Epage 407 PIC18F2420252044204520 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at wwwmicrochipcom This web site is used as a means to make files and information easily available to customers Accessible by using your favorite Internet browser the web site contains the following information Product Support Data sheets and errata application notes and sample programs design resources users guides and hardware support documents latest software releases and archived software General Technical Support Frequently Asked Questions FAQ technical support requests online discussion groups Microchip consultant program member listing Business of Microchip Product selector and ordering guides latest Microchip press releases listing of seminars and events listings of Microchip sales offices distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchips customer notification service helps keep customers current on Microchip products Subscribers will receive email notification whenever there are changes updates revisions or errata related to a specified product family or development tool of interest To register access the Microchip web site at wwwmicrochipcom click on Customer Change Notification and follow the registration instructions CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels Distributor or Representative Local Sales Office Field Application Engineer FAE Technical Support Development Systems Information Line Customers should contact their distributor representative or field application engineer FAE for support Local sales offices are also available to help customers A listing of sales offices and locations is included in the back of this document Technical support is available through the web site at httpsupportmicrochipcom PIC18F2420252044204520 DS39631Epage 408 2008 Microchip Technology Inc READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 480 7924150 Please list the following information and use this outline to provide us with your comments about this document To Technical Publications Manager RE Reader Response Total Pages Sent From Name Company Address City State ZIP Country Telephone Application optional Would you like a reply Y N Device Literature Number Questions FAX DS39631E PIC18F2420252044204520 1 What are the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this document easy to follow If not why 4 What additions to the document do you think would enhance the structure and subject 5 What deletions from the document could be made without affecting the overall usefulness 6 Is there any incorrect or misleading information what and where 7 How would you improve this document 2008 Microchip Technology Inc Advance Information DS39631Epage 409 PIC18F2420252044204520 PIC18F2420252044204520 PRODUCT IDENTIFICATION SYSTEM To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office PART NO X XX XXX Pattern Package Temperature Range Device Device PIC18F242025201 PIC18F442045201 PIC18F24202520T2 PIC18F44204520T2 VDD range 42V to 55V PIC18LF242025201 PIC18LF442045201 PIC18LF24202520T2 PIC18LF44204520T2 VDD range 20V to 55V Temperature Range I 40C to 85C Industrial E 40C to 125C Extended Package PT TQFP Thin Quad Flatpack SO SOIC SP Skinny Plastic DIP P PDIP ML QFN Pattern QTP SQTP Code or Special Requirements blank otherwise Examples a PIC18LF4520IP 301 Industrial temp PDIP package Extended VDD limits QTP pattern 301 b PIC18LF2420ISO Industrial temp SOIC package Extended VDD limits c PIC18F4420IP Industrial temp PDIP package normal VDD limits Note 1 F Standard Voltage Range LF Wide Voltage Range 2 T in tape and reel TQFP packages only DS39631Epage 410 2008 Microchip Technology Inc AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 852246199 Tel 4807927200 Fax 4807927277 Technical Support httpsupportmicrochipcom Web Address wwwmicrochipcom Atlanta Duluth GA Tel 6789579614 Fax 6789571455 Boston Westborough MA Tel 7747600087 Fax 7747600088 Chicago Itasca IL Tel 6302850071 Fax 6302850075 Dallas Addison TX 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