VHDL Design VGA Video Interfaces - Guia Completo

15 VHDL Design of VGA Video Interfaces 151 Introduction VGA video graphics array is a standard interface introduced by IBM in 1987 for connecting computers to analog video monitors figure 151a The circuits responsible for generating processing and storing the video signals are called graphics controller computer side and display controller monitor side figure 151b VGA monitors are CRTs cathode ray tubes Their current most basic resolution is 640 x 480 x 60 Hz VGA it consists of 640 columns by 480 lines of pixels picture elements refreshed 60 times per second see list in figure 152b It employs three colors R red G green B blue per pixel with the intensity of each color determined by an analog voltage in the 0Vto07V range indeed for green it can be either the regular 0Vto07V range or 03 V higher that is 03Vto1V when syncongreen is used explained later To generate the colors six bits per color were initially employed thus allowing a total of 263 266144 distinct colors or shades though only 16 or 256 of them were made available in the original VGA palette Other higherresolution standards succeeded VGA such as SVGA super VGA XGA extended graphics array SXGA super extended graphics array and more see their resolutions in figure 152 Such analog interfaces are collectively referred to as VGA modes with the original 640 x 480 x 60Hz version still being the default mode for most analog computer monitors that is the mode in which PCs operate at the beginning of the startup sequence VGA monitors are now being replaced with LCDs liquid crystal displays which operate differently from CRTs They are fully digital and their standard interface is called DVI digital visual interface Despite its digital behavior in many cases the graphics controller also contains a VGA section so VGA monitors can still be used This option analog digital is called DVII integrated DVI while the digitalonly version is called DVID Details on the theory and design of DVI systems will be given in chapter 16 As in chapters 16 and 17 which also deal with video interfaces here we focus on the following fundamental aspects 1 Operation of the VGA interface 2 How the circuit should be divided to make the design as simple and as standard as possible 3 How the control signals operate and how they should be generated 4 How images can be generated from local hardware external memory file etc rather than focusing on images themselves software 152 VGA Connector Figure 153 shows a VGA connector which is a 15pin connector called DB15 The figure also shows the corresponding pinout defined by the VESA Video Electronics Standards Association through a document called DDC display data channel Observe the following in figure 153 1 The table is separated into two parts with the upper part containing the standard sig nals and the lower part containing the signals used for monitor identification 2 In the upper part three wires are employed for the colors ðR G BÞ which are analog voltages between 0 V and 07 V on two parallel 75 W resistors ¼ 375 W As already men tioned G can be 03 V higher Figure 151 a Computer connected to an analog VGA monitor b Circuits responsible for the video signals graphics con troller on the host side display controller on the device side Figure 152 a Pixel count b Examples of display resolutions collectively called VGA modes 424 Chapter 15 3 Still in the upper part two wires are employed for the horizontal and vertical synchro nization signals Hsync Vsync which consist of 0V5V digital waveforms 4 The remaining six wires in the upper part of the table are either for ground or for an optional þ5V supply voltage 5 Finally the lower part of the table shows the signals used for monitor identification In modern monitors the DDC standard is used described later Note that the pins func tionalities change with the DDC version 153 DDC and EDID The lower part of the table in figure 153 shows three alternatives for monitor identification parameter passing identified as nonDDC DDC1 and DDC2B In the case of nonDDC obsolete the monitor is identified by means of three wires called ID0 ID1 and ID2 ID3 was added later Each of these wires has a pullup resistor connected to VCC on the computer side so the default logic value on these pins is 1 For a 0 to occur the display controller must provide a short circuit to GND A typical monitor Figure 153 The most common VGA connector called DB15 with respective pinout The function of some pins depends on the DDC version The last column shows the simplest possible connection just five active wires plus ground VHDL Design of VGA Video Interfaces 425 identification using ID2ID1ID0 in this order is the following 111 no monitor 101 monochrome monitor with resolution under 1024 x 768 110 color monitor with resolution under 1024 x 768 and 010 color monitor with the 1024 x 768 resolution included DDC display data channel is a standard procedure for computermonitor communication developed by VESA With the introduction of DDC such communication was greatly improved because it allowed much more room for the display to tell its parameters to the graphics controller Such information is stored in a ROM on the monitor side and obeys a standard format called EDID extended display identification data also defined by VESA Up to 128 bytes can be stored in the ROM containing the manufacturers name supported resolutions and other information Such information is made available every time a pulse occurs in Vsync in other words Vsync acts as the memoryread clock ID3 and the 5V supply were also included in DDC1 though monitor identification through ID pins became rapidly obsolete with the EDID structure accessed through pin 12 preferred instead DDC1 was rapidly superseded by DDC2B which introduced an important change in the DDC channel it determined that the EDID data should be transmitted using the I2C bus section 144 I2C is a robust serial interface consisting of just two wires called SDA serial data and SCL serial clock plus the power supply rails VCC and GND Consequently the EDID information must be stored in a ROM that supports I2C access The SDA and SCL lines are pulledup to VCC 5 V or 33 V by 15 kΩ resistors installed on the computer side Since SDA is bidirectional with DDC2B data can now not only be read from the monitor but can also be sent to it thus allowing for example the graphics controller to change the displays setup The 128byte EDID structure was eventually expanded to 256 bytes As already mentioned EDID is a standard data format for storing displayrelated information in a ROM at the monitor Like DDC EDID was also specified by VESA Currently the EDID ROM is accessed using the I2C bus Indeed this combination of EDID with I2C constitutes the monitoridentification part of the DDC2B standard There are several versions of EDID 11 12 13 2 3 encompassing 128 and 256 bytes of display information 154 Circuit Diagram Figure 154 shows a block diagram for a VGA system with the graphics controller on the left and the display controller on the right The VGA interface is the circuit used in the physical layer that interconnects these two controllers see figure 151b As shown in figure 154 the computerside circuit can be divided into four sections image generator control generator EDID interface and finally the DACs digital to analog converters The pixel signals are generated digitally normally with 10 bits then converted to ana log by the three DACs These analog voltages constitute the image that will be displayed by the VGA monitor Contrary to the pixel signals the control signals have a fixed constitution for a given VGA mode of course The whole sequence is controlled by pixelclk whose frequency for the original default VGA is 25175 MHz Five control signals are generated though in many cases not all are needed Hsync horizontal synchronism Vsync vertical syn chronism Hactive portion of Hsync during which pixels are displayed Vactive portion of Vsync during which lines of pixels are displayed and dena display enable Hsync and Vsync are responsible for determining when a new line or new frame should start with their timings also determining the VGA mode Hactive and Vactive represent the time intervals during which an image is actually being drawn on the screen Finally dena is responsible for turning the pixel signals OFF during retrace that is while the elec tron beam returns to the beginning of a new line or of a new frame so it can be obtained by simply ANDing Hactive and Vactive Note that only two of the five control signals are transmitted to the monitor As already mentioned the EDID circuit is responsible for retrieving the monitor specifi cations stored in the EDID ROM Note that all signals in the VGA cable are generated by the host computer and transmitted to the device monitor with the exception of SDA which is bidirectional reads display parameters and can also adjust them Figure 154 VGA interface circuit diagram VHDL Design of VGA Video Interfaces 427 pixelclk Hsync Hactive Hpulse width of Hsync pulse Hactive Active horiz display interval HBP Horizontal Back Porch HFP Horizontal Front Porch VGA mode Horizontal timing in clock pulses same as pixels Name Resolution Refresh Pixel clock Hpulse HBP Hactive HFP Total N x M rate Hz MHz pixels pixels pixels pixels pixels VGA 640 x 480 60 25175 96 48 640 16 800 VGA 640 x 480 75 315 96 48 640 16 800 SVGA 800 x 600 60 40 128 88 800 40 1056 SVGA 800 x 600 75 495 80 160 800 16 1056 SVGA 800 x 600 85 5625 64 152 800 32 1048 XGA 1024 x 768 60 65 136 160 1024 24 1344 XGA 1024 x 768 85 945 96 208 1024 48 1376 SXGA 1280 x 1024 60 108 112 248 1280 48 1688 Figure 155 Examples of VGA modes and corresponding horizontal timing parameters 155 Control Signals As we have seen the control signals are Hsync Vsync Hactive Vactive and dena and their timings define the VGA mode Several such modes are listed in figure 155 where the first line corresponds to the original default VGA Note that in this case the frequency of pixelclk is 25175 MHz Figure 155 also shows the waveforms for Hsync and Hactive based on pixelclk which consist of four parts all measured in number of pixels ie number of clock cycles called Hpulse width of the horizontal synchronization pulse HBP horizontal back porch Hactive active line display interval and HFP horizontal front porch The vertical timing diagram is depicted in figure 156 also consisting of four parts all measured in number of lines or number of Hsync cycles called Vpulse width of the vertical synchronization pulse VBP vertical back porch Vactive active column display interval and VFP vertical front porch For example in the 640 x 480 x 60Hz VGA option the drawing of one line takes 800 clock cycles figure 155 while one frame requires a time equivalent to 525 lines figure 156 Consequently to be able to generate 60 frames per second the clock frequency must be 800 x 525 x 60 25175 MHz which is the value listed in the figures indeed this clock frequency is for a refresh rate of 5994 Hz a value inherited from the NTSC television system The final control signal is dena which must be low during the blanking intervals retrace so it can be easily obtained by ANDing Hactive and Vactive As already mentioned some monitors support also a form of composite sync called syncongreen which consists of combining both horizontal and vertical synchronization pulses with the green signal thus eliminating the need for the Hsync and Vsync wires In this case the voltage range of G is made 03 V higher 03Vto1V so the downward pulses toward 0 V of Hsync and Vsync can be easily detected by the display controller which can also distinguish Hsync from Vsync because the latter is much longer 156 Pixel Signals In the last section we described the control signals which are applicationindependent fixed In this section we discuss the pixel signals which vary with the application Figure 157a shows additional details regarding the DACs pixel signals Thanks to the AND gates R G and B are turned OFF when dena ¼ 0 Note that pixelclk is needed to control the data sequence that is applied to the triple DAC Finally observe the presence of two new control signals called nblank and nsync which are specifically for the DACs An example of DAC for video applications is shown in figure 157b which is the ADV7123 chip from Analog Devices containing a triple 10bit converter The R and B DACs provide output voltages in the 0Vto07V range while the G DAC includes also a 03 V higher 03Vto1V range needed when syncongreen is used Since the DACs drive dual 75 W loads the output currents from R and B must be in the 0mAto187mA range because 07V75W75W ¼ 187 mA The additional current source for G which can be turned ON and OFF by nsync is 8 mA because 03V75W75W ¼ 8 mA The purpose of nsync is to cause G to operate in the regular when low or composite sync when high range The purpose of nblank is to blank the screen when low by Figure 156 Examples of VGA modes and corresponding vertical timing parameters VHDL Design of VGA Video Interfaces 429 Figure 157 a Details regarding the DACs b ADV7123 triple DAC Figure 158 a Circuit diagram showing the indispensable VGA signals b Horizontal and vertical sync signals for the basic 480 640 VGA mode redswitch ¼ 0 no red R ¼ 0000000000 0V redswitch ¼ 1 maximum red intensity R ¼ 1111111111 07V greenswitch ¼ 0 no green G ¼ 0000000000 0V greenswitch ¼ 1 maximum green intensity G ¼ 1111111111 07V blueswitch ¼ 0 no blue B ¼ 0000000000 0V blueswitch ¼ 1 maximum blue intensity B ¼ 1111111111 07V A 50 MHz clock and a triple 10bit DAC as in Alteras DE2 board will be used The DACs control signals nblank and nsync must be kept at 1 and 0 respectively A VHDL code for this VGA interface is presented below The control signal parameters of figure 158b were entered using GENERIC declarations lines 714 so the code can be easily adjusted to other VGA modes The signal names lines 1621 are from figure 158a Note that because only two Hsync Vsync of the five control signals are transmitted to the monitor figure 158a the other three were declared internally line 25 The code proper lines 26116 was separated into two parts Part 1 lines 3077 imple ments the control generator figure 158a Note that the code for each signal obeys the tim ing diagrams of figure 158b Part 2 of the code lines 81115 implements the image generator In lines 8591 a counter is used to construct a pointer called linecounter to the image rows If it points to row 1 lines 9396 the color is red If it points to rows 23 lines 97100 the color is green When pointing to rows 46 lines 101104 it is blue Finally when pointing to rows 7480 lines 105108 the color is determined by the three toggle switches In lines 110113 dena ¼ 0 is used to turn the image OFF during retrace This design could obviously have been done using a structural approach with each of these parts implemented using the COMPONENT construct such an approach will be illustrated in the next chapter The reader is invited to compile the code below and ob serve what happens on the VGA display while playing with the RGB switches 1 2 LIBRARY ieee 3 USE ieeestdlogic1164all 4 5 ENTITY vga IS 6 GENERIC 7 Ha INTEGER 96 Hpulse 8 Hb INTEGER 144 HpulseHBP 9 Hc INTEGER 784 HpulseHBPHactive 10 Hd INTEGER 800 HpulseHBPHactiveHFP 11 Va INTEGER 2 Vpulse 12 Vb INTEGER 35 VpulseVBP 13 Vc INTEGER 515 VpulseVBPVactive 432 Chapter 15 14 Vd INTEGER 525 VpulseVBPVactiveVFP 15 PORT 16 clk IN STDLOGIC 50MHz in our board 17 redswitch greenswitch blueswitch IN STDLOGIC 18 pixelclk BUFFER STDLOGIC 19 Hsync Vsync BUFFER STDLOGIC 20 R G B OUT STDLOGICVECTOR9 DOWNTO 0 21 nblanck nsync OUT STDLOGIC 22 END vga 23 24 ARCHITECTURE vga OF vga IS 25 SIGNAL Hactive Vactive dena STDLOGIC 26 BEGIN 27 28 Part 1 CONTROL GENERATOR 29 30 Static signals for DACs 31 nblanck 1 no direct blanking 32 nsync 0 no sync on green 33 Create pixel clock 50MHz25MHz 34 PROCESS clk 35 BEGIN 36 IF clkEVENT AND clk1 THEN 37 pixelclk NOT pixelclk 38 END IF 39 END PROCESS 40 Horizontal signals generation 41 PROCESS pixelclk 42 VARIABLE Hcount INTEGER RANGE 0 TO Hd 43 BEGIN 44 IF pixelclkEVENT AND pixelclk1 THEN 45 Hcount Hcount 1 46 IF HcountHa THEN 47 Hsync 1 48 ELSIF HcountHb THEN 49 Hactive 1 50 ELSIF HcountHc THEN 51 Hactive 0 52 ELSIF HcountHd THEN 53 Hsync 0 54 Hcount 0 55 END IF 56 END IF VHDL Design of VGA Video Interfaces 433 57 END PROCESS 58 Vertical signals generation 59 PROCESS Hsync 60 VARIABLE Vcount INTEGER RANGE 0 TO Vd 61 BEGIN 62 IF HsyncEVENT AND Hsync0 THEN 63 Vcount Vcount 1 64 IF VcountVa THEN 65 Vsync 1 66 ELSIF VcountVb THEN 67 Vactive 1 68 ELSIF VcountVc THEN 69 Vactive 0 70 ELSIF VcountVd THEN 71 Vsync 0 72 Vcount 0 73 END IF 74 END IF 75 END PROCESS 76 Display enable generation 77 dena Hactive AND Vactive 78 79 Part 2 IMAGE GENERATOR 80 81 PROCESS Hsync Vsync Vactive dena redswitch 82 greenswitch blueswitch 83 VARIABLE linecounter INTEGER RANGE 0 TO Vc 84 BEGIN 85 IF Vsync0 THEN 86 linecounter 0 87 ELSIF HsyncEVENT AND Hsync1 THEN 88 IF Vactive1 THEN 89 linecounter linecounter 1 90 END IF 91 END IF 92 IF dena1 THEN 93 IF linecounter1 THEN 94 R OTHERS 1 95 G OTHERS 0 96 B OTHERS 0 97 ELSIF linecounter1 AND linecounter3 THEN 98 R OTHERS 0 99 G OTHERS 1 434 Chapter 15 100 B OTHERS 0 101 ELSIF linecounter3 AND linecounter6 THEN 102 R OTHERS 0 103 G OTHERS 0 104 B OTHERS 1 105 ELSE 106 R OTHERS redswitch 107 G OTHERS greenswitch 108 B OTHERS blueswitch 109 END IF 110 ELSE 111 R OTHERS 0 112 G OTHERS 0 113 B OTHERS 0 114 END IF 115 END PROCESS 116 END vga 117 1510 Image Generation with a File and OnChip Memory In chapter 13 we saw several ways of implementing ROM and RAM memory It was also described how data from a file can be loaded into such memories The purpose of the de sign presented here is to show how an image can be read from a file and loaded into a ROM or RAM memory and from there be sent to a VGA display A simple image will again be used which eases the comparison between the actual and the expected result Figure 159 shows the image to be produced in this design along with the corresponding data file of type MIFsee chapter 13 The 480 lines are broken into eight 60line Figure 159 Image to be produced in the design of section 1510 and corresponding MIF file VHDL Design of VGA Video Interfaces 435 portions shown on the left and the 10bit intensity with 10bit DACs is broken into eight linearly spaced values shown in the center Toggle switches will again be employed for R G and B A VHDL code for this circuit is presented below In the library declarations lines 26 note the inclusion of the packages stdlogicarith which contains the function convstdlogicvector used in line 60 and lpmcomponents which specifies the lpmrom cell used in lines 4048 The control signal parameters of figure 158b were entered using GENERIC declara tions lines 1017 so the code can be easily adjusted to other VGA modes The signal names lines 1924 are from figure 158a Because only two Hsync Vsync of the five control signals are transmitted to the monitor figure 158a the other three were declared internally line 28 Two other internal signals were declared in lines 2930 to deal with the ROM The code proper lines 3166 was broken into two parts with part 1 implementing the control generator and part 2 implementing the image generator Because the former is ex actly the same as that in the previous design it was omitted in the code below The image generator lines 3966 is divided into three subsections The first subsection implements the ROM lines 4048 The second lines 5061 builds a pointer called linecounter that is used in line 48 as an address to retrieve data from the ROM which is assigned to the signal intensity Finally in the third subsection lines 6365 intensity is assigned or not to the system colors ðR G BÞ depending on the positions of the toggle switches As in the previous design a structural code could have been used with the control gen erator in one code and the image generator in another both then instantiated in the main code by means of the COMPONENT construct 1 2 LIBRARY ieee 3 USE ieeestdlogic1164all 4 USE ieeestdlogicarithall 5 LIBRARY lpm 6 USE lpmlpmcomponentsall 7 8 ENTITY vga IS 9 GENERIC 10 Ha INTEGER 96 Hpulse 11 Hb INTEGER 144 HpulseHBP 12 Hc INTEGER 784 HpulseHBPHactive 13 Hd INTEGER 800 HpulseHBPHactiveHFP 14 Va INTEGER 2 Vpulse 15 Vb INTEGER 35 VpulseVBP 436 Chapter 15 16 Vc INTEGER 515 VpulseVBPVactive 17 Vd INTEGER 525 VpulseVBPVactiveVFP 18 PORT 19 clk IN STDLOGIC 50MHz in our board 20 redswitch greenswitch blueswitch IN STDLOGIC 21 pixelclk BUFFER STDLOGIC 22 Hsync Vsync BUFFER STDLOGIC 23 R G B OUT STDLOGICVECTOR9 DOWNTO 0 24 nblanck nsync OUT STDLOGIC 25 END vga 26 27 ARCHITECTURE vga OF vga1 IS 28 SIGNAL Hactive Vactive dena STDLOGIC 29 SIGNAL address STDLOGICVECTOR8 DOWNTO 0 30 SIGNAL intensity STDLOGICVECTOR9 DOWNTO 0 31 BEGIN 32 33 Part 1 CONTROL GENERATOR 34 35 same as in previous design 36 37 Part 2 IMAGE GENERATOR 38 39 ROM instantiation 40 myrom lpmrom 41 GENERIC MAP 42 lpmwidthad 9 address width 43 lpmoutdata UNREGISTERED 44 lpmaddresscontrol REGISTERED 45 lpmfile stripesmif data file 46 lpmwidth 10 data width 47 PORT MAP 48 inclockNOT pixelclk addressaddress qintensity 49 Create address row number 50 PROCESS Vsync Hsync 51 VARIABLE linecounter INTEGER RANGE 0 TO Vd 52 BEGIN 53 IF Vsync0 THEN 54 linecounter 0 55 ELSIF HsyncEVENT AND Hsync1 THEN 56 IF Vactive1 THEN 57 linecounter linecounter 1 58 END IF VHDL Design of VGA Video Interfaces 437 Figure 1510 a Setup for the design of section 1511 data read from an external memory b Memoryread timing time 10 ns Since our circuit will operate in the basic VGA mode 640 480 60Hz its clock is 25 MHz Given that each memory address contains two pixels the memoryread operation only needs to be executed once every two pixel clock cyclesthat is at 125 MHz well under the maximum speed of this memory Note in the code that the five memorycontrol signals nWE write enable active low nCE chip enable active low nOE output enable active low nLB lower byte enable active low and nUB upper byte enable active low are all held at fixed values line 39 proper for memoryreading only The architecture lines 2675 contains again two parts control generator and image generator The former is exactly the same as that in the previous designs so it was omitted The latter is in lines 3875 and was further divided into three subsections The first of them assigns the static values to the five memorycontrol pins mentioned above line 39 The second subsection lines 4155 reads the memory and stores the result 16 bits 2 pixels locally Finally the third subsection lines 5774 assigns such bits to the R G and B signals 1 2 LIBRARY ieee 3 USE ieeestdlogic1164all 4 5 ENTITY vga IS 6 GENERIC 7 Ha INTEGER 96 Hpulse 8 Hb INTEGER 144 HpulseHBP 9 Hc INTEGER 784 HpulseHBPHactive 10 Hd INTEGER 800 HpulseHBPHactiveHFP 11 Va INTEGER 2 Vpulse 12 Vb INTEGER 35 VpulseVBP 13 Vc INTEGER 515 VpulseVBPVactive 14 Vd INTEGER 525 VpulseVBPVactiveVFP 15 PORT 16 clk IN STDLOGIC 50MHz 17 pixelclk BUFFER STDLOGIC 25MHz 18 Hsync Vsync BUFFER STDLOGIC control 19 R G B OUT STDLOGICVECTOR9 DOWNTO 0 to DACs 20 nblanck nsync OUT STDLOGIC to DACs 21 nWE nCE nOE nLB nUB OUT STDLOGIC to SRAM 22 address OUT INTEGER RANGE 0 TO 262143 to SRAM 23 data IN STDLOGICVECTOR15 DOWNTO 0 from SRAM 24 END vga 25 26 ARCHITECTURE vga OF vga IS 27 SIGNAL Hactive Vactive dena STDLOGIC 28 SIGNAL registereddata STDLOGICVECTOR15 DOWNTO 0 29 SIGNAL flag STDLOGIC 30 BEGIN 31 32 Part 1 CONTROL GENERATOR 33 34 same as in previous design 35 36 Part 2 IMAGE GENERATOR 37 38 Static signals for SRAM 39 nWE1 nCE0 nOE0 nLB0 nUB0 40 Read SRAM and register its data 41 PROCESS pixelclk Vsync 42 VARIABLE pixelcounter INTEGER RANGE 0 TO 262143 43 BEGIN 44 IF Vsync0 THEN 45 pixelcounter 0 46 flag 0 47 ELSIF pixelclkEVENT AND pixelclk1 THEN 48 IF dena1 AND flag1 THEN 49 registereddata data 50 pixelcounter pixelcounter 1 51 END IF 52 flag NOT flag 53 END IF 54 address pixelcounter 55 END PROCESS 56 Create image 57 PROCESS dena flag registereddata 58 BEGIN 59 IF dena1 THEN 60 IF flag1 THEN 61 R registereddata15 DOWNTO 8 00 62 G registereddata15 DOWNTO 8 00 63 B registereddata15 DOWNTO 8 00 64 ELSE 65 R registereddata7 DOWNTO 0 00 66 G registereddata7 DOWNTO 0 00 67 B registereddata7 DOWNTO 0 00 68 END IF 69 ELSE 440 Chapter 15 70 R OTHERS 0 71 G OTHERS 0 72 B OTHERS 0 73 END IF 74 END PROCESS 75 END vga 76 1512 Image Equalization with Gamma Expansion CRT monitors introduce a nonlinear luminance distortion known as gamma compression because it compresses the input values x according to the function xg where 0 a x a 1 and gA22 Consequently for a linear reproduction the inputs must be gamma ex panded that is x1g must be entered instead of x as in the NTSC television system To illustrate this phenomenon we can display the same image of section 1510 now with gamma expanded values at the input see figure 1511 Note that because the image is stored in an external memory initialization file nothing in the code of section 1510 needs to be changed The reader is invited to compile the code with this new MIF file and compare the resulting image on a VGA monitor against that produced in section 1510 1513 Exercises Note For exercise solutions please consult the book website Exercise 151 800 D 600 D 75Hz SVGA Interface a Say that our monitor supports other modes besides the default VGA mode What needs to be done for it to change from one mode to the other Figure 1511 Gamma expanded input values for approximately linear image reproduction VHDL Design of VGA Video Interfaces 441 Figure 1512 b Say that we want it to operate in the 800 600 75Hz mode Draw the corresponding horizontal and vertical timing diagrams as in figure 158b c Modify the code in section 159 in order to display the same image but operating in the 75 Hz SVGA mode Exercise 152 Image Generation with Hardware 1 Banner Design a circuit capable of producing the image of figure 1512a on a VGA monitor The color on the left half must be determined by three toggle switches for R G B with the complementary color R G B automatically assigned to the right half of the banner The figure must be generated by local hardware FPGA cells as in section 159 Exercise 153 Image Generation with Hardware 2 Sun in the Sky Design a circuit capable of producing the image of figure 1512b on a VGA monitor The color outside the circle must be determined by three toggle switches for R G B The figure must be generated by local hardware FPGA cells as in section 159 Exercise 154 Image Generation with Hardware 3 Filling with Green Design a circuit capable of producing the image of figure 1512c on a VGA monitor which must be generated by local hardware FPGA cells as in section 159 It consists of filling the screen with green from top to bottom with the base color determined by three toggle switches for R G and B When the filling is completed the base color should start filling the screen also from top to bottom until green starts filling it again and so on The speed of the filling should be one line per frame with 60 framessecond a total of 48060 8 seconds will be needed to fill one screen Exercise 155 Image Generation with Hardware 4 Rotating Bar Design a circuit capable of producing the image of figure 1512d on a VGA monitor which must be generated by local hardware FPGA cells as in section 159 Each bar must be 100 pixels wide As soon as the green bar reaches the bottom of the screen it must start reentering at the top the same occurring with the red bar in the horizontal direction The speed of the green bar must be one line per frame with 60 framessecond 8 seconds will be needed for a full bar rotation Choose for the red bar a speed such that it takes the same time as the green bar to cover one screen Exercise 156 Image Generation with Hardware 5 Digital Clock Design a circuit that implements the clock of figure 1513 on a VGA monitor The positions of the digits on the screen for the monitor operating in the basic 640 480 VGA mode are given in the figure The image must be generated by local hardware FPGA cells as in section 159 Hint See a related design in chapter 17 Exercise 157 Image Generation with Hardware 6 Arcade Game Design a circuit capable of generating the elementary game illustrated in figure 1514 The player must be able to move the racket horizontally using two pushbuttons If a clear ball is collected by the racket the player wins a point otherwise if the ball reaches the bottom of the screen the computer gets a point A few black balls also fall along with clear balls which must be avoided by the player The game ends when a certain score is reached or a black ball hits the racket The score must be kept on the screen upper left and right corners The speed of the balls four levels of difficulty must be set by two toggle switches The image must be generated by local hardware FPGA cells as in section 159 Exercise 158 Image Generation with a File and OnChip Memory C1 Banner Following the procedure in section 1510 design a circuit capable of generating the image of figure 1512a The image must first be prepared in a standard text file MIF for exam ple from which it should be read and transferred to the FPGA SRAM memory then finally displayed on the monitor The file should contain only 0s for the left half of the banner and 1s for the right half When reading this file 0 should be interpreted as green and 1 as red It is left to the reader to find a way of preparing the text file with Excel for example among several other possibilities Exercise 159 Image Generation with a File and OnChip Memory C2 Sun in the Sky Develop a design similar to that in exercise 158 for the image of figure 1512b Exercise 1510 Image Generation with a File and OChip Memory Arbitrary Picture Find a picture that you consider interesting Following the procedure in section 1511 design a circuit capable of displaying that picture on a VGA monitor 444 Chapter 15