Manual do Instrutor Sistemas Digitais - Tocci 10ed - Soluções

Instructors Resource Manual to accompany DIGITAL SYSTEMS Principles and Applications Tenth Edition Ronald J Tocci Neal S Widmer Gregory L Moss Prepared by Frank J Ambrosio Monroe Community College Upper Saddle River New Jersey Columbus Ohio Copyright 2007 by Pearson Education Inc Upper Saddle River New Jersey 07458 Pearson Prentice Hall All rights reserved Printed in the United States of America This publication is protected by Copyright and permission should be obtained from the publisher prior to any prohibited reproduction storage in a retrieval system or transmission in any form or by any means electronic mechanical photocopying recording or likewise For information regarding permissions write to Rights and Permissions Department Pearson Prentice Hall is a trademark of Pearson Education Inc Pearson is a registered trademark of Pearson plc Prentice Hall is a registered trademark of Pearson Education Inc Instructors of classes using Tocci Widmer and Moss Digital Systems Principles and Applications 10th Edition may reproduce material from the instructors manual for classroom use 10 9 8 7 6 5 4 3 2 1 ISBN 013172665X TABLE OF CONTENTS SOLUTIONS TO RONALD J TOCCINEAL S WIDMERGREGORY L MOSS DIGITAL SYSTEMS PRINCIPLES AND APPLICATIONS TENTH EDITION CHAPTER 1 Introductory Concepts 1 CHAPTER 2 Number Systems and Codes 3 CHAPTER 3 Describing Logic Circuits 9 CHAPTER 4 Combinational Logic Circuits 29 CHAPTER 5 FlipFlops and Related Devices 54 CHAPTER 6 Digital Arithmetic Operations and Circuits 80 CHAPTER 7 Counters and Registers 98 CHAPTER 8 IntegratedCircuit Logic Families 147 CHAPTER 9 MSI Logic Circuits 156 CHAPTER 10 Digital System Projects Using HDL 178 CHAPTER 11 Interfacing with the Analog World 189 CHAPTER 12 Memory Devices 198 CHAPTER 13 Programmable Logic Device Architectures 209 Instructors Resource Manual 10th edition CHAPTER ONE Introductory Concepts 11 a e are digital b c d are analog 12 a Analog b Analog c Digital d Digital e Analog 13 a 110012 1681 2510 b 100110012 810500625 9562510 c 10011011001101102 102412864168105012500625 1241687510 14 a 100112 1621 1910 b 110001012 8402500625 12312510 c 10011100100100102 1252562510 15 0002 0012 0102 0112 1002 1012 1102 1112 17 2N 1 210 1 1023 18 2N 1 214 1 16383 19 28 256 and 29 512 therefore 9 bits are needed 110 2N 1 63 therefore 6 bits are needed 111 three interval timing pulse image 112 voltage over time graph from 0 to 14 ms voltage levels at 03V 39V Instructors Resource Manual 10th edition 113 a 2N 1 15 N 4 Therefore 4 lines are required for parallel transmission b Only 1 line is required for serial transmission 114 A microprocessor is a CPU on a chip The CPU contains the control unit and the arithmetic logic unit ALU A microcomputer generally consists of several IC chips including a microprocessor chip memory chips and inputoutput interface chips along with inputoutput devices 115 A microcontroller is a specialized type of microcomputer that is designed to be used as a dedicated or embedded controller Microcontrollers are generally much smaller than generalpurpose microcomputers CHAPTER TWO Number Systems and Codes 21 a 101102 1642 2210 b 100101012 1281641 14910 c 1001000010012 204825681 231310 d 011010112 6432821 10710 e 111111112 1286432168421 25510 f 011011112 64328421 11110 g 11110101112 5122561286416421 98310 h 110111112 12864168421 22310 22 a 3710 3241 1001012 b 1310 841 11012 c 18910 1283216841 101111012 d 1000010 51225612864328 11111010002 e 7710 64841 10011012 f 39010 25612842 1100001102 g 20510 12864841 110011012 h 213310 2048641641 1000010101012 i 51110 2561286432168421 1111111112 23 281 25510 2161 6553510 24 a 74316 7x1624x1613x160 185910 b 3616 3x1616x160 5410 c 37FD16 3x1637x16215x16113x160 1433310 d 200016 2x163 819210 e 16516 1x1626x1615x160 35710 f ABCD16 10x16311x16212x16113x160 4398110 g 7FF16 7x16215x16115x160 204710 h 120416 1x1632x1624x160 461210 25 a 5916 3 Remainder of 11 316 0 Remainder of 3 5910 3B16 b 37216 23 Remainder of 4 2316 1 Remainder of 7 116 0 Remainder of 1 37210 17416 c 91916 57 Remainder of 7 5716 3 Remainder of 9 316 0 Remainder of 3 91910 39716 d 102416 64 Remainder of 0 6416 4 Remainder of 0 416 0 Remainder of 4 102410 40016 e 77116 48 Remainder of 3 4816 3 Remainder of 0 316 0 Remainder of 3 77110 30316 f 231316 144 Remainder of 9 14416 9 Remainder of 0 916 0 Remainder of 9 231310 90916 g 6553616 4096 Remainder of 0 409616 256 Remainder of 0 25616 16 Remainder of 0 1616 1 Remainder of 0 116 0 Remainder of 1 6553610 1000016 h 25516 15 Remainder of 15 1516 0 Remainder of 15 25510 FF16 26 a 74316 111010000112 b 3616 1101102 c 37FD16 110111111111012 d 200016 100000000000002 e 16516 10110010102 f ABCD16 10101011110011012 g 7FF16 011111111112 h 120416 10010000001002 27 a 1011021616 b 1001010129516 c 100100001001290916 d 0110101126B16 e 111111112FF16 f 0110111126F16 g 111101011123D716 h 110111112DF16 28 195 196 197 198 199 19A 19B 19C 19D 19E 19F 2A0 2A1 2A2 2A9 2AA 2AB 2AC 2AD 2AE 2AF 2B0 29 213316 133 Remainder of 5 13316 8 Remainder of 5 816 0 Remainder of 8 213310855161000010101012 210 16N 20000 Therefore n4 211 a 9216 9x1612x160 14610 b 1A616 1x16210x1616x160 42210 c 37FD16 3x1637x16215x16113x160 1433310 d ABCD16 10x16311x16212x16113x160 4398110 e 000F16 0x1630x1620x16115x160 1510 f 5516 5x1615x160 8510 g 2C016 2x16212x1610 70410 h 7FF16 7x16215x16115x160 204710 212 a 7516 4 Remainder of 11 B 416 0 Remainder of 4 75104B16 b 31416 19 Remainder of 10 A 1916 1 Remainder of 3 116 0 Remainder of 1 3141013A16 c 204816 128 Remainder of 0 12816 8 Remainder of 0 816 0 Remainder of 8 20481080016 d 2416 1 Remainder of 8 116 0 Remainder of 1 24101816 e 724516 452 Remainder of 13 D 45216 28 Remainder of 4 2816 1 Remainder of 12 C 116 0 Remainder of 1 7245101C4D16 f 49816 31 Remainder of 2 3116 1 Remainder of 15 F 116 0 Remainder of 1 498101F216 g 2561916 1601 Remainder of 3 160116 100 Remainder of 1 10016 6 Remainder of 4 616 0 Remainder of 6 2561910641316 h 409516 255 Remainder of 15 F 25516 15 Remainder of 15 F 1516 0 Remainder of 15 F 409510FFF16 213 a 9 b D c 8 d 0 e F f 2 g A h 9 I B j C k 3 l 4 m 1 n 5 o 7 p 6 214 a 0110 b 0111 c 0101 d 0001 e 0100 f 0011 g 1100 h 1011 i 1001 j 1010 k 0010 l 1111 m 0000 n 1000 o 1101 p 1001 215 a 0001011021616 b 1001010129516 c 100100001001290916 d 0110101126B16 e 111111112FF16 f 0110111126F16 g 00111101011123D716 h 110111112DF16 216 a 9216100100102 b 1A6160001101001102 c 37FD1600110111111111012 d ABCD1610101011110011012 e 000F1611112 f 5516010101012 d 2C01600101100000002 e 7FF1601111111111112 217 28016 28116 28216 28816 28916 28A16 28B16 28C16 28D16 28E16 28F16 29016 29116 29816 29916 29A16 29B16 29C16 29D16 29E16 29F16 2A016 218 With four hex digits we can represent a decimal number up to FFFF16 1641 6553510 With five hex digits we can represent a decimal number up to FFFFF16 1651 104857510 Therefore we need five hex digits to represent decimal numbers up to 1 million 219 a 47100100 0111BCD b 962101001 0110 0010BCD c 187100001 1000 0111BCD d 6727100110 0111 0010 0111BCD e 13100001 0011BCD f 529100101 0010 1001BCD g 89627101000 1001 0110 0010 0111BCD h 1024100001 0000 0010 0100BCD 220 a 2N1999 Therefore N10 Hence it requires 10 bits for straight binary b 99910 requires 12 bits for BCD 4 bits per digit 221 a 1001 0111 0101 0010BCD 975210 b 0001 1000 0100BCD 18410 c 0110 1001 0101BCD 69510 d 0111 0111 0111 0101BCD 777510 e 0100 1001 0010BCD 49210 f 0101 0101 0101BCD 55510 222 a 1 byte 8 bits Thus 8 bytes 64 bits b 4 bytes 32 bits A hex digit requires four bits to be represented Thus the largest hex number that can be represented in four bytes is FFFFFFFF16 c The largest BCDencoded decimal value that can be represented in three bytes is 999999 223 a 0101 b 4 nibbles c 3 bytes 224 x 3y Hex Bin With oddparity x 78 111 1000 1111 1000 F8 space 20 010 0000 0010 0000 20 3D 011 1101 0011 1101 3D space 20 010 0000 0010 0000 20 3 3 011 0011 1011 0011 B3 2A 010 1010 0010 1010 2A y 79 111 1001 0111 1001 79 1111 1000 0010 0000 0011 1101 0010 0000 1011 0011 0010 1010 0111 1001 x space space 3 y 225 x 3y Hex Bin With evenparity x 78 111 1000 0111 1000 78 space 20 010 0000 1010 0000 A0 3D 011 1101 1011 1101 BD space 20 010 0000 1010 0000 A0 3 3 011 0011 0011 0011 33 2A 010 1010 1010 1010 AA y 79 111 1001 1111 1001 F9 1111 1000 0010 0000 0011 1101 0010 0000 1011 0011 0010 1010 0111 1001 x space space 3 y 226 a 42B 45E 4EN 20blank 53S 4DM 49I 54T 48H Thus the name of the person is BEN SMITH b 4AJ 6Fo 65e 20blank 47G 72r 65e 65e 6En Thus the name of the person is Joe Green 227 a 7410 01110100BCD 101110100 b 3810 00111000BCD 000111000 c 888410 10001000010000100BCD 11000100010000100 d 27510 001001110101BCD 0001001110101 e 16510 000101100101BCD 0000101100101 f 920110 1001001000000001BCD 1100100100000001 228 a 1001 0101 1000 0 parity bit 9 5 8 Since the number of 1s is 5 there is no singlebit error b 0100 0111 0110 0 4 7 6 Since there are six 1s there is a single error c 0111 1100 0001 1 7 12 1 There are seven 1s However the second BCD code group has an error since 1100 is an illegal BCD code Thus there must be a double error because there are an odd number of 1s d 1000 0110 0010 1 8 6 2 There are five 1s Thus no singlebit errors 229 01001000 OK 11000101 OK 11001100 OK 11001000 There is a single error 11001100 Error cant be detected by the receiver 230 a 101100010012 b 111111112 c 20910 d 5994310 e 9C116 f 010100010001BCD g 56510 h 10DC16 i 196110 j 1590010 k 64016 l 952B16 m 100001100101BCD n 94710 o 100011001012 p 1011001101002 q Convert to decimal then to binary to obtain 10010102 r Convert to decimal then to BCD to obtain 01011000BCD 231 a 1001012 b 00110111BCD c 2516 d 011001101101111ASCII 232 a Hex b Two c digit d Gray code e parity biterrors f ASCII g Hex h Byte 233 a 10002 b 0101002 c 11002 234 a 10112 b 1001112 c 11012 235 a 777A16 b 999A16 c 100016 d 200116 e A0016 f 100B16 236 a 777816 b 999816 c 0FFE16 d 1FFF16 e 9FE16 f 100916 237 a A 20bit address will allow 1048576 220 different memory locations to exist b Since a hex digit requires 4 bits to represent it will take 5 hex digits to represent the 20bit address of a memory location c 000FF16 238 a 2664 different voltage values 28256 different voltage values 2101024 different voltage values b In 1s there are about 44000 samples of 10bits each recorded on the CD surface Thus there are about 440000 bits recorded on the CD disk during 1s of sampling c There are about 440000 bits recorded on the CD disk in 1 second of audio Therefore 5 billion bits of audio stored on the CD disk will be equivalent to approximately 1136363 seconds 5x109440000 239 2542x Therefore x7988bits 240 Mega 220 1048576 3 Bytespixel 1 byte per primary color 3 Bytespixel x 3 x 1048576 9437184 Bytesphoto Memory card capacity 128 x 1048576 134217728 Bytescard Thus 134217728 Bytescard 9437184 Bytesphoto 142 photoscard or 14 Pictures CHAPTER THREE Describing Logic Circuits 31 Waveforms for A B C X 32 Waveforms for A B C X 33 With A1 X will always be 1 since the OR gate output is 1 whenever any input is a 1 34 a Heres one case that refutes this statement Waveforms for A B X b Heres one case that refutes this statement Waveforms for A B X 35 There are 25 32 different input conditions Only one of these the 00000 condition produces a LOW output 36 a Waveforms for A B C X b X constant LOW c Waveforms for A D C X 37 Change the OR gate to an AND gate 38 OUT is always LOW since one or more inputs is always LOW 39 A logic HIGH and a logic LOW applied to the inputs of the unknown 2input gate would tell us what type of gate it is If the resulting output logic level is HIGH then the gate is an OR gate If the resulting output logic level is LOW then the gate is an AND gate 310 True The output of any AND gate will be HIGH only when all of its inputs are HIGH 311 a Waveforms for A A complement b Waveforms for B B complement 312 a X A B BC Truth Table A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 b X A B C A B C A B D Truth Table A B C D X 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 b Z A B CD E BC D c Y M N P Q d X w P Q e Z MNP Q E D C B A AB AB C AB C DAB C DAB C E 1 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 315 A B C D A BC A D A D A DABC 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 0 0 313 E D C B A A B A BC A B C D A B C D A B CE 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 314 E D C B A AB ABC ABC DABC DABC E 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 f X ADAB 317 a OUT 1 only when all inputs are 0 b With C0 c With C1 OUT 0 at all times 318 a OUT 0 only when all inputs are 1 b With C0 OUT 1 at all times c With C1 319 X ABBC X AB B C A B C X 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 1 A B C X 320 ABCDX 00001 00011 00101 00111 01001 01011 01101 01111 10001 10011 10101 10111 11000 11011 11101 11111 321 a b c 322 Proving theorem 15a X XY X Y X1 1011 X0 01000 Y1 101 Y0 000 11 00 X1 10010 X0 01101 Y0 101 Y1 011 11 11 Proving theorem 15b X XY X Y X1 0111 X0 10010 Y1 011 Y0 101 11 11 X1 01000 X0 10110 Y0 000 Y1 101 00 11 By canceling double INVERTERS the result is X A B C A B C A B D g AB CD A B C D A B C D h M NM N MN MN i ABCD ABC D A BC D 327 X A BBC A B BC A B B C A B C 328 Change each inverter to Change each AND to Change each OR to 323 a A 1 1 b A A A c B B 0 d C C C e X 0 0 f D 1 D g D 0 D h C C 1 i G GF G j Y WY Y 324 a X M NM PN P X MM MP NM NPN P X MMN MMP MPN MPP NMN NMP NPN NPP X 0 0 MPN 0 0 NMP 0 0 X MPN NMP b Z ABC ABC BCD Z BCA A D Z BC1 D Z BC 325 A B A B A1 B1 1 1 1 1 A0 B1 0 1 0 1 0 A0 B0 0 0 0 1 A1 B0 1 0 1 0 0 A B A B A1 B1 1 1 1 1 0 A0 B1 0 1 0 1 1 A0 B0 0 0 0 1 A1 B0 1 0 1 0 1 326 a ABC A B C A B C b A BC AB C AB C c ABCD AB CD A B CD d A B AB AB e AB A B A B f A C D ACD ACD 329 XABC 330 331 332 a The warning light W will be activated when temperature T is 200F and either the pressure P is 220 psi or the speed R is 4800 rpm In conclusion W1 when T1 and either P1 or R0 b 333 a NOR gate b AND gate c NAND gate 334 335 a b 336 a Z is HIGH only when AB0 and CD1 b Z will be LOW when A or B is HIGH or when C or D is LOW 337 338 X will go HIGH when E1 or D0 or CB0 or when B1 and A0 339 a X is asserted active HIGH b Z is asserted active LOW E D C B A X 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 341 B A LIGHT 0 0 0 0 1 1 1 0 1 342 a b 343 a FALSE b TRUE c FALSE d TRUE e FALSE f FALSE g TRUE h FALSE I TRUE j TRUE 344 Digital INPUTS A B C D E F G H LOGIC CIRCUITS Programmable Connections Matrix 345 AHDL SUBDESIGN prob345 abc INPUT define inputs to block x1yz OUTPUT define block output BEGIN x1 a b y a b z a b c END VHDL ENTITY prob345 IS PORT a b c IN bit define inputs to block x y z OUT bit define block output END prob345 ARCHITECTURE ckt OF prob345 IS BEGIN x a OR b logic descriptions y NOTa AND b z a OR b OR c END ckt Instructors Resource Manual 10th edition 346 a AHDL SUBDESIGN prob346 rd roma romb ram INPUT define inputs to block mem OUTPUT define block output BEGIN mem rd roma romb ram END a VHDL ENTITY prob346 IS PORTrd roma romb ram IN bit define inputs to block mem OUT bit define block output END prob346 ARCHITECTURE ckt OF prob346 IS BEGIN mem NOT rd AND NOT roma OR NOT romb OR NOT ram END ckt b AHDL SUBDESIGN prob346 rd roma romb ram INPUT define inputs to block mem OUTPUT define block output VARIABLE vwx1y NODE BEGIN x1 rd w roma romb v ram y w v mem x1 y END b VHDL ENTITY prob346 IS PORTrd roma romb ram IN bit define inputs to block mem OUT bit define block output END prob346 ARCHITECTURE ckt OF prob346 IS SIGNAL vwxy BIT BEGIN x NOT rd w NOT roma OR NOT romb v NOT ram y w OR v mem x AND y END ckt 27 Instructors Resource Manual 10th edition 347 348 349 NOTE All gates are CMOS 74HC30 74HC32 74HC02 DRIVE 74HC02 X XABC XABC YABCD 28 Instructors Resource Manual 10th edition CHAPTER FOUR Combinational Logic Circuits 41 a x ABC AC CAB A CA B b y Q RQ R QQ QR RQ RR QR RQ c w ABC ABC A ACB B A AC A A C d q RSTR S T q R S TRST q RRST SRST TRST q RST RST RST q RST e x ABC ABC ABC ABC ABC x ABC BCA A ABC C x ABC BC AB x BC BAC A BC BA C One possibility f z B CB C A B C z BB BC BC CC ABC z BC BC ABC z BC BC AC z BC BC A z BC BC AB g y C D ACD ABC ABCD ACD y CD ACD ABC ABCD ACD y CD CDA A ABC ABCD y CD CD ABC ABCD y DC C ABC ABCD y D ABC ABCD y D ABC ABC 29 h x ABCD ABD BCD x ABC D ABD BCD x ABC ABD ABD BCD 42 X MNQ MNQ MNQ X MNQ MNQ MNQ X MQ NQ X QN N 43 X M N Q M N Q M N Q X M N Q M N Q M N Q X MM MN MQ NM NN NQ QN QQT N Q X M MN MQ NM NQ QM ON Q T N Q X M Q M N Q X MM MN MQ MO ON QQ X MN Q Use X since this would give only three terms X ABC ABC ABC X BC ABC Alternate solution using SofP expression for X would be X AB BC BC 45 X ABC ABC ABC ABC By adding the term ABC three times and then factoring the following is obtained X ABC C ACB B BCA A X AB AC BC 46 Make the following assumptions A Its 500 or later B All machines are shut down C Its Friday D Production run for the day is complete Output Y assumes all variables that are not mentioned in the conditions of the story problem must be zero to blow the horn Output X assumes that all variables that are not mentioned in the conditions of the story problem can be either 1 or 0 in order to blow the horn X ABCD ABCD ABCD ABCD ABCD X AB BCD The same result can be obtained by writing the SofP expression and then simplifying it 48 Door D Ignition I Lights L 49 Change each gate to its NAND equivalent and then cancel double inversions 410 Change each gate to its NAND equivalent and then cancel double inversions Y ABCD ABCD By inspection X will be 1 whenever A30 A21 or when A3A20 while A1A01 Thus we can write X A3 A2 A3 A2 A1 A0 X A3 A2 A2 A1 A0 X A3 A2 A1 A0 411 a xACBCACD b xADBCBD c Make X1 to form a quad YBAC 412 YA 413 XBCBCAB Other solution XBCBCAC 414 a XABCABCABCABCABC XBCBCAB Other solution XBCBCAC YCDACDABCABCDACD YDABCABC c One possibility x ABC ABD ABD BCD For visual convenience let A3A A2B A1C A0D 416 a X BC AD b X BC AD ABC 417 X S1 S2 S1 S3 S3 S4 S2 S3 S2 S4 418 z ABD BC 419 In Example 43 of your textbook after the DeMorgan part is completed we have z ABC ACD ABCD ABC z ABC ACDB B ABCD ABC z ABC ABCD ABCD ABCD ABC z ABC ABCD ABCD ABCD ABC z BCA A AD ABDC C z BC ABD 420 a Output X will be HIGH only when A and B are at different levels b With B held LOW XA c With B held HIGH X A 421 X will be HIGH when AB BC and C1 Thus C1 B1 A0 is the only input condition that produces X1 422 a X ABC A B C C B A X b To find if ABC 1 X A B X is Low when AB 2 Y B C Y is Low when BC ABC when both 1 2 are true 423 424 425 One possibility is on the next page Note the use of the XNOR gates and AND gate 4 to determine when the two numbers are equal that is when X2Y2 X1Y1 and X0Y0 simultaneously AND gates 123 and the OR gate are used to sense when Y2 Y1 Y0 X2 X1 X0 The NOR gate simply uses the fact that if neither M nor P is HIGH then it must be true that X2 X1 X0 Y2 Y1 Y0 and therefore N1 426 Output Z3 Z3 1 only for single case in the TT Thus Z3 Y1 Y0 X1 X0 Output Z2 Z2 is HIGH for three cases Thus Z2 Y1Y0X1X0 Y1Y0X1X0 Y1Y0X1X0 Z2 Y1X1Y0 X0 Y1X1Y0X0 Output Z1 Z1 is HIGH for six cases Thus Z1 Y1Y0X1X0 Y1Y0X1X0 Y1Y0X1X0 Y1Y0X1X0 Y1Y0X1X0 Y1Y0X1X0 Z1 Y0X1Y1 X0 Y1X0Y0 X1 Output Z0 Z0 is HIGH for four cases Z0 Y1Y0X1X0 Y1Y0X1X0 Y1Y0X1X0 Y1Y0X1X0 Thus Z0 Y0X0 427 Instructors Resource Manual 10th edition Even Parity Checker a When all of the other inputs to the OR gate are in the LOW state the logic signal will pass through to its output unchanged b When all of the other inputs to the AND gate are in the HIGH state the logic signal will pass through to its output unchanged c When all of the other inputs to the NAND gate are in the HIGH state the logic signal will pass through to its output INVERTED d When all of the other inputs to the NOR gate are in the LOW state the logic signal will pass through to its output INVERTED a No A logic circuit must have two inputs in order to be used as an enabledisable circuit b No The control input of an XOR gate can be either HIGH or LOW If the control input is LOW the signal at the other input reaches the gates output unaffected If the control input is HIGH the signal at the other input reaches the gates output INVERTED Use an AND gate that is enabled when B0 C1 XA only if B0 C1 Use an OR gate since output is to be HIGH when inhibited XA only if BCD 1 X1 when BCD 1 44 Instructors Resource Manual 10th edition 428 429 430 Since there are only five cases when NS1 we will design for NS N S ABCD ABCD ABCD ABCD ABCD This can be simplified to N S CDA B ABC D Obviously E W N S 42 Instructors Resource Manual 10th edition 431 a Parity Generator To modify the circuit of figure 425 a to an Odd Parity Generator all that is needed is an inverter at the output Odd Parity Checker To modify the circuit of figure 425 b to an Odd Parity Checker the 2input exclusiveOR gates should be changed to 2input exclusiveNOR gates b Even Parity Generator Signals P and D0D7 go to the receiver 43 436 XA when BC X1 when BC 437 Z A0 S A1 S 438 No pairs no quads no octets Z X1 X0 Y1 Y0 X1 X0 Y1 Y0 X1 X0 Y1 Y0 X1 X0 Y1 Y 439 a 1 The output of the inverter is internally grounded 2 The output of the inverter is externally grounded 3 The input being driven by the output of the inverter is internally grounded b The output of the inverter is shorted to the output of another logic circuit 440 a Since Z14 is essentially floating the Logic Probe will show an indeterminate logic level b There will be 14V18V at the output Terminal Z29 will be floating HIGH in TTL since Z14 is opened internally Thus the signal at Z28 is the opposite of the signal at Z210 d 441 IC Z22 will be floating and therefore its voltage will fluctuate as it picks up noise Thus Z23 level will be unpredictable ICZ2 may also become overheated and eventually destroy itself 442 1 First isolate Z14 from Z21 by using one of the following methods a cutting the trace from Z14 to Z21 b clipping pin 4 of Z1 c clipping pin 1 of Z2 2 Check to see if Z14 is pulsing If it is then one can be sure that the inverter Z1 is working properly If its always LOW internally shorted to ground then inverter Z1 must be replaced 3 If step 2 above proves IC Z1 to be working properly then the problem must be with NAND gate Z2 internally shorted to ground By using a logic probe check the logic level at Z21 Chances are that it will have a permanent logic LOW which kept Z14 LOW and Z23 HIGH Replace Z2 443 1 Faulty IC bias Vcc andor Ground 2 Z22 is internally open floating 3 Z21 is internally open floating 4 Z23 is internally open floating Procedure With a VOM or logic probe check Vcc and Ground to the IC If the Vcc and Ground measurements are correct disconnect Z23 from any load it may be driving If problem persists replace Z2 444 Yes c e f a No This wouldve kept point X at a logic LOW permanently and the first case A1 B0 wouldnt have worked b No An open at Z213 has the same effect as a logic HIGH only in TTL Thus in the second case A0B1C1 Z211 wouldve been LOW and Z28 HIGH d No This wouldve cause IC Z2 to be unbiased and prevent the circuit from working properly for the first case g No This wouldve caused Z210 to be always LOW and Z28 HIGH for all cases 445 1 Make A0 Z11 B1 Z12 and C1 Z212 This is the case that causes the circuit to malfunction Note that the other three possible combinations of A and B do not cause a problem We know that IC Z1 is working from the results of the first case 2 The logic levels at Z213 and Z212 should be HIGH a Check to see if Z211 has a logic LOW b If Z211 is LOW and Z29 isnt turn off the power to the circuit c Use a VOM to make a continuity check between Z211 and Z29 If there is an open find it and restore the continuity between these two points 3 If after performing step two the technician finds that there is a good connection between Z211 and Z29 then one could conclude that either output Z211 or input Z29 is externally shorted to Vcc Since the circuit still has the power turned off from the last check the technician should make a continuity check to see if the trace between Z211 and Z29 is externally shorted to Vcc If there is a short to Vcc find it and eliminate it If no external short to Vcc is found then either Z211 or Z29 or both must be internally short to Vcc or have an internal open In any case the replacement of IC Z2 should be performed 446 This is a tough one You have noticed that Z26 and Z211 will be at the same logic level except for the two cases that dont work For those cases Z26 and Z211 are supposed to be different Since they measure indeterminate for those cases it is likely that Z26 and Z211 are shorted together probably by a solder bridge The short will have no effect for all those cases where these two outputs are at the same level 447 b If Z12 was internally shorted to ground whenever the passenger failed to fastened hisher seatbelt the circuit wouldve not detected this ALARM condition c Since this is a TTL logic circuit if there was an open connection between Z26 and Z210 the circuit wouldve operated as if a logic HIGH was present at Z210 This wouldve caused the circuit to ALWAYS assume that a passenger was in the seat with the respective seatbelt fastened Since the problem only manifests itself when an occupant is present in the car and the ignition is turned on it can be deduced that IC Z2 is working properly The problem must be with IC Z1 The following are the possible circuit failures a IC Z1 is not properly biased Most likely b IC Z1 is plugged in backwards problems Remote possibilities c Z14 and Z12 are internally shorted to Vcc d Z14 and Z12 are internally open e An open connection from Z12 to Z25 and from Z14 to Z22 f Connection from Z12 to Z25 is externally shorted to Vcc as well as the connection from Z14 to Z22 g Z11 and Z13 are internally shorted to Ground Procedure 1 Make the necessary voltage measurements to confirm proper IC Z1 bias Check for proper IC Z1 orientation 2 Check the logic levels at Z12 and Z14 with a logic probe If IC Z1 is working properly then a TTL logic LOW should be present at these points 3 If these logic levels are still HIGH by using an ohmmeter check for any external shorts to Vcc or open PC traces 4 Check the logic levels at Z11 and Z13 with a logic probe If IC Z1 is to work properly then a TTL logic HIGH should be present at these points 5 If these logic levels are LOW use an ohmmeter to check for any external shorts to Ground 6 If the above steps do not reveal a probable cause Z1 must be internally damaged and it must be replaced 449 For some reason Z213 is always HIGH The following are the possible circuit failures a Z213 is internally shorted to Vcc b Z28 is internally shorted to Vcc c Connection from Z28 to Z213 is open or externally shorted to Vcc d Z29 or Z210 are internally shorted to Ground e Z23 or Z26 are internally shorted to Ground f Connections from Z23 to Z29 or from Z26 to Z210 are externally shorted to Ground Procedure The first troubleshooting step is to make sure that all of the ICs are properly biased Vcc and Ground and oriented I Isolate Z213 from Z28 by cutting the trace on the PC board or by clipping the proper pin on IC Z2 either pin 8 or pin 13 Check the voltage level at Z213 with a VOM It should be about 0V since its floating at this point If the voltage is Vcc Z213 is either internally or externally shorted to Vcc and it should be replaced II If a fault is not found after performing step I then check the logic level at Z28 with a logic probe If its HIGH check the logic levels at Z29 and Z210 One of them or both should be LOW If they are both HIGH IC Z28 is internally or externally shorted to Vcc III If Z29 is LOW Check the logic levels at Z21 and Z22 They should be both LOW If they are LOW isolate Z23 from Z29 by cutting the trace on the PC board or by clipping the appropriate pin Z23 or Z29 Check the logic levels at Z23 and Z29 with a logic probe If either input is LOW one must conclude that IC Z2 pin 3 or pin 9 is externally or internally shorted to ground IV If Z210 is LOW the same test procedure should be used for the connection between Z210 and Z26 450 a True b True c False d False e True 451 All text between the characters serves as comments 452 Comments in a VHDL design file are indicated by 453 A special socket that allows you to drop the chip in and then clamp the contacts onto the pins 454 1 Boolean equation 2 Truth table 3 Schematic diagram 455 JEDEC Joint Electronic Device Engineering Council HDL Hardware Description Language 456 a AHDL gadgets70 OUTPUT VHDL gadgets OUT BITVECTOR 7 DOWNTO 0 b AHDL buzzer OUTPUT VHDL buzzer OUT BIT c AHDL altitude150 INPUT VHDL altitude IN INTEGER RANGE 0 TO 65535 d AHDL VARIABLE wire2 NODE VHDL SIGNAL wire2 BIT 457 a AHDL H98 B10011000 152 VHDL X98 B10011000 152 b AHDL H254 B1001010100 596 VHDL X254 B1001010100 596 c AHDL H3C4 B1111000100 964 VHDL X3C4 B1111000100 964 458 SUBDESIGN hw inbits30 INPUT outbits30 OUTPUT ENTITY hw IS Port inbits IN BITVECTOR 3 downto 0 outbits OUT BITVECTOR 3 downto 0 END hw AHDL outbits3 inbits1 outbits2 inbits3 outbits1 inbits0 outbits0 inbits2 VHDL outbits3 inbits1 outbits2 inbits3 outbits1 inbits0 outbits0 inbits2 459 TABLE abc y 000 0 001 0 010 1 011 1 100 1 101 0 110 1 111 1 END TABLE 460 BEGIN IF digitalvalue 10 THEN z VCC output a 1 ELSE z GND output a 0 END IF END WITH inbits SELECT y 0 WHEN 000 0 WHEN 001 1 WHEN 010 1 WHEN 011 1 WHEN 100 0 WHEN 101 1 WHEN 110 1 WHEN 111 ARCHITECTURE truth OF fig455 IS BEGIN PROCESS digitalvalue BEGIN IF digitalvalue 5 AND digitvalue 12 THEN z 1 ELSE z 0 END IF END PROCESS END truth NOTE The digitalvalue0 term drops out when this is simplified The compiler will issue a warning to this effect 464 a SUBDESIGN fig460 a b c INPUT define inputs to block y OUTPUT define outputs VARIABLE status20 NODE holds state of cold moderate hot BEGIN status a b c link input bits in order CASE status IS WHEN b010 y VCC WHEN b011 y VCC WHEN b111 y VCC WHEN OTHERS y GND END CASE END 464 b ENTITY fig461 IS port a b c IN bit declare 3 bits input y OUT BIT END fig461 ARCHITECTURE copy OF fig461 IS SIGNAL status BITVECTOR 2 downto 0 BEGIN status a b c link bits in order PROCESS status BEGIN CASE status IS WHEN 010 y 1 WHEN 011 y 1 WHEN 111 y 1 WHEN OTHERS y 0 END CASE END PROCESS END copy 465 SPQR 466 P D3D2D0D1 467 a Twodimensional form of a truth table used to simplify a sumofproducts expression b Logic expression consisting of two or more AND terms products that are ORed together c Logic circuit that produces an even or odd parity bit for a given set of input data bits d Group of eight 1s that are adjacent to each other within a Karnaugh map e Logic circuit that controls the passage of an input signal through to the output f Situation when a circuits output level for a given set of input conditions can be assigned as either a 1 or 0 g Input signal that is left disconnected in a logic circuit h Whenever a logic voltage level of a particular logic family falls out of the required range of voltages for either a logic 0 or logic 1 i Signal contention is when two signals are fighting each other j Programmable Logic Device k The TTL TransistorTransistorLogic family is the major family of bipolar digital ICs l The CMOS Complementary Metal Oxide Semiconductor family belongs to the class of unipolar digital ICs 468 RAM 000000002 111011112 0016 EF16 IO 111100002 F016 ROM 111100012 111111112 F116 FF16 469 CHAPTER FIVE FlipFlops and Related Devices 51 52 Same Q output as 51 53 54 55 One possibility 56 The response shown would occur If the NAND latch is not working as a FlipFlop A permanent logic HIGH at IC Z14 will prevent the latch from working properly and therefore the switch bounce will appear at Z16 When the 1 KHz squarewave is high the switch bounce will be present at Z26 57 Control inputs have to be stable for tS20ns prior to the clock transition 58 The FF will respond at times b d f h j corresponding to negativegoing CLK transitions 59 Assuming that Q0 initially for the positive edge triggered SC FF Assuming that Q0 initially for the negative edge triggered SC FF 510 a b c 511 FF can change state only at points b d f h j based on values of J and K inputs 512 a Connect the J and K inputs permanently HIGH The Q output will be a squarewave with a frequency of 5 KHz b The Q output will be a squarewave with a frequency of 25 KHz 513 CLK J K a Q b Q 514 a Since the FF has tH0 the FF will respond to the value present on the D input just prior to the NGT of the clock CLK Input Data Q b Connect Q to the D input of a second FF and connect the clock signal to the second FF The output of the second FF will be delayed by 2 clock periods from the Input Data 515 a CLK D Q b CLK D Q 516 Q is a 500 Hz square wave 517 a EN D Q b EN D Q 518 D CLK Q latch Q FF 519 If Q is connected back to D the Q and Q outputs will oscillate while CLK is HIGH This is because Q 1 will produce S0 C1 which will make Q 0 This Q 0 then will make S1 C0 which will make Q 1 520 JK1 so FF will toggle on each CLK negativegoing edge unless either PRESET or CLEAR inputs is LOW CLK CLEAR PRESET Q 521 CLK PRE CLR Q 522 CLK CLEAR PRESET Q