Microprocessador Superescalar MIPS em VerilogHDL - Trabalho Pratico

26112023 1907 Trabalho Prático httpspucminasinstructurecomcourses170059assignments814322moduleitemid3729189 13 Trabalho Prático Vencimento Sem prazo de entrega Pontos 0 Enviando um upload de arquivo Iniciar tarefa Trabalho Prático Microprocessador Superescalar com Pipeline de Instruções em VerilogHDL baseado na Arquitetura MIPS Observação Grupos de 4 alunos Objetivos Principais 1 Desenvolvimento Profundo Projetar e construir um microprocessador superescalar utilizando a linguagem VerilogHDL que empregue técnicas avançadas de pipeline de instruções 2 Otimização de Performance Maximizar a taxa de instruções por ciclo IPC ao implementar estratégias para lidar com hazards decorrentes do paralelismo 3 Compreensão Teórica Reforçar a compreensão dos princípios da arquitetura MIPS e das técnicas superescalares ao aplicálos em um projeto prático Detalhamento do Projeto 1 Definição do Conjunto de Instruções Será implementado o subconjunto de instruções descrito em especificação httpspucminasinstructurecomcourses170059files9964428wrap1 httpspucminasinstructurecomcourses170059files9964428downloaddownloadfrd1 Estude e compreenda os formatos das instruções designadas Rtype Itype Jtype 2 Esquematização da Arquitetura Elabore um diagrama de blocos do microprocessador destacando os principais componentes como Unidade de Controle ALU conjuntos de registradores e memória Detalhe o design do pipeline superescalar indicando os estágios e o mecanismo de tratamento de hazard de instruções 3 Codificação em Verilog Implemente de forma modular cada componente identificado no diagrama usando VerilogHDL 26112023 1907 Trabalho Prático httpspucminasinstructurecomcourses170059assignments814322moduleitemid3729189 23 Integre os módulos para compor o microprocessador garantindo a funcionalidade do pipeline superescalar e do controle de hazard de instruções Adote estratégias para gerenciar hazards potenciais seja de dados controle ou estruturais 4 Simulação e Testes Elabore um testbench robusto para simular o microprocessador validando seu desempenho e correção Submeta o subconjunto de instruções a diferentes cenários para garantir a resiliência e precisão do design 5 Documentação Detalhada Produza uma documentação consistente descrevendo a arquitetura os componentes a lógica de implementação e as decisões de design tomadas Relate os resultados das simulações interpretandoos e tirando conclusões relevantes 6 Apresentação Final Organize uma apresentação didática e interativa para exibir o funcionamento do microprocessador superescalar à classe e ao professor online Demonstre em tempo real a performance do microprocessador usando o testbench evidenciando a eficiência da reordenação de instruções online Critérios de Avaliação A avaliação levará em consideração a precisão e eficiência do microprocessador a qualidade do código em Verilog a profundidade da documentação e a clareza da apresentação Dicas Mantenha o foco na gestão de dependências entre instruções Utilize ferramentas de simulação para aprimorar constantemente seu código Valorize o trabalho em equipe promovendo debates e trocas de conhecimento Recorra a referências externas como artigos e tutoriais para aprofundar seu entendimento sobre técnicas superescalares e Verilog Pense em incrementar seu processador para suportar reordenação de instruções Sugestão de etapas de implementação 1 Implemente um processador singlecycle com as seguintes instruções addi sw lw add and andi or ori nor sll srl mul 2 Incremente seu processador do passo 1 implementando as seguintes instruções adicionais j beq bne slt jal jr 3 Modifique o processador do passo 2 para lidar com pipeline deixando a cargo de instruções nop a resolução de hazards 4 Modifique seu pipeline para que ele possa detectar hazard do tipo RAW e paralise o pipeline ou seja insira bolhas como resultado 26112023 1907 Trabalho Prático httpspucminasinstructurecomcourses170059assignments814322moduleitemid3729189 33 Prazo de Entrega No cronograma da disciplina Desejamos um processo de aprendizado rico e uma implementação bemsucedida General architecture for the MIPS Computer Figure 1 Overall architecture of the MIPS processor The MIPS computer consist of the following A 32bit processor CPU A memory module that consists of a RAM and memorymapped IO The RAM consists of 256 32bit words mapped to address 0 and is initialized with a mif file that contains the program that will execute Use the Altera 1Port RAM megafunction called altsyncram in earlier versions The RAM uses wordaligned addresses so you will need to remove the lower two bits of the 32bit address when connecting to the RAM In other words for a 256word RAM the RAM address input would connect to 9 downto 2 of the 32bit address We arent implementing loadstore byte instructions but if we did you would use the lower two bits to select which of the 4 bytes of the 32bit word to use The IO ports consist of two 32bit input ports and one 32bit output port with the following addresses The output port is connected to the four 7segment LEDs INPORT0 0000FFF8 INPORT1 0000FFFC Eg lw s1 FFFCzero means s1INPORT1 OUTPORT 0000FFFC Eg sw s1 FFFCzero means OUTPORT s1 General architecture for the MIPS Computer Figure 1 Overall architecture of the MIPS processor The MIPS computer consist of the following A 32bit processor CPU A memory module that consists of a RAM and memorymapped IO The RAM consists of 256 32bit words mapped to address 0 and is initialized with a mif file that contains the program that will execute Use the Altera 1Port RAM megafunction called altsyncram in earlier versions The RAM uses wordaligned addresses so you will need to remove the lower two bits of the 32bit address when connecting to the RAM In other words for a 256word RAM the RAM address input would connect to 9 downto 2 of the 32bit address We arent implementing loadstore byte instructions but if we did you would use the lower two bits to select which of the 4 bytes of the 32bit word to use The IO ports consist of two 32bit input ports and one 32bit output port with the following addresses The output port is connected to the four 7segment LEDs INPORT0 0000FFF8 INPORT1 0000FFFC Eg lw s1 FFFCzero means s1INPORT1 OUTPORT 0000FFFC Eg sw s1 FFFCzero means OUTPORT s1 Each input port will share the 9 switches which means that you can only specify the lower 9 bits of data loaded through the ports Because the ports share the same switches you can only specify one port at a time The 10th switch will be used to specify which port is loaded To load a value into each port you will use one of the two buttons as an enable signal for the input ports For example you would set the lower 9 switches for the desired value on INPORT0 set the 10th switch to low to select INPORT0 then press the enable button which should store the switch settings to a register the upper 23 bits should be set to 0 Note that you are responsible for determining the appropriate enable logic You would do the same thing for INPORT1 but you would need to set the 10th switch to high Reset for the CPU and memory is controlled by the second button Note that this reset should not reset the input ports in your circuit This separate reset is used to restart an application after changing the values of the input ports A processor would normally not be design this way but we have to work around the limited switches and buttons on the board General architecture for the MIPS Figure 2 General architecture of the MIPS CPU see included files for more detailed view The datapath the main rectangle in the middle of Figure 2 consists of ALU performs all the necessary arithmeticlogicshift operations required to implement the MIPS instruction set see instruction set table at end of this document The ALU also implements the conditions needed for branches and asserts the Branch Taken output if the condition is true The ALU should have four inputs two for the inputs to be processed one for a shift amount shown as IR106 and one for the operation select You can use whatever select values you want for the operations but I would recommend looking over the encoding of the rtype instructions first to simplify the logic Register File 32 registers with two read ports and one write port IR The Instruction Register IR holds the instruction once it is fetched from memory PC The Program Counter PC is a 32bit register that contains the memory address of the next instruction to be executed Some specialpurpose registers including Data Memory Register RegA RegB ALUout HI and LO These will be explained in lecture Controller which controls all the datapath and the memory module The controller does not control writing to the input ports Note that the ALU is controlled by a separate ALU Control unit that uses signals from both the main controller and the datapath This will be explained in lecture The design of the controllers is one of the main tasks of this project You are welcome to add more control signals that are not shown in the datapath figure ALU Controller controls the all the ALU Operations This logic is up to you to figure out but it will become more clear after discussing the instructions in lecture Memory contains the RAM and memorymapped IO ports Sign Extended convert a signed 16bit input to its 32bit representation when the signal isSigned is asserted The controller signals PCWrite enables the PC register PCWriteCond enables the PC register if the Branch signal is asserted IorD select between the PC or the ALU output as the memory address MemRead enables memory read MemWrite enables memory write MemToReg select between Memory data register or ALU output as input to write data signal IRWrite enables the instruction register JumpAndLink when asserted s31 will be selected as the write register IsSigned when asserted Sign Extended will output a 32bit sign extended representation of 16bit input PCSource select between the ALU output ALU OUT Reg or a shifted to left PC as an input to PC ALUOp used by the ALU controller to determine the desired operation to be executed by the ALU It is up to you to determine how to use this signal There are many possible ways of implementing the required functionality ALUSrcA select between RegA or Pc as the input1 of the ALU ALUSrcB select between RegB 4 IR150 or shifted IR150 as the input2 of the ALU RegWrite enables the register file RegDst select between IR2016 or IR1511 as the input to the Write Reg Other signals IR3126 the OPCode Will be decoded by the controller to determine what instruction to execute IR50 If the instruction is as Rtype this signal will be decoded by the ALU controller to determine the desired operation to be executed by the ALU IR106 For shift instructions this set of bits specifies the shift amount Other IR ranges are instruction specific and will be explained in lecture OPSelect will be used by the ALU to execute the desired operation LoadHI enables the HI register LoadLO enables the LO register AluLOHI select between ALU out LO or Hi as the write data of register file Branch gets asserted if the branch condition is true Opcode fetch decode execute cycle for the CPU controller Note This figure is not the complete It is also for a different version of the datapath and a different set of instructions so you cant use the exact same logic It is intended to be a basic template for you to follow You can add more states and signals as necessary Note that the timing or your design may also differ Source Patterson and Hennessy Computer Organization and Design The HardwareSoftware Interface 3rd ed Figure 3 General algorithm for designing a MIPS CPU Execution steps All instructions Step 1 Fetch instruction store in IR PC PC 4 Step 2 Decode instruction Look ahead steps Read in rs and rt registers to A and B respectively Compute target branch address using lower 16 bits of instruction ALUOut Memory access Step 3 Compute memory address Step 4 If lw Retrieve data from memory at specified address and place in MDR If sw Write data B register to memory at specified address Step 5 lw only Write contents of MDR to specified register Rtype Step 3 Perform specified operation ALUOut Step 4 Write ALUOut contents to specified register Branch Step 3 Compare two registers Use ZeroBranch output to determine if they are equal Determine if we branch to the address in ALUOut or to PC4 Selected Subset of MIPS Instructions See Excel sheet for more details Instruction OpCode Hex Type Example Meaning add unsigned 0x00 R addu s1 s2 s3 s1 s2 s3 add immediate unsigned 0x09 I addiu s1 s2 IMM s1 s2 IMM sub unsigned 0x00 R subu s1 s2 s3 s1 s2 s3 sub immediate unsigned 0x10 not MIPS I subiu s1 s2 IMM s1 s2 IMM mult 0x00 R mult s t HILO s t mult unsigned 0x00 R multu s t HILO s t and 0x00 R and s1 s2 s3 s1 s2 and s3 andi 0x0C I andi s1 s2 IMM s1 s2 and IMM or 0x00 R or s1 s2 s3 s1 s2 or s3 ori 0x0D I ori s1 s2 IMM s1 s2 or IMM xor 0x00 R xor s1 s2 s3 s1 s2 xor s3 xori 0x0E I xori s1 s2 IMM s1 s2 xor IMM srl shift right logical 0x00 R srl s1 s2 H s1 s2 H H is bits 106 of IR sll shift left logical 0x00 R sll s1 s2 H s1 s2 H H is bits 106 of IR sra shift right arithmetic 0x00 R sra s1 s2 H See XLS sheet slt set on less than signed 0x00 R slt s1s2 s3 s11 if s2 s3 else s10 slti set on less than immediate signed 0x0A I slti s1s2 IMM s11 if s2 IMM else s10 sltiu set on less than immediate unsigned 0x0B I sltiu s1s2 IMM s11 if s2 IMM else s10 sltu set on less than unsigned 0x00 R sltu s1s2 s3 s11 if s2 s3 else s10 mfhi move from Hi 0x00 R mfhi s1 s1 HI mflo move from LO 0x00 R mflo s1 s1 LO load word 0x23 I lw s1 offsets2 s1 RAMs2offset store word 0x2B I sw s1 offsets2 RAMs2offset s1 branch on equal 0x04 I beq s1s2 TARGET if s1s2 PC 4TARGET branch not equal 0x05 I bne s1s2 TARGET if s1s2 PC 4TARGET Branch on Less Than or Equal to Zero 0x06 I blez s1 TARGET if s1 0 PC 4TARGET Branch on Greater Than Zero 0x07 I bgtz s1 TARGET if s1 0 PC 4TARGET Branch on Less Than Zero 0x01 I bltz s1 TARGET if s1 0 PC 4TARGET Branch on Greater Than or Equal to Zero 0x01 I bgez s1 TARGET if s1 0 PC 4TARGET jump to address 0x02 J j TARGET PC TARGET jump and link 0x03 J jal TARGET ra PC4 and PC TARGET jump register 0x00 R jr ra PC ra Fake instruction 0x3F Halt Useful for week 2 deliverables